TI TSM102

TSM102,, TSM102A
DUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,
AND VOLTAGE REFERENCE
www.ti.com
SLVS602 – MARCH 2006
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
OPERATIONAL AMPLIFIERS
– Low Supply Current…200 µA/A
– Medium Speed…2.1 MHz
– Low-Level Output Voltage Close to
VCC–…0.1 V Typ (RL = 10 kΩ)
– Input Common-Mode Voltage Range
Includes Ground
COMPARATORS
– Low Supply Current…200 µA/A
(VCC = 5 V)
– Input Common-Mode Voltage Range
Includes Ground
– Low Output Saturation Voltage…
Typically 250 mV (Isink = 4 mA)
VOLTAGE REFERENCE
– Adjustable Output Voltage…VREF to 36 V
– Sink Current Capability…1 mA to 100 mA
– 0.4% (A Grade) and 1% (Standard Grade)
Precision
– Latch-Up Immunity
•
•
Switch-Mode Power Supplies
Battery Chargers
Voltage and Current Sensing
Power-Good, Overvoltage, Undervoltage,
Overcurrent Detection
Window Comparators
Alarms, Detectors, and Sensors
D (SOIC) OR PW (TSSOP) PACKAGE
(TOP VIEW)
1OUT 1
COMP
COMP
1IN− 2
16 4OUT
15 4IN−
– +
+
–
1IN+ 3
14 4IN+
VCC+ 4
13 VCC–
12 3IN+
2IN+ 5
–
2IN− 6
2OUT 7
AMP
+
+
–
AMP
11 3IN−
10 3OUT
VREF 8
9 CATHODE
DESCRIPTION/ORDERING INFORMATION
The TSM102 and TMS102A combine the building blocks of a dual operational amplifier, a dual comparator, and
a precision voltage reference, all of which often are used to implement a wide variety of power-management
functions, including overcurrent detection, undervoltage/overvoltage detection, power-good detection, window
comparators, error amplifiers, etc. Additional applications include alarm and detector/sensor applications.
The TSM102A offers a tight VREF tolerance of 0.4% at 25°C. The TSM102 and TSM102A are characterized for
operation from –40°C to 85°C.
ORDERING INFORMATION
TA
MAX VREF
TOLERANCE (25°C)
PACKAGE (1)
SOIC – D
A grade:
0.4% precision
TSSOP – PW
–40°C to 85°C
SOIC – D
Standard grade:
1% precision
TSSOP – PW
(1)
ORDERABLE PART NUMBER
Tube of 75
TSM102AID
Reel of 2500
TSM102AIDR
Tube of 90
TSM102AIPW
Reel of 2000
TSM102AIPWR
Tube of 75
TSM102ID
Reel of 2500
TSM102IDR
Tube of 90
TSM102IPW
Reel of 2000
TSM102IPWR
TOP-SIDE MARKING
TSM102AI
SN102AI
TSM102I
SN102I
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
TSM102,, TSM102A
DUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,
AND VOLTAGE REFERENCE
www.ti.com
SLVS602 – MARCH 2006
Absolute Maximum Ratings (1)
over free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage
36
V
VID
Input differential voltage
36
V
VI
Input voltage range
IKA
Voltage reference cathode current
θJA
Package thermal impedance (2) (3)
TJ
Maximum junction temperature
Tstg
Storage temperature range
(1)
(2)
(3)
–0.3
D package
36
V
100
mA
73
PW package
°C/W
108
–65
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Selecting the maximum of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
MIN
MAX
3
UNIT
VCC+ – VCC–
Supply voltage
VID
Comparator differential input voltage
30
V
VCC+ – VCC–
VKA
Cathode-to-anode voltage
VREF
36
V
V
IK
Reference cathode current
1
100
mA
TA
Operating free-air temperature
–40
85
°C
Total Device Electrical Characteristics
PARAMETER
ICC
2
Total supply current,
excluding reference cathode current
TEST CONDITIONS
VCC+ = 5 V, VCC– = 0 V, No load
Submit Documentation Feedback
TA
25°C
Full range
MIN
TYP
MAX
0.8
1.5
2
UNIT
mA
www.ti.com
TSM102,, TSM102A
DUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,
AND VOLTAGE REFERENCE
SLVS602 – MARCH 2006
Operational Amplifier Electrical Characteristics
VCC+ = 5 V, VCC– = GND, R1 connected to VCC/2 (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Input offset voltage drift
TEST CONDITIONS
TA
MIN
25°C
TYP
MAX
1
4.5
Full range
IIO
Input offset current
IIB
Input bias current
AVD
Large-signal voltage gain
VCC+ = 30 V, R1 = 10 kΩ,
VO = 5 V to 25 V
kSVR
Supply-voltage rejection ratio
VCC+ = 5 V to 30 V
6.5
25°C
10
25°C
5
Full range
25°C
20
100
200
25°C
50
Full range
25
mV
µV/°C
20
40
Full range
UNIT
100
nA
nA
V/mV
25°C
80
25°C
VCC–
100
VCC+ – 1.8
dB
Full range
VCC–
VCC+ – 2.2
VICM
Input common-mode voltage
CMRR
Common-mode rejection ratio
VCC+ = 30 V,
VICM = 0 V to VCC+ – 1.8 V
ISC
Short-circuit current
VID = ±1 V, VO = 2.5 V
VOH
High-level output voltage
VCC+ = 30 V, RL = 10 kΩ
VOL
Low-level output voltage
RL = 10 kΩ
SR
Slew rate
VCC = ±15 V, CL = 100 pF,
VI = ±10 V, RL = 10 kΩ
25°C
1.3
2
V/µs
GBW
Gain bandwidth product
RL = 10 kΩ, CL = 100 pF, f = 100 kHz
25°C
1.4
2.1
MHz
Φm
Phase margin
RL = 10 kΩ, CL = 100 pF
25°C
45
°
THD
Total harmonic distortion
25°C
0.01
%
Vn
Equivalent input noise voltage
25°C
19
25°C
Source
Sink
f = 1 kHz
Submit Documentation Feedback
70
90
3
6
3
6
25°C
27
28
Full range
26
25°C
25°C
130
Full range
V
dB
mA
V
170
200
mV
nV/√Hz
3
TSM102,, TSM102A
DUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,
AND VOLTAGE REFERENCE
www.ti.com
SLVS602 – MARCH 2006
Comparator Electrical Characteristics
VCC+ = 5 V, VCC– = GND (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
VID
Comparator differential
input voltage
IIO
Input offset current
IIB
Input bias current
IOH
High-level output current
TEST CONDITIONS
TA
MIN
TYP
5
Full range
9
Full range
VID = 1 V, VCC = VO = 30 V
MAX
25°C
VCC+
25°C
50
Full range
150
25°C
250
Full range
400
25°C
0.1
Full range
250
mV
V
nA
nA
nA
1
25°C
UNIT
400
µA
VOL
Low-level output voltage
VID = –1 V, Isink = 4 mA
AVD
Large-signal voltage gain
VCC+ = 15 V, R1 = 15 kΩ,
VO = 1 V to 11 V
25°C
Isink
Output sink current
VO = 1.5 V, VID = –1 V
25°C
6
VICM
Input common-mode
voltage range
25°C
0
VCC+ – 1.5
Full range
0
VCC+ – 2
tRESP
Response time (1)
R1 = 5.1 kΩ to VCC+, VREF = 1.4 V
25°C
1.3
µs
Large-signal response time
R1 = 5.1 kΩ to VCC+, VREF = 1.4 V,
VI = TTL
25°C
300
ns
tRESP,large
(1)
4
Full range
700
mV
200
V/mV
16
mA
V
The response-time specification is for 100-mV input step with 5-mV overdrive. For larger overdrive signals, 300 ns can be obtained.
Submit Documentation Feedback
TSM102,, TSM102A
DUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,
AND VOLTAGE REFERENCE
www.ti.com
SLVS602 – MARCH 2006
Voltage-Reference Electrical Characteristics
PARAMETER
TEST CONDITIONS
TSM102
TA
VKA = VREF, IK = 10 mA,
See Figure 1
MIN
TYP
MAX
25°C
2.475
2.5
2.525
25°C
2.49
2.5
2.51
VREF
Reference voltage (1)
∆VREF
Reference input voltage deviation
over temperature range (1)
VKA = VREF, IK = 10 mA,
See Figure 1
Full range
7
30
DVREF
DT
Average temperature coefficient of
reference input voltage (2)
VKA = VREF, IK = 10 mA
Full range
±22
±100
DVREF
DVKA
Ratio of change in reference voltage
to change in cathode voltage
VKA = 3 V to 36 V, IK = 10 mA,
See Figure 2
25°C
–1.1
–2
IREF
Reference input current
IK = 10 mA, R1 = 10 kΩ, R2 = ∞,
See Figure 2
25°C
1.5
2.5
∆IREF
Reference input current deviation
over temperature range
IK = 10 mA, R1 = 10 kΩ, R2 = ∞,
See Figure 2
Imin
Minimum cathode current
for regulation
IK,OFF
Off-state cathode current
(1)
(2)
TSM102A
Full range
UNIT
V
mV
ppm/°C
3
mV/V
µA
Full range
0.5
1
µA
VKA = VREF, See Figure 1
25°C
0.5
1
mA
See Figure 3
25°C
180
500
nA
∆VREF is defined as the difference between the maximum and minimum values obtained over the full temperature range.
∆VREF = VREF(MAX) – VREF(MIN)
The temperature coefficient is defined as the slopes (positive and negative) of the voltage vs temperature limits within which the
reference voltage is specified.
–n
VREF(MAX)
pp
m/
C
°
pm/
+n p
°C
MAX
2.5 V
MIN
VREF(MIN)
T1
T2
Temperature
Temperature
25°C
Submit Documentation Feedback
5
TSM102,, TSM102A
DUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,
AND VOLTAGE REFERENCE
www.ti.com
SLVS602 – MARCH 2006
PARAMETER MEASUREMENT INFORMATION
Input
VKA
IK
VREF
Figure 1. Test Circuit for VKA = VREF
VKA
Input
VKA = VREF (1 + (R1/R2)) + (IREF × R1)
IK
R1
IREF
R2
VREF
Figure 2. Test Circuit for VKA > VREF
VKA
Input
IOFF
Figure 3. Test Circuit for IOFF
6
Submit Documentation Feedback
TSM102,, TSM102A
DUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,
AND VOLTAGE REFERENCE
www.ti.com
SLVS602 – MARCH 2006
TYPICAL CHARACTERISTICS
AMPLIFIER TOTAL HARMONIC DISTORTION
vs
FREQUENCY
AMPLIFIER NOISE VOLTAGE
vs
FREQUENCY
400
350
0.1
nV/ÖHz
Voltage Noise – nV/rtHz
THD – Total Harmonic Distortion – %
1
0.01
0.001
300
250
200
150
100
50
0.0001
100
100
0
10k
10000
1k
1000
100k
100000
10
100
f – Frequency – Hz
Figure 4.
Figure 5.
GAIN AND PHASE
vs
FREQUENCY
VREF STABILITY
vs
CAPACITANCE
180
50
140
40
Phase
30
100
60
10
-20
0
-60
-10
-100
-20
-140
25
Current – mA
20
Gain
100000
100k
35
Phase – deg
Gain – dB
30
10000
10k
f – Frequency – Hz
60
20
1000
1k
20
15
10
-30
1k
1.E+03
10k
1.E+04
100k
1.E+05
1M
1.E+06
f – Frequency – Hz
-180
10M
1.E+07
5
0
1
10
100
1000
10000
Capacitance – pF
Figure 6.
Figure 7.
Submit Documentation Feedback
7
TSM102,, TSM102A
DUAL OPERATIONAL AMPLIFIER, DUAL COMPARATOR,
AND VOLTAGE REFERENCE
www.ti.com
SLVS602 – MARCH 2006
TYPICAL CHARACTERISTICS (continued)
VREF
vs
TEMPERATURE
2.515
IO = 100 mA
2.510
2.505
VREF – V
2.500
IO = 10 mA
2.495
2.490
IO = 1 mA
2.485
2.480
–40 –25
–10
5
20
35
50
65
80
Temperature – °C
Figure 8.
8
Submit Documentation Feedback
95
110 125
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TSM102AID
ACTIVE
SOIC
D
16
TSM102AIDR
ACTIVE
SOIC
D
16
TSM102AIPW
ACTIVE
TSSOP
PW
16
TSM102AIPWR
ACTIVE
TSSOP
PW
16
TSM102ID
ACTIVE
SOIC
D
16
TSM102IDR
ACTIVE
SOIC
D
16
TSM102IPW
ACTIVE
TSSOP
PW
16
TSM102IPWR
ACTIVE
TSSOP
PW
16
40
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
90
40
90
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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