SY89230U 3.2GHz Precision, LVPECL ÷3, ÷5 Clock Divider General Description The SY89230U is a precision, low jitter 3.2GHz ÷3, ÷5 clock divider with a LVPECL output. The differential input includes Micrel’s unique, 3-pin internal termination architecture that allows the input to interface to any differential signal (AC- or DCcoupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. The outputs are 800mV, 100Kcompatible LVPECL with fast rise/fall times guaranteed to be less than 200ps. The SY89230U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. The SY89230U is part of Micrel’s high-speed, Precision ® Edge product line. All support documentation can be found on Micrel’s web site at: www.micrel.com. Block Diagram Precision Edge ® Features • Accepts a high-speed input and provides a precision ÷3 and ÷5 sub-rate, LVPECL output • Guaranteed AC performance over temperature and supply voltage: – DC-to >3.2GHz throughput – < 850ps Propagation Delay (In-to-Q) – < 200ps Rise/Fall times • Ultra-low jitter design: – <1psRMS random jitter – <1psRMS cycle-to-cycle jitter – <10psPP total jitter (clock) – <0.7psRMS MUX crosstalk induced jitter • Unique patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS) • Wide input voltage range VCC to GND • 800mV LVPECL output • 45% to 55% Duty Cycle (÷ 3) • 47% to 53% Duty Cycle (÷ 5) • 2.5V ±5% or 3.3V ±10% supply voltage • -40°C to +85°C industrial temperature range • Available in 16-pin (3mm x 3mm) QFN package Applications • Fail-safe clock protection Markets • • • • LAN/WAN Enterprise servers ATE Test and measurement Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com November 2007 M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U Ordering Information(1) Part Number Package Type Operating Range SY89230UMG QFN-16 QFN-16 (2) SY89230UMGTR Package Marking Lead Finish Industrial 230U with Pb-Free bar-line Indicator NiPdAu Pb-Free Industrial 230U with Pb-Free bar-line Indicator NiPdAu Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals Only. 2. Tape and Reel. Pin Configuration 16-Pin QFN November 2007 2 M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U Pin Description Pin Number Pin Name Pin Function IN, /IN Differential Input: This input pair is the differential signal input to the device, which accepts AC- or DC-coupled signal as small as 100mV. The input internally terminates to a VT pin through 50Ω. Note that this input pair will default to an indeterminate state if left open. See “Input Interface Applications” subsection for more details. VT Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin. The VT pin provides a center-tap for the input (IN, /IN) to a termination network for maximum interface flexibility. See “Input Interface Applications” subsection for more details. VREF-AC Reference Voltage: This output biases to VCC–1.2V. It is used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01µF low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is ±0.5mA. For more details, see “Input Interface Applications” subsection. 5 EN Single-ended Input: This TTL/CMOS-compatible input disables and enables the output. It is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. When disabled, Q goes LOW and /Q goes HIGH. EN being synchronous, outputs will be enabled/disabled after a rising and a falling edge of the input clock. VTH = VCC/2. 6 /MR Single-ended Input: This TTL/CMOS-compatible input, when pulled LOW, asynchronously sets Q output LOW and /Q output HIGH. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open. VTH = VCC/2. 7 NC No Connect 8, 13 VCC Positive Power Supply: Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to the VCC pins as possible. 12, 9 Q, /Q Differential Output: The LVPECL output swing is typically 800mV and is terminated with 50Ω to VCC-2V. See the “Truth Table” below for the logic function. 10, 11, 14,15 GND, Exposed Pad Ground: Ground and exposed pad must be connected to a ground plane that is the same potential as the ground pins. DIV_SEL Single-ended Input: This TTL/CMOS-compatible input selects divide-by-3 when pulled LOW and divide-by-5 when pulled HIGH. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open. VTH = VCC/2. 1, 4 2 3 16 Truth Table Inputs November 2007 Outputs DIV_SEL EN /MR Q /Q X X 0 0 1 0 1 1 ÷3 ÷3 1 1 1 ÷5 ÷5 X 0 1 0 1 3 M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) .......................... –0.5V to +4.0V Input Voltage (VIN) ..................................–0.5V to VCC LVPECL Output Current (IOUT) .................................... Continuous ................................................. 50mA Surge ........................................................ 100mA Current (VT) Source or sink current on VT…………±100mA Input Current Source or sink current on (IN, /IN) ........... ±50mA Current (VREF-AC) (4) Source/Sink Current on VREF-AC ............ ±0.5mA Maximum Operating Junction Temperature…..125°C Lead Temperature (soldering, 20 sec.) .......... +260°C Storage Temperature (Ts) ..................–65°C to 150°C Supply Voltage (VCC).................. +2.375V to +2.625V ......................................................+3.0V to +3.6V Ambient Temperature (TA) ................ –40°C to +85°C (3) Package Thermal Resistance QFN (θ JA) Still-Air ..................................................... 75°C/W QFN (ψ JB) Junction-to-Board………………………….33°C/W DC Electrical Characteristics(5) TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter VCC Power Supply Condition Min Typ Max Units 2.375 3.0 2.5 3.3 2.625 3.6 V V ICC Power Supply Current 62 85 mA RIN Input Resistance (IN-to-VT) No load, max VCC 45 50 55 Ω RDIFF_IN Differential Input Resistance (IN-to-/IN) 90 100 110 Ω VIH Input High Voltage (IN, /IN) 1.2 VCC V VIL Input Low Voltage (IN, /IN) 0 VIH–0.1 V VIN Input Voltage Swing (IN, /IN) See Figure 2a. Note 6. 0.1 VCC V VDIFF_IN Differential Input Voltage Swing |IN-/IN| See Figure 2b. 0.2 VREF-AC Output Reference Voltage VT_IN Voltage from Input to VT VCC–1.3 V VCC–1.2 VCC–1.1 V 1.8 V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and ψJB values are determined for a 4-layer board in still air unless otherwise stated. 4. Due to limited drive capability use for input of the same package only. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIN (max) is specified when VT is floating. November 2007 4 M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U LVPECL Outputs DC Electrical Characteristics(7) VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC-2V; TA = –40°C to + 85°C, unless otherwise stated. Symbol Parameter Max Units VOH Output HIGH Voltage Q, /Q Condition VCC-1.145 Min Typ VCC-0.895 V VOL Output LOW Voltage Q, /Q VCC-1.945 VCC-1.695 V VOUT Output Voltage Swing Q, /Q See Figure 2a. 550 800 950 mV VDIFF_OUT Differential Output Voltage Swing Q, /Q See Figure 2b. 1100 1600 mV LVTTL/CMOS DC Electrical Characteristics(7) VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C, unless otherwise stated. Symbol Parameter VIH Input HIGH Voltage Condition Min Typ Max 2.0 VIL Input LOW Voltage IIH Input HIGH Current -125 IIL Input LOW Current -300 Units V 0.8 V 30 µA µA Note: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. November 2007 5 M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U AC Electrical Characteristics(8) VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC-2V; TA = –40°C to + 85°C, unless otherwise stated. Symbol Parameter Condition Min fMAX Maximum Input Operating Frequency VOUT ≥ 200mV 3.2 tw Minimum Pulse Width IN, /IN 140 tpd Differential Propagation Delay Typ Max Units GHz ps 450 650 850 250 450 650 ps In-to-Q /MR(H-L)-to-Q tRR Reset Recovery Time tS EN Set-up Time tH EN Hold Time tskew Part-to-Part Skew tJITTER Clock 400 ps EN-to-IN Note 9 50 ps IN-to-EN Note 9 250 ps Note 10 300 ps Random Jitter Note 11 1 psRMS Cycle-to-Cycle Jitter Note 12 1 psRMS Total Jitter tr, tf ps /MR(L-H)-to-IN 10 psPP Output Rise/Fall Time (20% to 80%) At full output swing. Note 13 90 200 ps Output Duty Cycle(÷ 3) Duty Cycle(input): 50%; f ≤3.2GHz, Note 14 46 54 % Output Duty Cycle(÷ 5) Duty Cycle(input): 50%; f ≤3.2GHz, Note 14 47 53 % Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold do not apply. 10. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 11. Random Jitter is measured with a K28.7 character pattern, measured at <fMAX. 12. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the output signal. 13. Total Jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. 14. For Input Duty Cycle different from 50%, see “Output Duty Cycle Equation” in “Functional Description” subsection. November 2007 6 M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U The Enable function operates as follows: Functional Description 1. The enable/disable function is synchronous so that the clock outputs will be enabled following a rising and a falling edge of the input clock when switching from EN=LOW to EN=HIGH. Output Duty Cycle Equation For a non 50% input, derate the spec by: Divide by 3: 1+ (0.5 - X 100 ) x100, in % 3 However, when switching from EN=HIGH to EN=LOW, the clock outputs will be disabled following an input clock rising edge and an output clock falling edge. Divide by 5: X 100 (0.5 ) x100, in % 5 X = input Duty Cycle, in % 2+ 2. The enable/disable function always guarantees the full pulse width at the output before the clock outputs are disabled, non-depending on the divider ratio. Refer to Figure 1b for examples. Example: if a 45% input duty cycle is applied or X=45, in divide by 3 mode, the spec would expand by 1.67% to 44.3%-55.7% Divider Operation The divider operation uses both the rising and falling edge of the input clock. For divide by 3, the falling edge of the second input clock cycle will determine the falling edge of the output. For divide by 5, the falling edge of the third input clock cycle. Refer to Figure 1c. Enable (EN) EN is a synchronous TTL/CMOS-compatible input that enables/disables the outputs based on the input to this pin. Internal 25k Ω pull -up resistor defaults the input to logic HIGH if left open. Input switching threshold is VCC/2. November 2007 7 M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U Timing Diagrams Figure 1a. Propagation Delay November 2007 8 M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U Figure 1b. Enable Output Timing Diagram Examples (divide by 3) November 2007 9 M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U Figure 1c. Divider Operation Timing Diagram November 2007 10 M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U Typical Operating Characteristics VCC = 3.3V, GND = 0V, tr / tf ≤ 300ps, RL = 50Ω to VCC–2V; TA = 25°C, unless otherwise stated. Functional Characteristics VCC = 2.5V, GND = 0V, VIN = 100mV, Q = Divide by 3, tr/tf ≤ 300ps, RL = 50Ω to VCC-2V; TA = 25°C, unless otherwise stated. November 2007 11 M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U Single-Ended and Differential Swings Figure 2b. Differential Voltage Swing Figure 2a. Single-Ended Voltage Swing Input and Output Stages Figure 3b. Simplified Differential Output Stage Figure 3a. Simplified Differential Input Stage November 2007 12 M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U Input Interface Applications Option: may connect VT to VCC Figure 4a. LVPECL Interface (DC-Coupled) Figure 4b. LVPECL Interface (AC-Coupled) Figure 4d. CML Interface (AC-Coupled) Figure 4e. LVDS Interface (DC-Coupled) November 2007 13 Figure 4c. CML Interface (DC-Coupled) M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U PECL Output Interface Applications PECL has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low EMI. PECL is ideal for driving 50Ω- and 100Ω-controlled impedance transmission lines. There are several techniques for terminating the PECL output: parallel termination-thevenin equivalent, parallel termination (3-resistor), and ACcoupled termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced. Figure 5b. Parallel Termination (3-Resistor) Figure 5a. Parallel Termination-Thevenin Equivalent Related Product and Support Documentation Part Number Function SY89228U 1GHz Precision, LVPECL ÷3, ÷5 Clock Divider with Fail-Safe Input and Internal Termination SY89229U 1GHz Precision, LVDS ÷3, ÷5 Clock Divider with Fail-Safe Input and Internal Termination SY89231U 3.2GHz Precision, LVDS ÷3, ÷5 Clock Divider HBW Solutions New Products and Applications November 2007 Datasheet Link www.micrel.com/product-info/products/solutions.shtml 14 M9999-110507-A [email protected] or (408) 955-1690 Micrel, Inc. SY89230U Package Information 16-Pin QFN Packages Notes: 1. Package meets Level 2 Moisture Sensitivity Classification. 2. All parts are dry-packed before shipment. 3. Exposed pad must be soldered to a ground for proper thermal management. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2007 Micrel, Inc. November 2007 15 M9999-110507-A [email protected] or (408) 955-1690