W78LE812 8-BIT MTP MICROCONTROLLER GENERAL DESCRIPTION The W78LE812 is an 8-bit microcontroller which can accommodate a wide range of supply voltages with low power consumption. The instruction set for the W78LE812 is fully compatible with the standard 8051. The W78LE812 contains an 8K bytes MTP ROM (Multiple-Time Programmable ROM); a 256 bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 6-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by a fourteen sources two-level interrupt capability. To facilitate programming and verification, the MTP-ROM inside the W78LE812 allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78LE812 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. FEATURES • Fully static design 8-bit CMOS microcontroller • Wide supply voltage of 2.4V to 5.5V • 256 bytes of on-chip scratchpad RAM • 8 KB electrically erasable/programmable MTP-ROM • 64 KB program memory address space • 64 KB data memory address space • Four 8-bit bi-directional ports • Three 16-bit timer/counters • Timer 2 Clock-out • One full duplex serial port(UART) • Watchdog Timer • Direct LED drive outputs • Fourteen sources, two-level interrupt capability • Wake-up via external interrupts at Port 1 • EMI reduction mode • Built-in power management • Code protection mechanism • Packages: − DIP 40: W78LE812-24 − PLCC 44: W78LE812P-24 − PQFP 44: W78LE812F-24 -1- Publication Release Date: February 1999 Revision A2 W78LE812 PIN CONFIGURATIONS 40-Pin DIP (W78LE812) INT2,,T2, P1.0 INT3,T2EX, P1.1 INT4,P1.2 INT5,P1.3 INT6,P1.4 INT7,P1.5 INT8,P1.6 INT9,P1.7 RST A9CTRL,RXD, P3.0 A13CTR,LTXD, P3.1 A14CTRL,INT0, P3.2 OECTRL,INT1, P3.3 T0, P3.4 T1, P3.5 CE,WR, P3.6 OE,RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 I N T 6 , P 1 . 4 INT7,P1.5 INT8,P1.6 INT9,P1.7 RST A9CTRL,RXD, P3.0 P4.3 A13CTRL,TXD, P3.1 A14CTRL,INT0, P3.2 OECTRL,INT1, P3.3 T0, P3.4 T1, P3.5 I N T 5 , P 1 . 3 I N T 4 , P 1 . 2 I N T 2 , T 2 , P 1 . 0 P 4 V . D 2 D A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 P 3 . 7 , / R D , / O E X T A L 2 X V P P T S 4 2 A S . . L 0 0 , 1 A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 EA,VPP ALE,P4.5 PSEN,P4.6 P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8 I N T 6 , P 1 . 4 A D 3 , P 0 . 3 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R , / C E P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 44-Pin PQFP (W78LE812F) 44-Pin PLCC (W78LE812P) I N T 3 , T 2 E X , P 1 . 1 VDD P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA,VPP P4.1 ALE,P4.5 INT7,P1.5 INT8,P1.6 INT9,P1.7 RST A9CTRL,RXD, P3.0 P4.3 A13CTRL,TXD, P3.1 PSEN,P4.6 P2.7, A15 P2.6, A14 P2.5, A13 A14CTRL,INT0, P3.2 OECTRL,INT1, P3.3 T0, P3.4 T1, P3.5 P 2 . 4 , A 1 2 I N T 4 , P 1 . 2 I N T 2 , T 2 , P 1 . 0 P 4 V . D 2 D A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 28 6 27 7 8 26 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 1 2 P 3 . 6 , / W R , / C E -2- I N T 5 , P 1 . 3 I N T 3 , T 2 E X , P 1 . 1 P 3 . 7 , / R D , / O E X T A L 2 X V P P P T S 4 2 2 A S . . . L 0 0 1 , , 1 A A 8 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA,VPP P4.1 ALE,P4.5 PSEN,P4.6 P2.7, A15 P2.6, A14 P2.5, A13 W78LE812 PIN DESCRIPTION SYMBOL EA PSEN ALE RST XTAL1 XTAL2 VSS VDD P0.0−P0.7 P1.0−P1.7 P2.0−P2.7 P3.0−P3.7 P4.0-P4.6 DESCRIPTIONS EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM address and data will not be present on the bus if EA pin is high and the program counter is within on-chip ROM area. Otherwise they will be present on the bus. PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0 address/data bus during fetch and MOVC operations. When internal ROM access is performed, no PSEN strobe signal outputs from this pin. This pin also serves the alternative function P4.6. ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. This pin also serves the alternative function P4.5 RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external clock. CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1. GROUND: Ground potential POWER SUPPLY: Supply voltage for operation. PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order address/data bus during accesses to external memory. The pins of Port 0 can be individually configured to open-drain or standard port with internal pull-ups. PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate functions which are described below: T2(P1.0): Timer/Counter 2 external count input T2EX(P1.1): Timer/Counter 2 Reload/Capture control INT2−INT9 (P1.0−P1.7):External interrupt 2 to 9 PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. The pins P3.4 to P3.7 can be configured with high sink current which can drive LED displays directly. All bits have alternate functions, which are described below: RXD(P3.0) : Serial Port receiver input TXD(P3.1) : Serial Port transmitter output INT0 (P3.2) : External Interrupt 0 INT1(P3.3) : External Interrupt 1 T0(P3.4) : Timer 0 External Input T1(P3.5) : Timer 1 External Input WR (P3.6) :External Data Memory Write Strobe RD (P3.7) : External Data Memory Read Strobe PORT 4: A 6-bit bi-directional I/O port which is bit-addressable. Pins P4.0 to P4.3 are available on 44-pin PLCC/QFP package. Pins P4.5 and P4.6 are the alternative function corresponding to ALE and PSEN . -3- Publication Release Date: February 1999 Revision A2 W78LE812 BLOCK DIAGRAM P1.0 Port 1 Port 1 Latch P1.7 INT2~9 ACC B P0.0 Port 0 Interrupt T1 Latch T2 Port 0 P0.7 Timer 2 DPTR Timer 0 Stack Pointer PSW ALU Temp Reg. Timer 1 PC Incrementor UART Addr. Reg. P3.0 Port 3 Port 3 SFR RAM Address Instruction Decoder & Sequencer Latch P3.7 256 bytes RAM & SFR P2.0 Port 2 Latch Bus & Clock Controller P2.7 Port 4 Latch P4.0 Watchdog Timer Port 4 P4.6 Oscillator XTAL1 Port 2 XTAL2 Reset Block ALE PSEN RST Power control VCC Vss FUNCTIONAL DESCRIPTION The W78LE812 architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space. Timers 0, 1, and 2 Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of the W78LE812: it is a 16-bit up/down counter that is configured and controlled by the T2CON and T2MOD registers. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the -4- W78LE812 setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. In the auto-reload mode, Timer 2 performs a up counter which is similar with standard 8052. When counting up, an overflow in Timer 2 will cause a reload from RCAP2H and RCAP2L registers. The Timer 2 also provides a programmable clock-out mode as a clock generator. To enable this mode, timer 2 has to be configured with a 16-bit auto-reload timer (C/T2 = 0, CP/RL2 = 0) and bit T2OE (T2MOD.1) must be set to 1. This mode produces a 50% duty cycle clock output and timer 2 rollovers will not generate an interrupt. The clock-out frequency depends on the oscillator frequency and the reload value of registers RCAP2H and RCAP2L. The clock-out frequency is determined by following equation: Clock-out Frequency = Oscillator Frequency / [ 4 × ( 65536 - RCAP2H, RCAP2L ) ] OSC 1/2 TL2 TH2 T2 (P1.0) 1/2 TR2 (T2CON.2) T2EX (P1.1) RCAP2L RCAP2H Timer 2 Interrupt EXF2 EXEN2 (T2CON.3) T2CON.6 Timer 2 Clock-Out Mode TIMER 2 MODE CONTROL Bit: 7 6 5 4 3 2 1 0 - - - - - - T2OE - Mnemonic: T2MOD Address: C9h T2OE: Timer 2 Output Enable. This bit enables/disables the Timer 2 clock-out function. I/O Port Options The Port 0 and Port 3 of W78LE812 may be configured with different types by setting the bits of the Port Options Register POR that is located at 86H. The pins of Port 0 can be configured with either the open drain or standard port with internal pull-up. By the default, Port 0 is an open drain bidirectional I/O port. When the PUP bit in the POR register is set, the pins of Port 0 will perform a quasi-bi-directional I/O port with internal pull-up that is structurally the same as Port 2. The high nibble of Port 3 (P3.4 to P3.7) can be selected to serve the direct LED displays drive outputs by setting the HDx bit in the PO register. When the HDx bit is set, the corresponding pin P3.x can sink about 20mA current for driving LED display directly. After reset, the POR register is cleared and the pins of Ports 0 and 3 are the same as those of the standard 80C31. The POR register is shown below. -5- Publication Release Date: February 1999 Revision A2 W78LE812 Port Options Register Bit: 7 6 5 4 3 2 1 0 EP6 EP5 - HD7 HD6 HD5 HD4 PUP Mnemonic: POR PUP Address: 86H : Enable Port 0 weak pull-up. HD4−7 : Enable pins P3.4 to P3.7 individually with High Drive outputs. EP5 : Enable P4.5. To set this bit shifts ALE pin to the alternate function P4.5. EP6 : Enable P4.6. To set this bit shifts PSEN pin to the alternate function P4.6 Port 4 The W78LE812 has one additional bit-addressable I/O port P4 in which the port address is D8H. The Port 4 contains seven bits; P4.0 to P4.3 are only available on 44-pin PLCC/QFP package; P4.5 and P4.6 are the alternate function corresponding to pins ALE, PSEN . When program is running in the internal memory without any access to external memory, ALE and PSEN may be individually configured to the alternate functions P4.5 and P4.6 that serve as general purpose I/O pins. To enable I/O port P4.5 and P4.6, the bits EP5 and EP6 in the POR register must be set. During reset, the, ALE and PSEN perform as in the standard 80C32. The alternate functions P4.5 and P4.6 must be enabled by software. Care must be taken with the ALE pins when configured as the alternate functions. The ALE will emit pulses until either the EP5 bit in POR register or AO bit in AUXR register is set to 1. i.e. User's applications should elude the ALE pulses before software configure it with I/O port P4.5. Port 4 Bit: 7 6 5 4 3 2 1 0 - P4.6 P4.5 - P4.3 P4.2 P4.1 P4.0 Mnemonic: P4 Address: D8H Interrupt System The W78LE812 has twelve interrupt sources: INT0 and INT1; Timer 0,1 and 2; Serial Port; INT2 to INT9. Each interrupt vectors to a specific location in program memory for its interrupt service routine. Each of these sources can be individually enabled or disabled by setting or clearing the corresponding bit in Special Function Register IE0 and IE1. The individual interrupt priority level depends on the Interrupt Priority Register IP0 and IP1. Additional external interrupts INT2 to INT9 are level sensitive and may be used to awake the device from power down mode. The Port 1 interrupts can be initialized to either active HIGH or LOW via setting the Interrupt Polarity Register IX. The IRQ register contains the flags of Port 1 interrupts. Each flag in IRQ register will be set when a interrupt request is recognized but must be cleared by software. Note that the interrupt flags have to be cleared before the interrupt service routine is completed, or else another interrupt will be generated. -6- W78LE812 Interrupt Enable Register 0 Bit: 7 6 5 4 3 2 1 0 EA - ET2 ES ET1 EX1 ET0 EX0 Mnemonic: IE EA : ET2: ES : ET1: EX1: ET0: EX0: Address: A8H Global enable. Enable/disable all interrupts. Enable Timer 2 interrupt. Enable Serial Port interrupt. Enable Timer 1 interrupt Enable external interrupt 1 Enable Timer 0 interrupt Enable external interrupt 0 Interrupt Enable Register 1 Bit: 7 6 5 4 3 2 1 0 EX9 EX8 EX7 EX6 EX5 EX4 EX3 EX2 Mnemonic: IE1 EX9: EX8: EX7: EX6: EX5: EX4: EX3: EX2: Enable external interrupt 9 Enable external interrupt 8 Enable external interrupt 7 Enable external interrupt 6 Enable external interrupt 5 Enable external interrupt 4 Enable external interrupt 3 Enable external interrupt 2 Address: E8H Note: 0 = interrupt disabled, 1 = interrupt enabled. Interrupt Priority Register 0 Bit: 7 6 5 4 3 2 1 0 - PS1 PT2 PS PT1 PX1 PT0 PX0 Mnemonic: IP0 IP.7: PS1: PT2: PS : PT1: PX1: PT0: PX0: Address: B8h Unused. This bit defines the Serial port 1 interrupt priority. PS = 1 sets it to higher priority level. This bit defines the Timer 2 interrupt priority. PT2 = 1 sets it to higher priority level. This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level. This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level. This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level. This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level. This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level. -7- Publication Release Date: February 1999 Revision A2 W78LE812 Interrupt Priority Register 1 Bit: 7 6 5 4 3 2 1 0 PX9 PX8 PX7 PX6 PX5 PX4 PX3 PX2 Mnemonic: IP1 PX9: PX8: PX7: PX6: PX5: PX4: PX3: PX2: Address: F8h This bit defines the External interrupt 9 priority. PX9 = 1 sets it to higher priority level. This bit defines the External interrupt 8 priority. PX8 = 1 sets it to higher priority level. This bit defines the External interrupt 7 priority. PX7 = 1 sets it to higher priority level. This bit defines the External interrupt 6 priority. PX6 = 1 sets it to higher priority level. This bit defines the External interrupt 5 priority. PX5 = 1 sets it to higher priority level. This bit defines the External interrupt 4 priority. PX4 = 1 sets it to higher priority level. This bit defines the External interrupt 3 priority. PX3 = 1 sets it to higher priority level. This bit defines the External interrupt 2 priority. PX2 = 1 sets it to higher priority level. Interrupt Polarity Register Bit: 7 6 5 4 3 2 1 0 IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2 Mnemonic: IX Address: E9H IL9: External interrupt 9 polarity level. IL8: External interrupt 8 polarity level. IL7: External interrupt 7 polarity level. IL6: External interrupt 6 polarity level. IL5: External interrupt 5 polarity level. IL4: External interrupt 4 polarity level. IL3: External interrupt 3 polarity level. IL2: External interrupt 2 polarity level. Note: 0 = active LOW, 1 = active HIGH. Interrupt Request Flag Register Bit: 7 6 5 4 3 2 1 0 IQ9 IQ8 IQ7 IQ6 IQ5 IQ4 IQ3 IQ2 Mnemonic: IRQ IQ9: IQ8: IQ7: IQ6: IQ5: IQ4: IQ3: IQ2: Address: C0H External interrupt 9 request flag. External interrupt 8 request flag. External interrupt 7 request flag. External interrupt 6 request flag. External interrupt 5 request flag. External interrupt 4 request flag. External interrupt 3 request flag. External interrupt 2 request flag. -8- W78LE812 Table.1 Priority level for simultaneous requests of the same priority interrupt sources SOURCE FLAG External Interrupt 0 Serial Port External Interrupt 5 Timer 0 Overflow External Interrupt 6 External Interrupt 1 External Interrupt 2 External Interrupt 7 Timer 1 Overflow Timer 2 Overflow External Interrupt 3 External Interrupt 8 External Interrupt 4 External Interrupt 9 PRIORITY LEVEL IE0 RI + TI IQ5 TF0 IQ6 IE1 IQ2 IQ7 TF1 TF2 + EXF2 IQ3 IQ8 IQ4 IQ9 (highest) VECTOR ADDRESS 0003H 0023H 0053H 000BH 005BH 0013H 003BH 0063H 001BH 002BH 0043H 006BH 004BH 0073H (lowest) Watchdog Timer The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the system clock. The divider output is selectable and determines the time-out interval. When the time-out occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a system monitor. This is important in real-time control applications. In case of power glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is left unchecked the entire system may crash. The watchdog time-out selection will result in different time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software should restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog timer are discussed below. Watchdog Timer Control Register Bit: 7 6 5 4 3 2 1 0 ENW CLRW WIDL - - PS2 PS1 PS0 Mnemonic: WDTC Address: 8FH ENW : Enable watch-dog if set. CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled under IDLE mode. Default is cleared. -9- Publication Release Date: February 1999 Revision A2 W78LE812 PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2−0 as follows: PS2 PS1 PS0 PRESCALER SELECT 0 0 0 0 0 1 0 1 0 2 4 8 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 16 32 64 128 256 The time-out period is obtained using the following equation : 1 × 214 × PRESCALER × 1000 × 12 mS OSC Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6 (CLRW). After 1 is written to this bit, the 14-bit timer , prescaler and this bit will be reset on the next instruction cycle. The Watchdog timer is cleared on reset. ENW WIDL IDLE EXTERNAL RESET OSC PRESCALER 1/12 Watchdog Timer Block Diagram 14-BIT TIMER CLEAR CLRW Typical Watch-Dog time-out period when OSC = 20 MHz PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD 0 0 0 0 0 0 1 1 0 1 0 1 19.66 mS 39.32 mS 78.64 mS 157.28 mS 1 1 0 0 0 1 314.57 mS 629.14 mS 1 1 1 1 0 1 1.25 s 2.50 s - 10 - INTERNAL RESET W78LE812 Clock The W78LE812 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78LE812 relatively insensitive to duty cycle variations in the clock. The W78LE812 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground. An external clock source should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. Power Management Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. AUXR - Auxiliary Register Bit: 7 6 5 4 3 2 1 0 - - - - - - - AO Mnemonic: AUXR AO: Address: 8Eh Turn off ALE signal. Reduce EMI Emission Because of the on-chip MTP-ROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is not needed. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space.. Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78LE812 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. - 11 - Publication Release Date: February 1999 Revision A2 W78LE812 ON-CHIP MTP ROM CHARACTERISTICS The W78LE812 has several modes to program the on-chip MTP-ROM. All these operations are configured by the pins RST, ALE, PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2), OECTRL(P3.3), CE (P3.6), OE (P3.7), A0(P1.0) and VPP( EA ). Moreover, the A15−A0(P2.7−P2.0, P1.7−P1.0) and the D7−D0(P0.7−P0.0) serve as the address and data bus respectively for these operations. READ OPERATION This operation is supported for customer to read their code and the Security bits. The data will not be valid if the Lock bit is programmed to low. OUTPUT DISABLE CONDITION When the OE is set to high, no data output appears on the D7..D0. PROGRAM OPERATION This operation is used to program the data to MTP ROM and the security bits. Program operation is done when the VPP is reach to VCP (12.5V) level, CE set to low, and OE set to high. PROGRAM VERIFY OPERATION All the programming data must be checked after program operations. This operation should be performed after each byte is programmed; it will ensure a substantial program margin. ERASE OPERATION An erase operation is the only way to change data from 0 to 1. This operation will erase all the MTP ROM cells and the security bits from 0 to 1. This erase operation is done when the VPP is reach to VEP level, CE set to low, and OE set to high. ERASE VERIFY OPERATION After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase margin. This operation will be done after the erase operation if VPP = VEP(14.5V), CE is high and OE is low. PROGRAM/ERASE INHIBIT OPERATION This operation allows parallel erasing or programming of multiple chips with different data. When P3.6( CE ) = VIH, P3.7( OE ) = VIH, erasing or programming of non-targeted chips is inhibited. So, except for the P3.6 and P3.7 pins, the individual chips may have common inputs. - 12 - W78LE812 COMPANY/DEVICE ID READ OPERATION This operation is supported for MTP ROM programmer to get the company ID or device ID on the W78LE812. OPERATIONS P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 EA P2,P1 P0 (A9 (A13 (A14 (OE ( CE ) ( OE ) (VPP) (A15..A0) (D7..D0) NOTES CTRL) CTRL) CTRL) CTRL) Read 0 0 0 0 0 0 1 Address Data Out Output Disable 0 0 0 0 0 1 1 X Hi-Z Program 0 0 0 0 0 1 VCP Address Data In Program Verify 0 0 0 0 1 0 VCP Address Data Out @3 Erase 1 0 0 0 0 1 VEP A0:0, others: X Data In @4 0FFH Erase Verify 1 0 0 0 1 0 VEP Address Data Out Program/Erase Inhibit X 0 0 0 1 1 VCP/ VEP X X Company ID 1 0 0 0 0 0 1 A0 = 0 Data Out Device ID 1 0 0 0 0 0 1 A0 = 1 Data Out @5 Notes: 1. All these operations happen in RST = VIH, ALE = VIL and PSEN = VIH. 2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = VSS. 3. The program verify operation follows behind the program operation. 4. This erase operation will erase all the on-chip MTP-ROM cells and the Security bits. 5. The erase verify operation follows behind the erase operation. SECURITY BITS During the on-chip MTP-ROM operation mode, the MTP-ROM can be programmed and verified repeatedly. Until the code inside the MTP-ROM is confirmed OK, the code can be protected. The protection of MTP ROM and those operations on it are described below. The W78LE812 has several Special Setting Registers, including the Security Register and Company/Device ID Registers, which can not be accessed in normal mode. These registers can only be accessed from the MTP-ROM operation mode. Those bits of the Security Registers can not be changed once they have been programmed from high to low. They can only be reset through eraseall operation. The contents of the Company ID and Device ID registers have been set in factory. Both registers are addressed by the A0 address line during the same specific condition. The Security Register is addressed in the MTP-ROM operation mode by address #0FFFFh. - 13 - Publication Release Date: February 1999 Revision A2 W78LE812 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 1 0 1 0 1 1 1 0 0 0 0 0 B2 B1 B0 Reserved Company ID (#DAH) 0000h 8KB MTP ROM Device ID (#E0H) Program Memory 1FFFh Security Bits Reserved B0 : Lock bit, logic 0 : active B1 : MOVC inhibit, logic 0 : the MOVC instruction in external memory cannot access the code in internal memory. logic 1 : no restriction. B2 : Encryption logic 0 : the encryption logic enable logic 1 : the encryption logic disable Default 1 for each bit. Security Register 0FFFFh Special Setting Registers Lock bit This bit is used to protect the customer's program code in the W78LE812. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the MTP ROM data and Special Setting Registers can not be accessed again. MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction. Encryption This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will reset this bit. +5V +5V V DD A0 to A7 V IL V IL V IL V IL V IL V IH P1 P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 X'tal1 P0 EA/Vpp V DD PGM DATA V IL RST V IH PSEN V IH P1 V IL V CP ALE P2 A0 to A7 V IL V IL V IL V IH V IL P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 X'tal1 A8 to A15 X'tal2 X'tal2 Vss Vss Programming Configuration P0 EA/Vpp V CP ALE V IL RST V IH PSEN V IH P2 Programming Verification - 14 - PGM DATA A8 to A15 W78LE812 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN. MAX. UNIT VDD−VSS -0.3 +7.0 V Input Voltage VIN VSS -0.3 VDD +0.3 V Operating Temperature TA 0 70 °C Storage Temperature TST -55 +150 °C DC Power Supply Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC CHARACTERISTICS VSS = 0V, TA = 25° C, unless otherwise specified. SYMBOL PARAMETER SPECIFICATION TEST CONDITIONS MIN. MAX. UNIT VDD Operating Voltage 2.4 5.5 V IDD Operating Current - 20 mA VDD = 5.5V, 20 Mhz, no load, RST = 1 - 3 mA VDD = 2.4V, 12 Mhz, no load, RST = 1 - 7 mA VDD = 5.5V, 20 Mhz, no load - 1.5 mA VDD = 2.4V, 12 Mhz, no load - 50 µA VDD = 5.5V, no load - 30 µA VDD = 2.4V, no load IIDLE IPWDN Idle Current Power Down Current Input IIN Input Current P1, P2, P3, P4 -50 +10 µA VDD = 5.5V VIN = 0V or VDD ILK Input Leakage Current P0, EA -10 +10 µA VDD = 5.5V VSS < VIN < VDD IIN2 Input Current RST -10 +0 µA VDD = 5.5V 0 < VIN < VDD ILK1 Input Leakage Current P0, EA -60 +300 µA VDD = 5.5V 0V < VIN < VDD ITL Logic 1-to-0 Transition Current P1, P2, P3, P4 -500 - µA VDD = 5.5V VIN = 2V VIL1 Input Low Voltage 0 0.8 V VDD = 5.5V P1, P2, P3, P4 0 0.5 V VDD = 2.4V Input Low Voltage 0 0.8 V VDD = 5.5V 0 0.3 V VDD = 2.4V VIL2 [*3] RST - 15 - Publication Release Date: February 1999 Revision A2 W78LE812 DC Characteristics, continued SYMBOL PARAMETER SPECIFICATION TEST CONDITIONS MIN. MAX. 0 0.8 0 0.6 V VDD = 2.4V Input High Voltage 3.5 VDD +0.2 V VDD = 5.5V P1, P2, P3, P4, EA 1.6 VDD +0.2 V VDD = 2.4V Input High Voltage 3.5 VDD +0.2 V VDD = 5.5V RST 1.7 VDD +0.2 V VDD = 2.4V 3.5 VDD +0.2 V VDD = 5.5V 1.6 VDD +0.2 V VDD = 2.4V Output Low Voltage - 0.45 V VDD = 4.5V, IOL = +2 mA P1, P2, P3, P4 - 0.25 V VDD = 2.4V, IOL = +1 mA Output Low Voltage - 0.45 V VDD = 4.5V, IOL = +4 mA P0, ALE, PSEN [*4] - 0.25 V VDD = 2.4V, IOL = +2 mA VOL3 Output Low Voltage P3[*6] - 0.22 V VDD = 4.5V, IOL = +2 mA ISK1 Sink current 4 12 mA VDD = 4.5V, VOL = 0.45V P1, P2, P3[5], P4<0:4> 1.8 5.4 mA VDD = 2.4V, VOL = 0.4V Sink current 10 18 mA VDD = 4.5V, VOL = 0.45V P0, ALE, PSEN , P4<5:6> 4.5 9 mA VDD = 2.4V, VOL = 0.4V ISK3 Sink current P3.4 to P3.7 in High-Drive mode 12 24 mA VDD = 4.5V, VOL = 0.45V VOH1 Output High Voltage 2.4 - V VDD = 4.5V, VOH = -100 µA P1, P2, P3, P4 1.4 - V VDD = 2.4V, VOH = -20 µA Output High Voltage 2.4 - V VDD = 4.5V, IOH = -400 µA 1.4 - V VDD = 2.4V, IOH = -200 µA Source current -120 -250 µA VDD = 4.5V, VOH = 2.4V P1, P2, P3, P4<0:4> -20 -40 µA VDD = 2.4V, VOH = 1.4V Source current -10 -14 mA VDD = 4.5V, VOH = 2.4V P0, ALE, PSEN , P4<5:6> -1.9 -3.3 mA VDD = 2.4V, VOH = 1.4V VIL3 Input Low Voltage [*3] XTAL1 VIH1 VIH2 VIH3 Input High Voltage [*4] XTAL1 UNIT VDD = 5.5V Output VOL1 VOL2 ISK2 VOH2 P0, ALE, PSEN ISR1 ISR2 [*4] Notes: *1. RST pin has an internal pull-down. *2. Pins of P1 and P3 can source a transition current when they are being externally driven from 1 to 0. *3. RST is a Schmitt trigger input and XTAL1 is a CMOS input. *4. P0, P2, ALE and PSEN are tested in the external access mode. *5. P3.4 to P3.7 are in normal mode. *6. P3(P3.4−P3.7) is used LED driver port by set SFR. - 16 - W78LE812 AC CHARACTERISTICS The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a ±20 nS variation. The numbers below represent the performance expected from a 0.6micron CMOS process when using 2 and 4 mA output buffers. Clock Input Waveform XTAL1 T CH TCL F OP, PARAMETER Operating Speed Clock Period Clock High Clock Low TCP SYMBOL MIN. TYP. MAX. UNIT NOTES FOP TCP TCH TCL 0 25 10 10 - 24 - MHz nS nS nS 1 2 3 3 Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input. Program Fetch Cycle PARAMETER Address Valid to ALE Low Address Hold from ALE Low ALE Low to PSEN Low PSEN Low to Data Valid Data Hold after PSEN High Data Float after PSEN High ALE Pulse Width PSEN Pulse Width SYMBOL MIN. TYP. MAX. UNIT NOTES TAAS TAAH TAPL 1 TCP -∆ 1 TCP -∆ 1 TCP -∆ - - nS nS nS 4 1, 4 4 TPDA - - 2 TCP nS 2 TPDH 0 - 1 TCP nS 3 TPDZ 0 - 1 TCP nS TALW TPSW 2 TCP -∆ 3 TCP -∆ 2 TCP 3 TCP - nS nS 4 4 Notes: 1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "∆" (due to buffer driving delay and wire loading) is 20 nS. - 17 - Publication Release Date: February 1999 Revision A2 W78LE812 Data Read Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES ALE Low to RD Low TDAR 3 TCP -∆ - 3 TCP +∆ nS 1, 2 RD Low to Data Valid TDDA - - 4 TCP nS 1 Data Hold from RD High TDDH 0 - 2 TCP nS Data Float from RD High TDDZ 0 - 2 TCP nS RD Pulse Width TDRD 6 TCP -∆ 6 TCP - nS 2 Notes: 1. Data memory access time is 8 TCP. 2. "∆" (due to buffer driving delay and wire loading) is 20 nS. Data Write Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT ALE Low to WR Low TDAW 3 TCP -∆ - 3 TCP +∆ nS Data Valid to WR Low TDAD 1 TCP -∆ - - nS Data Hold from WR High TDWD 1 TCP -∆ - - nS WR Pulse Width TDWR 6 TCP -∆ 6 TCP - nS Note: "∆" (due to buffer driving delay and wire loading) is 20 nS. Port Access Cycle PARAMETER Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE SYMBOL TPDS TPDH TPDA MIN. 1 TCP 0 1 TCP TYP. - MAX. - UNIT nS nS nS Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference. - 18 - W78LE812 Program Operation PARAMETER VPP Setup Time Data Setup Time Data Hold Time Address Setup Time Address Hold Time SYMBOL TVPS TDS TDH TAS TAH TPWP MIN. 2.0 2.0 2.0 2.0 0 290 TYP. 300 MAX. 310 UNIT µS µS µS µS µS µS OE Setup Time TOCS TOCH TOES 2.0 2.0 2.0 - - µS µS µS OE High to Output Float TDFP 0 - 130 nS Data Valid from OE TOEV - - 150 nS CE Program Pulse Width for Program Operation OECTRL Setup Time OECTRL Hold Time Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status, and the PSEN pin must pull in VIH status. TIMING WAVEFORMS Program Fetch Cycle S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 XTAL1 TALW ALE T APL PSEN T PSW TAAS PORT 2 T AAH T PDA T PDH, T PDZ PORT 0 Code A0-A7 Data A0-A7 - 19 - Code A0-A7 Data A0-A7 Publication Release Date: February 1999 Revision A2 W78LE812 Data Read Cycle S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 XTAL1 ALE PSEN PORT 2 A8-A15 DATA A0-A7 PORT 0 T DAR T DDA T DDH, T DDZ RD T DRD Data Write Cycle S4 S5 S6 S1 S2 S3 S4 S5 XTAL1 ALE PSEN A8-A15 PORT 2 PORT 0 A0-A7 DATA OUT T DWD TDAD WR T DAW T DWR - 20 - S6 S1 S2 S3 W78LE812 Port Access Cycle S5 S6 S1 XTAL1 ALE TPDS T PDA T PDH DATA OUT PORT INPUT SAMPLE Program Operation Program P2, P1 VIH (A15... A0) VIL P3.6 VIH (CE) VIL P3.3 (OECTRL) VIH P3.7 VIH (OE) VIL P0 (A7... A0) Program Verify Address Stable TPWP TAH TOCS TOCH TOES TDFP TDH VIH D OUT Data In Data Out TDS Vcp TOEV Vpp VIH Address Valid TAS VIL VIL Read Verify TVPS - 21 - Publication Release Date: February 1999 Revision A2 W78LE812 TYPICAL APPLICATION CIRCUITS Expanded External Program Memory and Crystal VDD VDD 31 19 10 u EA XTAL1 R 18 XTAL2 CRYSTAL 8.2 K 9 C1 RST C2 12 13 14 15 INT0 INT1 T0 T1 1 2 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 39 AD0 38 AD1 37 AD2 36 AD3 35 AD4 34 AD5 33 AD6 32 AD7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 21 22 23 24 25 26 27 28 RD WR PSEN ALE TXD RXD 17 16 29 30 11 10 A8 A9 A10 A11 A12 A13 A14 A15 AD0 3 AD1 4 AD2 7 AD3 8 AD413 AD514 AD617 AD718 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND 1 OC 11 G 74373 2 A0 5 A1 6 A2 9 A3 12 A4 15 A5 16 A6 19 A7 A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 27 A15 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 GND 20 CE 22 OE 27512 W78LE812 Figure A CRYSTAL C1 C2 R 16 MHz 30P 30P - 24 MHz 15P 15P - Above table shows the reference values for crystal applications. Note: C1, C2, R components refer to Figure A. - 22 - O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 W78LE812 Typical Application Circuits, continued Expanded External Data Memory and Oscillator VDD VDD 31 10 u EA 19 XTAL1 18 XTAL2 9 RST 12 13 14 15 INT0 OSCILLATOR 8.2 K 1 2 3 4 5 6 7 8 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 39 38 37 36 35 34 33 32 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 21 22 23 24 25 26 27 28 A8 A9 A10 A11 A12 A13 A14 RD 17 16 29 30 11 10 WR PSEN ALE TXD RXD AD0 3 AD1 4 AD2 7 AD3 8 AD4 13 AD5 14 AD6 17 AD7 18 GND 1 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OC 11 G 74373 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 GND 20 22 27 CE OE D0 11 D1 12 D2 13 D3 15 D4 16 D5 17 D6 18 D7 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 WR 20256 W78LE812 Figure B - 23 - Publication Release Date: February 1999 Revision A2 W78LE812 PACKAGE DIMENSIONS 40-pin DIP Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. Symbol D 40 21 E1 0.010 0.150 0.155 0.160 3.81 3.937 4.064 0.016 0.018 0.022 0.406 0.457 0.559 0.048 0.050 0.054 1.219 1.27 1.372 0.008 0.010 0.014 0.203 0.254 0.356 2.055 2.070 52.20 52.58 0.600 0.610 14.986 15.24 15.494 0.540 0.545 0.550 13.72 13.84 13.97 0.090 0.100 0.110 2.286 2.54 2.794 0.120 0.130 0.140 3.048 3.302 3.556 15 0 0.670 16.00 16.51 17.01 0 eA S 20 0.254 0.590 a 1 5.334 0.210 A A1 A2 B B1 c D E E1 e1 L 0.630 0.650 15 0.090 2.286 Notes: E S 1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . parting line. are determined at the mold 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. c A A2 A1 Base Plane Seating Plane L B e1 eA a B1 44-pin PLCC HD D 6 1 44 40 Symbol 7 39 E 17 HE GE 29 18 28 c A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.185 0.020 4.699 0.508 0.145 0.150 0.155 0.026 0.028 0.032 0.016 0.018 0.022 0.008 0.010 0.014 0.203 0.254 0.356 0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 0.050 BSC 3.81 3.937 0.66 0.711 0.813 0.406 0.457 0.559 3.683 1.27 0.590 0.610 0.630 14.99 15.49 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.100 0.110 2.296 2.54 2.794 0.004 Notes: 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. θ e b b1 Seating Plane A1 y GD - 24 - 16.00 0.090 L A2 A BSC 0.10 W78LE812 Package Dimensions, continued 44-pin PQFP HD Symbol 34 A A1 A2 b c D E e HD HE L L1 y θ 33 1 E HE 11 12 e Dimension in mm Dimension in inch D 44 b 22 Min. Nom. Max. Min. Nom. Max. --- --- --- --- 0.002 0.01 0.02 0.05 0.25 0.5 0.075 0.081 0.087 1.90 2.05 2.20 0.01 0.014 0.018 0.25 0.35 0.45 0.004 0.006 0.010 0.101 0.152 0.254 0.390 0.394 0.398 9.9 10.00 10.1 0.390 0.394 0.398 9.9 10.00 10.1 0.025 0.031 0.036 0.635 0.80 0.952 0.510 0.520 0.530 12.95 13.2 13.45 13.45 --- --- 0.510 0.520 0.530 12.95 13.2 0.025 0.031 0.037 0.65 0.8 0.95 0.051 0.063 0.075 1.295 1.6 1.905 0.08 0.003 0 7 0 7 Notes: 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec. c A2 A θ A1 Seating Plane See Detail F L y L1 Headquarters Detail F Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 25 - Publication Release Date: February 1999 Revision A2