W91820N SERIES 13-MEMORY TONE/PULSE DIALER WITH HANDFREE, LOCK AND HOLD FUNCTIONS GENERAL DESCRIPTION The W91820N is a series of tone/pulse switchable telephone dialers with 13 memory, keytone, hold, lock, and handfree dialing control features. These chips are fabricated using Winbond's highperformance CMOS technology and thus offer good performance in low-voltage, low-power operations. FEATURES • • • • • • • • • • • • • • • • • • • • • • Tone/pulse switchable dialer Two by 32 digits redial and save memory Three by 32 digits one-touch direct repertory memory Ten by 32 digits two-touch indirect repertory memory Pulse-to-tone (*/T) keypad for long distance call operation Chain dialing Uses 5 × 5 keyboard Easy operation with redial, flash, pause, and */T keypads Pause, P→T (pulse-to-tone) can be stored as a digit in memory Dialing rate:10 ppS or 20 ppS by mask option Minimum tone output duration: 93 mS (unless W91824N/AN is 87 mS) Minimum intertone pause: 93 mS (unless W91824N/AN is 87mS) Pause time: 3.6 sec. (unless W91824N/AN is 2.0 sec.) Flash break time (73 mS, 100 mS, 300 mS, or 600 mS) selectable by keypad; pause time is 1.0 S Make/break ratio (2:3 or 1:2) selectable by MODE pin Mute key for speech network mute No key will be accepted except the "HOLD" key when in the Hold mode Key tone output for valid keypad entry recognition On-chip power-on reset Uses 3.579545 MHz crystal or ceramic resonator 20, or 22-pin dual-in-line plastic package The different dialers in the W91820N series are shown in the following table: TYPE NO. PULSE (ppS) LOCK KEY TONE HANDFREE DIALING PACKAGE (PINS) W91820N/824N 10 - √ - 20 W91820AN/824AN 10 - √ √ 22 W91820LN 10 √ - - 20 W91820ALN 10 √ - √ 22 W91822N 20 - √ - 20 W91822AN 20 - √ √ 22 Note: W91824N/824AN for French only. -1- Publication Release Date: May 1999 Revision A2 W91820N SERIES PIN CONFIGURATIONS C1 1 22 R4 C1 1 20 R4 C2 2 21 R3 C2 2 19 R3 C3 3 20 R2 C3 3 18 R2 C4 4 19 R1 C4 4 17 R1 KT 5 18 N.C. KT 5 16 N.C. H/P MUTE 6 17 VDD VSS 7 16 MODE 15 DTMF 6 15 VDD VSS 7 14 MODE XT 8 XT 8 13 DTMF XT 9 14 DP XT 9 12 DP T/P MUTE 10 13 HKS T/P MUTE 10 11 HKS HFI 11 12 HFO H/P MUTE W91820N/822N /824N W91820AN/822AN /824AN C1 1 22 R4 R4 C2 2 21 R3 19 R3 C3 3 20 R2 18 R2 C4 4 19 R1 17 R1 LOCK 5 18 N.C. C1 1 20 C2 2 C3 3 C4 4 LOCK 5 16 N.C. H/P MUTE 6 17 VDD H/P MUTE 6 15 VDD VSS 7 16 MODE VSS 7 14 MODE XT 8 15 DTMF XT 8 13 DTMF XT 9 14 DP XT 9 12 DP T/P MUTE 10 13 HKS T/P MUTE 10 11 HKS HFI 11 12 HFO W91820LN W91820ALN -2- W91820N SERIES PIN DESCRIPTION SYMBOL 20-PIN 22-PIN I/O ColumnRow Inputs 1−4 & 17−20 1−4 & 19−22 I FUNCTION The keyboard input is compatible with a standard 5 × 5 keyboard, an inexpensive single contact (Form A) keyboard, and electronic input. In normal operation, any single button can be pushed to produce dual tone, pulses, or functions. Activation of two or more buttons will result in no response except for a single tone. XT 8 8 I A built-in inverter together with an inexpensive 3.579545 MHz crystal supplies the oscillator. The oscillator stops when there is no keypad input. The crystal frequency deviation is 0.02%. XT 9 9 O Crystal oscillator output pin. T/P MUTE 10 10 O The T/P MUTE is a conventional CMOS N-channel open drain output. The output transistor turns on with a low level during a dialing sequence (both pulse and tone mode). Otherwise, it is off. N.C. 16 18 - No connect MODE 14 16 I Connecting the mode pin to VSS places the dialer in tone mode. Connecting the mode pin to VDD places the dialer in pulse mode with an M/B ratio of 40:60. Leaving the mode pin floating places the dialer in pulse mode with an M/B ratio of 33.3:66.7. HKS 11 13 I The HKS (hook switch) input is used to sense whether the handset is on-hook or off-hook. In on-hook state, HKS = 1: chip is in sleeping mode, no operation. In off-hook state, HKS = 0: chip is enabled for normal operation. HKS pin is pulled to VDD by internal resistor. KT (W91820N/8 20AN/822N/ 824N/822AN /824AN only) 5 5 O The key tone output is a conventional CMOS inverter. The key tone is generated when any valid key is pressed; the KT pin generates a 1.2 KHz square wave at 35 mS. When no key is pressed, the KT pin remains in low state. -3- Publication Release Date: May 1999 Revision A2 W91820N SERIES Pin Description, continued SYMBOL LOCK 20-PIN 22-PIN I/O FUNCTION 5 5 I The function of this terminal is to prevent "0" dialing and "9" dialing under PABX system long distance call control. When the first key input after reset is 0 or 9, all key inputs, including the 0 or 9 key, become invalid and the chip generates no output. The telephone is reinitialized by a reset. (W91820LN/ 820ALN only) The function of the LOCK pin is shown below: FUNCTION LOCK PIN VDD "0", "9" dialing inhibited Floating Normal dialing Mode VSS "0" dialing inhibited H/P MUTE 6 6 I The H/P MUTE is a conventional inverter output. During pulse dialing, flash break or hold period, this output is active high; otherwise, it remains in low state. DP 12 14 O N-channel open drain dialing pulse output. Flash key will cause DP to be active in either tone mode or pulse mode. In lock mode, the DP remains low for 300 mS durint offhook delay time. The timing diagram for pulse mode is shown in Figure 1(a, b). DTMF 13 15 O During pulse dialing, this pin remains in a low state regardless of the keypad input. In tone mode, it will output a dual or single tone. A detailed timing diagram for tone mode is shown in Figure 2(a, b). OUTPUT FREQUENCY VDD, VSS 15, 7 17, 7 I Specified Actual R1 697 699 Error % +0.28 R2 770 766 -0.52 R3 852 848 -0.47 R4 941 948 +0.74 C1 1209 1216 +0.57 C2 1336 1332 -0.30 C3 1477 1472 -0.34 Power input pins for the dialer chip. VDD is the power and VSS is the ground. -4- W91820N SERIES Pin Description, continued SYMBOL HFI , HFO 20-PIN 22-PIN I/O FUNCTION - 11, 12 I, O Handfree control pins. A low pulse on the HFI input pin toggles the handfree control state. The status of the handfree control state is listed in the following table: NEXT STATE CURRENT STATE HFO INPUT HFO DIALING - Low HFI High Yes On Hook High HFI Low No Off Hook High HFI Low Yes On Hook - Off Hook Low Yes Off Hook Low On Hook Low No Off Hook High On Hook High Yes HOOK SW. The HFI pin is pulled to VDD by an internal resistor. A detailed timing diagram is shown in Figure 3. BLOCK DIAGRAM XT XT HKS SYSTEM CLOCK GENERATOR HFI ROW (R1 ~ R4, Vx/R5) CONTROL LOGIC READ/WRITE COUNTER LOCK MODE KEYBOARD INTERFACE COLUMN (C1 ~ C4, Vss) LOCATION LATCH DTMF D/A CONVERTER ROW & COLUMN PROGRAMMABLE COUNTER -5- PULSE CONTROL LOGIC RAM T/P MUTE KT DP HFO H/P MUTE DATA LATCH & DECODER Publication Release Date: May 1999 Revision A2 W91820N SERIES FUNCTIONAL DESCRIPTION Keyboard Operation C1 C2 C3 C4 VSS 1 4 7 */T 2 5 8 0 3 6 9 # S F4 A R/P EM1 EM2 EM3 SAVE F1 F2 F3 H R1 R2 R3 R4 Vx/R5 • S: Store function key • A: Indirect repertory memory dialing function key • H: Hold function key • R/P: Redial and pause function key • */T: * in tone mode and P→T key in pulse mode • SAVE: Save function key for one-touch 32-digit memory • EM1, ..., EM3: Emergency one-touch memory key • F1, ..., F4: Flash function keys: F1 = 600 mS, F2 = 300 mS, F3 = 73 mS, F4 = 100 mS; all flash pause time is 1.0 mS Note: D1, ..., Dn, D1`, ..., Dn`, */T, #, Mn: EM1, ..., EM3, Ln: 0−9 Normal Dialing OFF HOOK (or ON HOOK & ), HFI D1 , , …, D2 Dn 1. D1, D2, …, Dn will be dialed out. 2. Dialing length is unlimited, but redial is inhibited if length oversteps 32 digits in normal dialing. Redialing Dialing OFF HOOK Come The (or ON HOOK ON HOOK , & OFF HOOK , HFI (or D1 ON HOOK , & D2 , …, HFI Dn ), , BUSY R/P R/P key can execute redial function only as first key-in after off-hook. Otherwise, it will invoke the pause function. • The below cases are selected by mask option for W91824N/AN (French version) only. In tone mode: D1, D2, D3,*(or #), D4, D5, D6 The chip will only output D1, D2, D3 and ignore *(or #), D4, D5, D6. In pulse mode: D1, D2, D3, */T, D4, D5, D6 -6- W91820N SERIES The chip will only output D1,D2,D3 and do not transfer to tone mode. In pulse mode, the # sign does not effect. Number Store 1. OFF HOOK EMn (or (or A ON HOOK , Ln a. The dialing out of or D1 & SAVE to Dn ), HFI D1 , D2 , ..., Dn , S , S , ) must first be finished before the S key is pressed. b. D1, D2, …, Dn will be stored in memory location Mn or saved and then dialed out. 2. OFF HOOK EMn (or (or A ON HOOK , Ln or & ), HFI SAVE S , D1 , D2 , ..., Dn , S , ) a. D1, D2, …, Dn will be stored in memory location, Mn (or saved), but will not be dialed out. b. R/P and */T keys can be stored as a digit in memory, but the first digit. In store mode, R/P R/P key cannot be the is the pause function key. c. The store mode is released after the store function is executed or when the state of the hook switch changes or the flash function is executed. Save OFF HOOK (or ON HOOK & ), HFI D1 , D2 , ..., Dn , Save a. D1, D2, ..., Dn will be dialed out. b. If the dialing of D1 to Dn is finished, pressing SAVE will duplicate D1 to Dn to the save memory. OFF HOOK come on (or ON HOOK OFF HOOK (or & ), HFI ON HOOK c. D1 to Dn will be dialed out after the & HFI ), SAVE SAVE key is pressed. Repertory Dialing Procedure One-touch direct repertory dialing: OFF HOOK (or ON HOOK & HFI ), Mn -7- (or SAVE ) Publication Release Date: May 1999 Revision A2 W91820N SERIES Two-touch direct repertory dialing: OFF HOOK (or ON HOOK & HFI ), A ON HOOK & HFI ), D1 , Ln Access Pause OFF HOOK (or , D2 , R/P , D3 , ..., Dn 1. The pause function can be stored in memory. 2. The pause function is executed with normal dialing, redialing or memory dialing. 3. The pause function timing diagram is shown in Figure 6. Pulse-to-tone (*/T) OFF HOOK (or , Dn' D2' , ..., ON HOOK & HFI ), D1 , D2 , ..., Dn , */T , D1' , 1. If the mode switch is set in pulse mode, then it will perform case a: D1, D2, ---, Dn, Pause (3.6 sec), D1', D2', ---, Dn' (Pulse) (Tone) case b: (only for French version) D1, D2, ---, Dn, * , D1', D2', ---, Dn' (Pulse) (Tone) 2. If the mode switch is set in tone mode, then the output signal will be: D1, D2, ---, Dn, * , D1', D2', ---, Dn' (Tone) 3. It can be reset to pulse mode only if ON HOOK is active. This is because it remains in tone mode when the digits have been dialed out. 4. The function timing diagram is shown in Figure 7. Flash OFF HOOK (or ON HOOK 1. Fn = F1−F4. If Fn & HFI ), Fn is pressed, the dialer will execute a flash break time of 600 mS (F1), 300 mS (F2), 73 mS (F3) or 100 mS (F4) and a pause time of 1.0 second, after which the next digit is dialed out. 2. The flash key has the first priority of the keyboard function only one flash key will be released to the user. 3. When the flash key is key in, the system will return to the initial state after the flash pause time is finished. 4. The flash function timing diagram is shown in Figure 8. -8- W91820N SERIES Cascaded Dialing OFF HOOK 1. (or ON HOOK Normal Dialing + Repertory Dialing Redialing + (1st sequence) + Normal Dialing + Repertory Dialing (2nd sequence) + (1st sequence) 3. ) HFI Repertory Dialing (1st sequence) 2. & Normal Dialing (2nd sequence) Normal Dialing + Repertory Dialing (2nd sequence) Redialing is valid only for the first key-in. The second sequence should not be operated until the first sequence is dialed out completely. ABSOLUTE MAXIMUM RATING PARAMETER SYMBOL RATING UNIT VDD−VSS -0.3 to +7.0 V VIL VSS -0.3 V VIH VDD +0.3 V VOL VSS -0.3 V VOH VDD +0.3 V PD 120 mW Operation Temperature TOPR -20 to +70 °C Storage Temperature TSTG -55 to +150 °C DC Supply Voltage Input/Output Voltage Power Dissipation Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. -9- Publication Release Date: May 1999 Revision A2 W91820N SERIES DC CHARACTERISTICS (VDD−VSS = 2.5V, Fosc. = 3.58 MHz, TA = 25° C, all outputs unloaded) PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT 2.0 - 5.5 V Operating Voltage VDD - Operating Current IOP Tone - 0.4 0.6 mA Pulse - 0.2 0.4 mA Standby Current ISB HKS = 0, No load & No key entry - - 15 µA Memory Retention Current IMR HKS = 1, VDD = 1.0V - - 1 µA Tone Output Voltage VTO Row group, RL = 5 KΩ 130 150 170 mVrms Col/Row, VDD = 2.0−5.5V 1 2 3 dB Pre-emphasis DTMF Distortion THD RL = 5 KΩ, VDD = 2.0−5.5V - -30 -23 dB DTMF Output DC Level VTDC RL = 5 KΩ, VDD = 2.0−5.5V 1.0 - 3.0 V DTMF Output Sink Current ITL VTO = 0.5V 0.2 - - mA DP Output Sink Current IPL VPO = 0.5V 0.5 - - mA T/P MUTE Output Sink Current IML VMO = 0.5V 0.5 - - mA KT Drive/Sink Current IKTH VKTH = 2.0V 0.5 - - mA IKTL VKTL = 0.5V 0.5 - - mA IHFH VHFH = 2.0V 0.5 - - mA IHFL VHFL = 0.5V 0.5 - - mA H/P MUTE IHPH VHPH = 2.0V 0.5 - - mA Drive/Sink Current IHPL VHPL = 0.5V 0.5 - - mA Keypad Input Drive Current IKD VI = 0V 4 - - µA 300 500 - KΩ 200 400 - µA - - 5.0 KΩ HFO Drive/Sink Current HKS Pull High Resister Keypad Input Sink Current RHKS IKS VI = 2.5V Keypad Resistance - 10 - W91820N SERIES AC CHARACTERISTICS PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT Key-in Debounce Key Release Debounce On-hook Debounce TKID TKRD TOHD - - 20 20 20 - mS mS mS - 150 40 33.3 20 16.7 - mS mS mS mS mS - 800 - mS - 500 - mS - 800 500 40:60 33.3:66.7 93 - mS mS % % mS - 93 600 300 73 100 1.0 3.6 - mS mS 2.0 1.2 35 600 - S KHz mS mS Pre-digit Pause1 Pre-digit Pause2 Inter Digit Pause (Auto Dialing) TPDP1 10 ppS TPDP2 20 ppS TIDP Lock Mode Unlock Mode Mode Pin = VDD Mode Pin = Floating Mode Pin = VDD Mode Pin = Floating 10 ppS (W91820N/W91820AN/820LN /820ALN/824N/824AN only) 20 ppS (W91822N/822AN only) Interdigit Pause (Auto dialing) Make/Break Ratio TIDP Tone Output Duration TTD Intertone Pause Flash Break Time TITP TFB Flash Pause Time Pause Time TFP TP M:B 10 ppS 20 ppS Mode Pin = VDD Mode Pin = Floating F1 F2 F3 F4 (W91824N/AN only) Key Tone Frequency Key Tone Duration One-key Redialing Pause Time One-key Redialing Break Time First Key-in Delay S S FKT TKTD TRP - - TRB - - 2.2 - S - 300 - mS TFKD Lock only Notes: 1. Crystal parameters suggested for proper operation are Rs < 100 Ω, Lm = 96 mH, Cm = 0.02 pF, Cn = 5 pF, Cl = 18 pF, Fosc. = 3.579545 MHz ±0.02%. 2. Crystal oscillator accuracy directly affects these times. - 11 - Publication Release Date: May 1999 Revision A2 W91820N SERIES TIMING WAVEFORMS HKS 4 KEY IN 2 TKID DP 2 TKID M TIDP B TPDP M B TIDP TIDP TPDP T/P MUTE H/P MUTE KT DTMF LOW OSC. OSC. OSC. Figure 1(a). Pulse Mode Tming Diagram (Normal dialing without lock function) HKS 300 mS 4 KEY IN 2 2 TFKD DP TKID MB M B T IDP TIDP TIDP TPDP T/P MUTE (long mute) H/P MUTE DTMF OSC. LOW OSC. Figure 1(b). Pulse Mode Timing Diagram (Normal dialing with lock function) - 12 - OSC. W91820N SERIES Timing Waveforms, continued HKS R/P KEY IN M DP B M B TIDP TIDP TIDP TPDP TPDP T/P MUTE (long mute) H/P MUTE KT LOW DTMF OSC. OSC. ON HOOK Figure 1(c). Pulse Mode Timing Diagram (Auto dialing without lock) HKS 300 mS R/P KEY IN M DP T FKD B TIDP TIDP TPDP T/P MUTE (long mute) H/P MUTE DTMF OSC. LOW OSC. Figure 1(d).Pulse Mode Timing Diagram (Auto dialing with lock function) - 13 - Publication Release Date: May 1999 Revision A2 W91820N SERIES Timing Waveforms, continued HKS KEY IN 3 2 6 TKID DTMF TKRD TTD TITP TKID TKRD 5 TKRD TITP TITP T/P MUTE LOW H/P MUTE KT DTMF HIGH OSC. OSC. OSC. Figure 2(a). Tone Mode Timing Diagram HKS KEY IN 300 mS 3 2 6 TKRD DTMF TTD TITP TKRD TKID 5 TKRD TITP TITP T/P MUTE TFKD H/P MUTE LOW DP HIGH OSC. OSC. OSC. Figure 2(b). Tone Mode Timing Diagram (Normal dialing with lock function) - 14 - W91820N SERIES Timing Waveforms, continued HKS T T < TOHD R/P KEY IN TKID DTMF TTD TITP TITP T/P MUTE LOW H/P MUTE KT DP HIGH OSC. OSC. ON HOOK Figure 2(c). Tone Mode Timing Diagram (Auto dialing without lock function) HKS 300 mS T T < TOHD R/P KEY IN DTMF TTD TITP TITP T/P MUTE T FKD H/P MUTE TKID LOW DP HIGH OSC. OSC. Figure 2(d). Tone Mode Timing Diagram (Auto dialing with lock function) - 15 - Publication Release Date: May 1999 Revision A2 W91820N SERIES Timing Waveforms, continued HKS T T > TOHD R/P KEY IN TKID DTMF TTD TITP T/P MUTE (return to initial state) LOW H/P MUTE KT DP HIGH OSC. OSC. ON HOOK Figure 2(c). Tone Mode Timing Diagram with On-hook Debounce (Auto dialing) HKS ON HOOK OFF HOOK HFI H KEY HFO T/P MUTE HIGH H/P MUTE LOW CHIP ENABLE Note: The H KEY can not be enabled during chip dissable. Figure 3(a) - 16 - W91820N SERIES Timing Waveforms, continued OFF HOOK HKS HFI H KEY HFO T/P MUTE HIGH H/P MUTE CHIP ENABLE Figure 3(b) Note: The H KEY and HFI inputs will toggle the HFO signal. The first time HFI or H KEY are activated, the HFO signal will go high and the previous active input will be neglected. ON HOOK HKS HFI H KEY HFO T/P MUTE HIGH H/P MUTE CHIP ENABLE Figure 3(c) Note: The HKS signal change of state from high to low will initialize both the HFO and H/P MUTE signals. - 17 - Publication Release Date: May 1999 Revision A2 W91820N SERIES Timing Waveforms, continued HKS T T<TOHD 4 KEY IN TKID M B DP TIDP TPDP T/P MUTE TFKD TOFD H/P MUTE TOHD LOW DTMF OSC. OSC. OSC. CHIP ENABLE ON HOOK Figure 4. Lock Function Timing Diagram LOW HKS KEY IN OKR M TRB DP B TRP TKID TIDP TPDP T/P MUTE H/P MUTE KT LOW DTMF OSC . OSC. Figure 5. Pulse Mode One-key Redialing Timing Diagram - 18 - TIDP TPDP W91820N SERIES Timing Waveforms, continued HKS 4 KEY IN 2 TKID DP R/P 2 M B TIDP M B TIDP TIDP TPDP TPDP T/P MUTE TP H/P MUTE KT DTMF LOW OSC. OSC . Figure 6. Pause Function Timing Diagram HKS KEY IN 4 2 TKID DP B TPDP */T 8 M TIDP MB TIDP T/P MUTE TP DTMF TITP H/P MUTE KT OSC. OSC. Figure 7(a). Pulse to Tone Function Timing Diagram - 19 - Publication Release Date: May 1999 Revision A2 W91820N SERIES Timing Waveforms, continued HKS KEY IN 4 2 TKID DP */T 8 M B T IDP TPDP M B T IDP T/P MUTE H/P MUTE DTMF * 8 TITP T ITP KT OSCILLATION OSC. Figure 7(b). Pulse to tone function timing diagram (only for French version) HKS KEY IN R/P M DP B TPDP TIDP M B TIDP T/P MUTE H/P MUTE KT LOW DTMF OSC . OSC. ON HOOK Figure 7(c). Pulse mode auto-redialing timing diagram continue Figure 6(b). (only for French version) - 20 - W91820N SERIES Timing Waveforms, continued HKS R/P KEY IN TKID DTMF TTD TITP 2 4 T/P MUTE LOW H/ P MUTE KT DP HIGH OSC. OSC . ON HOOK Figure 7(d). Tone mode auto-redialing timing diagram continue Figure 6(b). (only for French version) LOW HKS Fn KEY IN TKID DP TFB T/P MUTE H/P MUTE KT LOW DTMF TFP OSC. OSC. Figure 8. Flash Operation Timing Diagram - 21 - Publication Release Date: May 1999 Revision A2 W91820N SERIES Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 22 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798