TI CD74FCT844AEN

CD74FCT843A,
CD74FCT844A
Data sheet acquired from Harris Semiconductor
SCHS267
BiCMOS FCT Interface Logic,
9-Bit Transparent Latches, Three-State
D
ENDE
M
M
O
S
EC
IGN
NOT R NEW DES ology
n
Tech
FOR
January 1997
Features
MOS
Use C
Circuit Design
Speed of Bipolar FAST™/AS/S
48mA Output Sink Current
Output Voltage Swing Limited to 3.7V at VCC = 5V
Controlled Output Edge Rates
Input/Output Isolation to VCC
BiCMOS Technology with Low Quiescent Power
• Buffered Inputs
• Typical Propagation Delay: 6.8ns at VCC = 5V,
TA = 25oC, CL = 50pF (FCT843A)
• CD74FCT843A
- Noninverting
•
•
•
•
•
•
• CD74FCT844A
- Inverting
Ordering Information
• SCR Latchup Resistant BiCMOS Process and
PART NUMBER
TEMP.
RANGE (oC)
PKG.
NO.
PACKAGE
CD74FCT844AEN
0 to 70
24 Ld PDIP
E24.3
CD74FCT843AM
0 to 70
24 Ld SOIC
M24.3
NOTE: When ordering the suffix M package, use the entire part
number. Add the suffix 96 to obtain the variant in the tape and reel.
Pinouts
CD74FCT843A
(SOIC)
TOP VIEW
CD74FCT844A
(PDIP)
TOP VIEW
OE 1
24 VCC
OE 1
24 VCC
D0 2
23 Y0
D0 2
23 Y0
D1 3
22 Y1
D1 3
22 Y1
D2 4
21 Y2
D2 4
21 Y2
D3 5
20 Y3
D3 5
20 Y3
D4 6
19 Y4
D4 6
19 Y4
D5 7
18 Y5
D5 7
18 Y5
D6 8
17 Y6
D6 8
17 Y6
D7 9
16 Y7
D7 9
16 Y7
D8 10
15 Y8
D8 10
15 Y8
CLR 11
14 PRE
CLR 11
14 PRE
GND 12
13 LE
GND 12
13 LE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1997
8-1
File Number
2396.2
CD74FCT843A, CD74FCT844A
Functional Diagram
843A 844A
D0
D1
D2
D3
D4
D5
D6
D7
D8
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
13 14
LE
PRE
1
11
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
CLR
OE
GND = PIN 12
VCC = PIN 24
TRUTH TABLE (Note 1)
INPUTS
OUTPUTS
CLR
PRE
OE
LE
843A
Dn
844A
Dn
Yn
H
H
H
X
X
X
Z
High Z
H
H
H
L
X
X
Z
Latched (High Z)
H
H
L
H
L
H
L
Transparent
H
H
L
H
H
L
H
Transparent
H
H
L
L
X
X
NC
H
L
L
X
X
X
H
Preset
L
H
L
X
X
X
L
Clear
FUNCTION
Latched
L
L
L
X
X
X
H
Preset
L
H
H
L
X
X
Z
Latched (High Z)
H
L
H
L
X
X
Z
Latched (High Z)
NOTE:
1. H= HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
NC = No Change
Z = High Impedance
8-2
CD74FCT843A, CD74FCT844A
IEC Logic Symbol
CD74FCT843A
1
13
11
14
EN
C1
R
S
2
1D
CD74FCT844A
1
13
11
14
EN
C1
R
S
1D
23
2
3
22
3
22
4
21
4
21
5
20
5
20
6
6
7
19
18
7
19
18
8
17
8
17
9
16
15
9
16
15
10
10
8-3
23
CD74FCT843A, CD74FCT844A
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Diode Current, IIK (For VI < -0.5V) . . . . . . . . . . . . . . . . . . -20mA
DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA
DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . . 70mA
DC Output Source Current per Output Pin, IO . . . . . . . . . . . . -30mA
DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237mA
DC Ground Current (IGND). . . . . . . . . . . . . . . . . . . . . . . . . . . 453mA
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC-Lead Tips Only)
Operating Conditions
Operating Temperature Range, TA . . . . . . . . . . . . . . . . .0oC to 70oC
Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
DC Input Voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
DC Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ VCC
Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Commercial Temperature Range 0oC to 70oC, VCC Max = 5.25V, VCC Min = 4.75V
AMBIENT TEMPERATURE (TA)
25oC
TEST CONDITIONS
PARAMETER
SYMBOL
VI (V)
IO (mA)
0oC TO 70oC
VCC (V)
MIN
MAX
MIN
MAX
UNITS
High Level Input Voltage
VIH
4.75 to
5.25
2
-
2
-
V
Low Level Input Voltage
VIL
4.75 to
5.25
-
0.8
-
0.8
V
High Level Output Voltage
VOH
VIH or VIL
-15
Min
2.4
-
2.4
-
V
Low Level Output Voltage
VOL
VIH or VIL
48
Min
-
0.55
-
0.55
V
High Level Input Current
IIH
VCC
Max
-
0.1
-
1
µA
Low Level Input Current
IIL
GND
Max
-
-0.1
-
-1
µA
IOZH
VCC
Max
-
0.5
-
10
µA
IOZL
GND
Max
-
-0.5
-
-10
µA
Input Clamp Voltage
VIK
VCC or
GND
Min
-
-1.2
-
-1.2
V
Short Circuit Output Current
(Note 3)
IOS
VO = 0
VCC or
GND
Max
-75
-
-75
-
mA
Quiescent Supply Current,
MSI
ICC
VCC or
GND
Max
-
8
-
80
µA
∆ICC
3.4V
(Note 4)
Max
-
1.6
-
1.6
mA
Three-State Leakage Current
Additional Quiescent Supply
Current per Input Pin
TTL Inputs High, 1 Unit Load
-18
0
NOTES:
3. Not more than one output should be shorted at one time. Test duration should not exceed 100ms.
4. Inputs that are not measured are at VCC or GND.
5. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆ICC limit specified in Static Characteristics Chart, e.g., 1.6mA Max. @ 70oC.
8-4
CD74FCT843A, CD74FCT844A
Switching Specifications Over Operating Range FCT Series tr, tf = 2.5ns, CL = 50pF, RL (Figure 1)
25oC
0oC TO 70oC
SYMBOL
VCC (V)
TYP
MIN
MAX
UNITS
CD74FCT843A
tPLH, tPHL
5
(Note 6)
6.8
1.5
9
ns
CD74FCT844A
tPLH, tPHL
5
7.5
1.5
10
ns
tPLH, tPHL
5
9
1.5
12
ns
PRE to Outputs
tPLH
5
9
1.5
12
ns
CLR to Outputs
tPHL
5
9.8
1.5
13
ns
Output Enable Times
tPZL, tPZH
-
10.5
1.5
14
ns
Output Disable Times
tPLZ, tPHZ
-
6
1.5
8
ns
CPD
(Note 7)
-
-
-
-
pF
Minimum (Valley) VOHV During Switching of
Other Outputs (Output Under Test Not Switching)
VOHV
5
0.5
-
-
V
Maximum (Peak) VOLP During Switching of
Other Outputs (Output Under Test Not Switching)
VOLP
5
1
-
-
V
Input Capacitance
CI
-
-
-
10
pF
Three-State Output Capacitance
CO
-
-
-
15
pF
PARAMETER
Propagation Delays
Data to Outputs
LE to Outputs
Power Dissipation Capacitance
NOTES:
6. 5V: Minimum is at 5.25V for 0oC to 70oC, Maximum is at 4.75V for 0oC to 70oC, Typical is at 5V.
7. CPD, measured per flip-flop, is used to determine the dynamic power consumption.
PD (per package) = VCC ICC + Σ(VCC2 fI CPD + VO2 fOCL + VCC ∆ICC D) where:
VCC = supply voltage
∆ICC = flow through current x unit load
CL = output load capacitance
D = duty cycle of input high
fO = output frequency
fI = input frequency
Prerequisite for Switching
25oC
PARAMETER
0oC TO 70oC
SYMBOL
VCC (V)
TYP
MIN
MAX
UNITS
Setup Time, Data to LE
tSU
5
(Note 8)
-
2.5
-
ns
Hold Time, Data to LE
tH
5
-
2.5
-
ns
LE Pulse Width
tW
5
-
4
-
ns
PRE, CLR Pulse Width
tW
5
-
8
-
ns
tREC
5
-
14
-
ns
PRE, CLR Recovery Time
NOTE:
8. Minimum is at 4.75V for 0oC to 70oC, Typical is at 5V.
Test Circuits and Waveforms
tr, tf = 2.5ns
(NOTE 9)
VI
SWITCH POSITION
7V
3V
0
PULSE ZO
GEN
RT = ZO
VCC
500Ω
RL
V0
DUT
RT
CL
50pF
500Ω
RL
NOTE:
9. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; Z
≤ 50Ω;
TEST
SWITCH
tPLZ, tPZL, Open Drain
Closed
tPHZ, tPZH, tPLH, tPHL
Open
DEFINITIONS:
CL = Load capacitance, includes jig and probe
capacitance.
8-5
RT = Termination resistance, should be equal to ZOUT of
the Pulse Generator.
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