XICOR X5165S8-2.7

Preliminary Information
Replaces X25163/X25165
X5163/X5165
CPU Supervisor with 16Kbit SPI EEPROM
FEATURES
DESCRIPTION
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence
—Reset signal valid to VCC = 1V
• Determine watchdog or low voltage reset with a
volatile flag bit
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 16Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock™ protection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14-lead TSSOP, 8-lead SOIC
These devices combine four popular functions, Poweron Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscillator to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out
interval, the device activates the RESET/RESET signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip point.
RESET/RESET is asserted until VCC returns to proper
operating level and stabilizes. Five industry standard
VTRIP thresholds are available, however, Xicor’s unique
circuits allow the threshold to be reprogrammed to meet
custom requirements or to fine-tune the threshold for
applications requiring higher precision.
BLOCK DIAGRAM
Watchdog Transition
Detector
WP
SO
SCK
CS/WDI
Protect Logic
RESET/RESET
Data
Register
Status
Register
Command
Decode &
Control
Logic
4K Bits
4K Bits
VCC Threshold
Reset Logic
8K Bits
VCC
+
VTRIP
REV 1.1 3/5/01
EEPROM Array
SI
Watchdog
Timer Reset
-
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Reset &
Watchdog
Timebase
X5163 = RESET
X5165 = RESET
Power on and
Low Voltage
Reset
Generation
Characteristics subject to change without notice.
1 of 21
X5163/X5165 – Preliminary Information
PIN DESCRIPTION
Pin
(SOIC/PDIP)
Pin
TSSOP
Name
Function
1
1
CS/WDI
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power up, a HIGH to
LOW transition on CS is required
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
2
2
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
3
6
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the Watchdog Timer control and the memory write protect bits.
4
7
VSS
Ground
5
8
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
6
9
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
7
13
RESET/
RESET
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever VCC falls below the minimum VCC sense level. It will remain
active until VCC rises above the minimum VCC sense level for 200ms. RESET/
RESET goes active if the Watchdog Timer is enabled and CS remains either
HIGH or LOW longer than the selectable Watchdog time out period. A falling
edge of CS will reset the Watchdog Timer. RESET/RESET goes active on power
up at 1V and remains active for 200ms after the power supply stabilizes.
8
14
VCC
Supply Voltage
3-5,1012
NC
No internal connections
PIN CONFIGURATION
14-Lead TSSOP
8-Lead SOIC/PDIP
CS/WDI
SO
REV 1.1 3/5/01
1
8
2
WP
3
VSS
4
X5163/65
CS/WDI
1
14
VCC
SO
2
13
RESET/RESET
NC
3
NC
4
NC
WP
VSS
VCC
7
RESET/RESET
6
SCK
5
SI
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12
NC
11
NC
5
10
NC
6
9
SCK
7
8
SI
X5163/65
Characteristics subject to change without notice.
2 of 21
X5163/X5165 – Preliminary Information
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X5163/X5165 activates a
Power On Reset Circuit. This circuit goes active at 1V
and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
of the oscillator. When VCC exceeds the device VTRIP
value for 200ms (nominal) the circuit releases RESET/
RESET, allowing the processor to begin executing code.
To set the new VTRIP voltage, apply the desired VTRIP
threshold to the VCC pin and tie the CS/WDI pin and
the WP pin HIGH. RESET and SO pins are left unconnected. Then apply the programming voltage VP to
both SCK and SI and pulse CS/WDI LOW then HIGH.
Remove VP and the sequence is complete.
Figure 1. Set VTRIP Voltage
CS
VP
Low Voltage Monitoring
During operation, the X5163/X5165 monitors the VCC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum VTRIP. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until VCC returns and exceeds
VTRIP for 200ms.
Watchdog Timer
The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to
prevent a RESET/RESET signal. The CS/WDI pin
must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two
nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor
can change these watchdog bits, or they may be
“locked” by tying the WP pin LOW and setting the
WPEN bit HIGH.
SCK
VP
SI
Resetting the VTRIP Voltage
This procedure sets the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the
VTRIP is reset, the new VTRIP is something less than
1.7V. This procedure must be used to set the voltage to
a lower value.
To reset the VTRIP voltage, apply a voltage between
2.7 and 5.5V to the VCC pin. Tie the CS/WDI pin, the
WP pin, AND THE SCK pin HIGH. RESET and SO
pins are left unconnected. Then apply the programming voltage VP to the SI pin ONLY and pulse CS/WDI
LOW then HIGH. Remove VP and the sequence is
complete.
Figure 2. Reset VTRIP Voltage
VCC Threshold Reset Procedure
The X5163/X5165 has a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or
for higher precision in the VTRIP value, the X5163/
X5165 threshold may be adjusted.
CS
SCK
VCC
VP
SI
Setting the VTRIP Voltage
This procedure sets the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and the
new VTRIP is 4.6V, this procedure directly makes the
change. If the new setting is lower than the current setting, then it is necessary to reset the trip point before
setting the new value.
REV 1.1 3/5/01
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Characteristics subject to change without notice.
3 of 21
X5163/X5165 – Preliminary Information
Figure 3. VTRIP Programming Sequence Flow Chart
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied =
Old VCC applied + Error
Execute
Set VTRIP
Sequence
New VCC Applied =
Old VCC applied - Error
Apply 5V to VCC
Execute
Reset VTRIP
Sequence
Decrement VCC
(VCC = VCC - 50mV)
NO
RESET pin
goes active?
YES
Error > -Emax
Measured VTRIP –
Desired VTRIP
Error > Emax
Error < Emax
Emax = Maximum Desired Error
REV 1.1 3/5/01
DONE
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Characteristics subject to change without notice.
4 of 21
X5163/X5165 – Preliminary Information
Figure 4. Sample VTRIP Reset Circuit
VP
NC
4.7K
NC
VTRIP
Adj.
+
4.7K
RESET
1
8
2
7
X5163/65
3
6
4
5
NC
Program
SPI SERIAL MEMORY
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
REV 1.1 3/5/01
Reset VTRIP
Test VTRIP
Set VTRIP
10K
10K
Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time,
even during a Write Cycle. The Status Register is formatted as follows:
7
6
5
4
3
2
1
0
WPEN
FLB
WD1
WD0
BL1
BL0
WEL
WIP
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a nonvolatile write operation is in progress. When set to a
“0”, no write is in progress.
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Characteristics subject to change without notice.
5 of 21
X5163/X5165 – Preliminary Information
Table 1. Instruction Set
Instruction Name
Instruction Format*
Operation
WREN
0000 0110
Set the Write Enable Latch (Enable Write Operations)
SFLB
0000 0000
Set Flag Bit
WRDI/RFLB
0000 0100
Reset the Write Enable Latch/Reset Flag Bit
RSDR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)
READ
0000 0011
Read Data from Memory Array Beginning at Selected Address
WRITE
0000 0010
Write Data to Memory Array Beginning at Selected Address
Note:
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
WREN CMD Status Register
Device Pin
Block
Block
Status Register
WEL
WPEN
WP#
Protected Block
Unprotected Block
WPEN, BL0, BL1,
WD0, WD1
0
X
X
Protected
Protected
Protected
1
1
0
Protected
Writable
Protected
1
0
X
Protected
Writable
Writable
1
X
1
Protected
Writable
Writable
The Write Enable Latch (WEL) bit indicates the Status
of the Write Enable Latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are programmed
using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM
array. Any portion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock
protection of that portion of memory.
Status
Register Bits
Array Addresses Protected
BL1
BL0
X516x
0
0
None
0
1
$0600–$07FF
1
0
$0400–$07FF
1
1
$0000–$07FF
REV 1.1 3/5/01
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time Out Period. These nonvolatile bits are
programmed with the WRSR instruction.
Status Register Bits
WD1
WD0
Watchdog Time Out
(Typical)
0
0
1.4 seconds
0
1
600 milliseconds
1
0
200 milliseconds
1
1
disabled
The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB
and RFLB instructions. The Flag bit is automatically
reset upon power up. This flag can be used by the system to determine whether a reset occurs as a result of
a watchdog time out or power failure.
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with
the WP pin to provide an In-Circuit Programmable
ROM function (Table 2). WP is LOW and WPEN bit programmed HIGH disables all Status Register Write
Operations.
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Characteristics subject to change without notice.
6 of 21
X5163/X5165 – Preliminary Information
Figure 5. Read EEPROM Array Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25
26 27 28 29 30
SCK
Instruction
16 Bit Address
15 14 13
SI
3
2
1
0
Data Out
High Impedance
7
SO
6
5
4
3
2
1
0
MSB
In Circuit Programmable ROM Mode
This mechanism protects the block lock and Watchdog
bits from inadvertent corruption.
In the locked state (Programmable ROM Mode) the
WP pin is LOW and the nonvolatile bit WPEN is “1”.
This mode disables nonvolatile writes to the device’s
Status Register.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation disables subsequent write attempts to the Status Register.
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting
the WPEN bit in the Status Register to “0” blocks the
WP pin function, allowing writes to the Status Register
when WP is HIGH or LOW. Setting the WPEN bit to “1”
while the WP pin is LOW activates the Programmable
ROM mode, thus requiring a change in the WP pin
prior to subsequent Status Register changes. This
allows manufacturing to install the device in a system
with WP pin grounded and still be able to program the
Status Register. Manufacturing can then load Configuration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to
be protected by setting the block lock bits, and finally
set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
REV 1.1 3/5/01
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequentially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 1).
To read the Status Register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the Status Register are shifted out on the SO line.
Refer to the Read Status Register Sequence (Figure 2).
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the
Write Operation without taking CS HIGH after issuing
the WREN instruction, the Write Operation will be
ignored.
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Characteristics subject to change without notice.
7 of 21
X5163/X5165 – Preliminary Information
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be “0’s”. The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation.
If the address counter reaches the end of a page and
the clock continues, the counter will roll back to the first
address of the page and overwrite any data that may
have been previously written.
OPERATIONAL NOTES
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 4).
– Reset Signal is active for tPURST.
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The Write Enable Latch is reset.
– The Flag Bit is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits
0 and 1 must be “0”.
– A WREN instruction must be issued to set the Write
Enable Latch.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
While the write is in progress following a Status Register or EEPROM Sequence, the Status Register may be
read to check the WIP bit. During this time the WIP bit
will be high.
Figure 6. Read Status Register Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14
SCK
Instruction
SI
Data Out
SO
High Impedance
7
6
5
4
3
2
1
0
MSB
REV 1.1 3/5/01
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Characteristics subject to change without notice.
8 of 21
X5163/X5165 – Preliminary Information
Figure 7. Write Enable Latch Sequence
CS
0
1
2
3
4
9
10
5
6
7
SCK
SI
High Impedance
SO
Figure 8. Write Sequence
CS
0
1
2
3
4
5
6
7
8
20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16 Bit Address
15 14 13
3 2
SI
1
0
7
6
5
Data Byte 1
4 3 2
1
0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
7
6
5
Data Byte 2
4 3 2
1
0
7
Data Byte 3
5 4 3 2
6
1
0
6
5
Data Byte N
4
3 2
1
0
Figure 9. Status Register Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
7
6
5
11 12 13 14 15
SCK
Instruction
SI
SO
REV 1.1 3/5/01
Data Byte
4
3
2
1
0
High Impedance
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Characteristics subject to change without notice.
9 of 21
X5163/X5165 – Preliminary Information
SYMBOL TABLE
WAVEFORM
REV 1.1 3/5/01
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
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Characteristics subject to change without notice.
10 of 21
X5163/X5165 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ........................–65 to +135°C
Storage temperature .............................–65 to +150°C
Voltage on any pin with
respect to VSS ......................................–1.0V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Device Option
Supply Voltage
Commercial
0°C
70°C
–2.7 or -2.7A
2.7V to 5.5V
Industrial
–40°C
+85°C
Blank or -4.5A
4.5V-5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
ICC1
Max.
Unit
Test Conditions
VCC Write Current (Active)
5
mA
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
ICC2
VCC Read Current (Active)
0.4
mA
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
ISB1
VCC Standby Current
WDT = OFF
1
µA
CS = VCC, VIN = VSS or VCC,
VCC = 5.5V
ISB2
VCC Standby Current
WDT = ON
50
µA
CS = VCC, VIN = VSS or VCC,
VCC = 5.5V
ISB3
VCC Standby Current
WDT = ON
20
µA
CS = VCC, VIN = VSS or VCC,
VCC = 3.6V
ILI
Input Leakage Current
0.1
10
µA
VIN = VSS to VCC
ILO
Output Leakage Current
0.1
10
µA
VOUT = VSS to VCC
VIL(1)
Min.
Typ.
Input LOW Voltage
–0.5
VCC x 0.3
V
VIH
Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output LOW Voltage
0.4
V
VCC > 3.3V, IOL = 2.1mA
VOL2
Output LOW Voltage
0.4
V
2V < VCC ≤ 3.3V, IOL = 1mA
VOL3
Output LOW Voltage
0.4
V
VCC ≤ 2V, IOL = 0.5mA
VOH1
Output HIGH Voltage
VCC – 0.8
V
VCC > 3.3V, IOH = –1.0mA
VOH2
Output HIGH Voltage
VCC – 0.4
V
VOH3
Output HIGH Voltage
VCC – 0.2
V
VCC ≤ 2V, IOH = –0.25mA
VOLS
Reset Output LOW Voltage
V
IOL = 1mA
(1)
REV 1.1 3/5/01
0.4
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2V < VCC ≤ 3.3V, IOH = –0.4mA
Characteristics subject to change without notice.
11 of 21
X5163/X5165 – Preliminary Information
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
(2)
COUT
(2)
CIN
Test
Max.
Unit
Conditions
Output Capacitance (SO, RESET, RESET)
8
pF
VOUT = 0V
Input Capacitance (SCK, SI, CS, WP)
6
pF
VIN = 0V
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
5V
A.C. TEST CONDITIONS
5V
3.3KΩ
1.64KΩ
Output
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x0.5
RESET/RESET
1.64KΩ
100pF
30pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Serial Input Timing
2.7-5.5V
Symbol
Parameter
Min.
Max.
Unit
0
2
MHz
fSCK
Clock Frequency
tCYC
Cycle Time
500
ns
tLEAD
CS Lead Time
250
ns
tLAG
CS Lag Time
250
ns
tWH
Clock HIGH Time
200
ns
tWL
Clock LOW Time
200
ns
tSU
Data Setup Time
50
ns
tH
Data Hold Time
50
ns
(3)
Input Rise Time
100
ns
(3)
Input Fall Time
100
ns
tRI
tFI
tCS
(4)
tWC
REV 1.1 3/5/01
CS Deselect Time
500
Write Cycle Time
ns
10
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ms
Characteristics subject to change without notice.
12 of 21
X5163/X5165 – Preliminary Information
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
SI
SO
tRI
tFI
MSB IN
LSB IN
High Impedance
Serial Output Timing
2.7–5.5V
Symbol
Parameter
Min.
Max.
Unit
fSCK
Clock Frequency
2
MHz
tDIS
Output Disable Time
250
ns
Output Valid from Clock Low
200
ns
tV
tHO
0
Output Hold Time
0
ns
(3)
Output Rise Time
100
ns
(3)
Output Fall Time
100
ns
tRO
tFO
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
SO
SI
REV 1.1 3/5/01
MSB OUT
tHO
MSB–1 OUT
tWL
tDIS
LSB OUT
ADDR
LSB IN
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Characteristics subject to change without notice.
13 of 21
X5163/X5165 – Preliminary Information
Power-Up and Power-Down Timing
VTRIP
VCC
VTRIP
tPURST
0 Volts
tF
tPURST
tRPD
tR
RESET (X5163)
RESET (X5165)
RESET Output Timing
Symbol
VTRIP
VTH
tPURST
(5)
tRPD
(5)
Parameter
Reset Trip Point Voltage, X5163-4.5A, X5163-4.5A
Reset Trip Point Voltage, X5163, X5165
Reset Trip Point Voltage, X5163-2.7A, X5165-2.7A
Reset Trip Point Voltage, X5163-2.7, X5165-2.7
Min.
Typ.
Max.
Unit
4.5
4.25
2.85
2.55
4.63
4.38
2.92
2.63
4.75
4.5
3.0
2.7
V
VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage)
Power-up Reset Time Out
20
100
VCC Detect to Reset/Output
200
mV
280
ms
500
ns
tF
VCC Fall Time
100
µs
tR(5)
VCC Rise Time
100
µs
1
V
VRVALID
Reset Valid VCC
Notes: (5) This parameter is periodically sampled and not 100% tested.
(6) Typical values not tested.
CS/WDI vs. RESET/RESET Timing
CS/WDI
tCST
RESET
tWDO
tRST
tWDO
tRST
RESET
REV 1.1 3/5/01
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Characteristics subject to change without notice.
14 of 21
X5163/X5165 – Preliminary Information
RESET/RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
Watchdog Time Out Period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
100
450
1
200
600
1.4
300
800
2
ms
ms
sec
tCST
CS Pulse Width to Reset the Watchdog
400
tRST
Reset Time Out
100
tWDO
ns
200
300
ms
VTRIP Set Conditions
tTHD
VCC
VTRIP
tTSU
tVPS
CS
tRP
tP
tVPH
tVPH
tVPS
tVPO
VP
SCK
VP
tVPO
SI
VTRIP Reset Conditions
tTHD
VCC
VTRIP
tTSU
tVPS
CS
SCK
tVPS
tRP
tP
tVP1
tVPH
tVPO
VCC
VP
tVPO
SI
REV 1.1 3/5/01
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Characteristics subject to change without notice.
15 of 21
X5163/X5165 – Preliminary Information
VTRIP Programming Specifications: VCC = 1.7–5.5V; Temperature = 0°C to 70°C
Parameter
Description
Min. Max.
Unit
tVPS
SCK VTRIP Program Voltage Setup time
1
µs
tVPH
SCK VTRIP Program Voltage Hold time
1
µs
VTRIP Program Pulse Width
1
µs
tTSU
VTRIP Level Setup time
10
µs
tTHD
VTRIP Level Hold (stable) time
10
ms
tWC
VTRIP Write Cycle Time
tRP
VTRIP Program Cycle Recovery Period (Between successive programming cycles)
10
ms
SCK VTRIP Program Voltage Off time before next cycle
0
ms
tP
tVPO
10
ms
Programming Voltage
15
18
V
VTRIP Programed Voltage Range
1.7
5.0
V
Vta1
Initial VTRIP Program Voltage accuracy (VCC applied—VTRIP) (Programmed at 25°C.)
-0.1
+0.4
V
Vta2
Subsequent VTRIP Program Voltage accuracy [(VCC applied—Vta1)—VTRIP)
(Programmed at 25°C.)
-25
+25
mV
Vtr
VTRIP Program Voltage repeatability (Successive program operations.) (Programmed
at 25°C.)
-25
+25
mV
Vtv
VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.)
-25
+25
mV
VP
VTRAN
VTRIP programming parameters are periodically sampled and are not 100% tested.
REV 1.1 3/5/01
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Characteristics subject to change without notice.
16 of 21
X5163/X5165 – Preliminary Information
VCC Supply Current vs. Temperature (ISB)
tWDO vs. Voltage/Temperature (WD1, 0 = 1, 1)
1.9
18
Watchdog Timer On (VCC = 5V)
16
1.8
1.7
Reset (seconds)
14
Isb (µA)
12
Watchdog Timer On (VCC = 5V)
10
8
6
4
1.3
1.2
1
–40
25
Temp (°C)
1.7
90
VTRIP vs. Temperature (programmed at 25°C)
4.5
5.2
0.75
Reset (seconds)
4.975
3.525
VTRIP = 3.5V
3.500
3.475
2.525
–40°C
0.7
25°C
0.65
90°C
0.6
0.55
0.5
VTRIP = 2.5V
2.500
0.45
2.475
0
25
Temperature
1.7
85
tPURST vs. Temperature
2.4
3.1
3.8
Voltage
4.5
5.2
4.5
5.2
tWDO vs. Voltage/Temperature (WD1, 0 0 = 0, 1)
205
200
200
195
195
Reset (seconds)
205
190
185
180
175
170
165
REV 1.1 3/5/01
3.1
3.8
Voltage
0.8
VTRIP = 5V
5.000
160
–40
2.4
tWDO vs. Voltage/Temperature (WD1, 0 = 1, 0)
5.025
Voltage
90°C
1.4
0
Time (ms)
25°C
1.5
1.1
Watchdog Timer Off (VCC = 3V, 5V)
2
–40°C
1.6
–40°C
25°C
190
185
90°C
180
175
170
165
160
25
Degrees °C
90
1.7
2.4
3.1
3.8
Voltage
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Characteristics subject to change without notice.
17 of 21
X5163/X5165 – Preliminary Information
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"Typical
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1 3/5/01
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Characteristics subject to change without notice.
18 of 21
X5163/X5165 – Preliminary Information
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1 3/5/01
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Characteristics subject to change without notice.
19 of 21
X5163/X5165 – Preliminary Information
Ordering Information
VCC
Range
VTRIP
Range
Package
Operating Temperature
Range
4.5-5.5V
4.5.4.75
8-Pin PDIP
0oC - 70oC
8L SOIC
0oC - 70oC
oC
-40
14L TSSOP
oC
0
-
oC
-40
4.5-5.5V
4.25.4.5
8-Pin PDIP
8L SOIC
14L TSSOP
oC
0
-
8L SOIC
X5165S8-4.5A
X5163S8I-4.5A
- 85oC
70oC
X5163P
X5165P
X5163S8
X5165S8
X5163S8I
0oC - 70oC
X5163V14
oC
0
-40
oC
0
-
85oC
- 70oC
oC
14L TSSOP
X5163S8-4.5A
-40oC - 85oC
-40
2.85-3.0
Part Number RESET
(Active HIGH)
70oC
0oC - 70oC
oC
2.7-5.5V
-
85oC
Part Number RESET
(Active LOW)
-
X5163S8-2.7A
85oC
- 70oC
-40oC - 85oC
2.7-5.5V
2.55-2.7
8L SOIC
0oC - 70oC
X5163S8-2.7
X5165S8-2.7
-40oC - 85oC
14L TSSOP
0oC - 70oC
oC
-40
-
X5163V14-2.7
85oC
Part Mark Information
X5163/65 W
X
Blank = 8-Lead SOIC
V = 14 Lead TSSOP
Blank = 5V ±10%, 0°C to +70°C, VTRIP = 4.25-4.5
A = 5V±10%, 0°C to +70°C, VTRIP = 4.5-4.75
I = 5V ±10%, –40°C to +85°C, VTRIP = 4.25-4.5
IA = 5V ±10%, –40°C to +85°C, VTRIP = 4.5-4.75
F = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.55-2.7
FA = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.85-3.0
G = 2.7V to 5.5V, –40°C to +85°C, VTRIP = 2.55-2.7
GA = 2.7V to 5.5V, –40°C to +85°C, VTRIP = 2.85-3.0
REV 1.1 3/5/01
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Characteristics subject to change without notice.
20 of 21
X5163/X5165 – Preliminary Information
LIMITED WARRANTY
©Xicor, Inc. 2001 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS AND TRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
REV 1.1 3/5/01
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Characteristics subject to change without notice.
21 of 21