X68257 68XX Microcontroller Family Compatible X68257 256K 32,768 x 8 Bit E2 Micro-Peripheral FEATURES DESCRIPTION • Multiplexed Address/Data Bus —Direct Interface to Popular 68HC11 Family • High Performance CMOS —Fast Access Time, 120ns —Low Power —60mA Active Maximum —500µA Standby Maximum • Software Data Protection • Toggle Bit Polling —Early End of Write Detection • Page Mode Write —Allows up to 128 Bytes to be Written in One Write Cycle • High Reliability —Endurance: 10,000 Write Cycle —Data Retention: 100 Years • 28-Lead PDIP Package • 28-Lead SOIC Package • 32-Lead PLCC Package The X68257 is an 32K x 8 E2PROM fabricated with advanced CMOS Textured Poly Floating Gate Technology. The X68257 features a multiplexed address and data bus allowing direct interface to a variety of popular single-chip microcontrollers operating in expanded multiplexed mode without the need for additional interface circuitry. FUNCTIONAL DIAGRAM CE, CE R/W E SEL A8–A14 AS CONTROL LOGIC L A T C H E S SOFTWARE DATA PROTECT X D E C O D E 32K x 8 E2PROM Y DECODE I/O & ADDRESS LATCHES AND BUFFERS A/D0–A/D7 6539 ILL F02.2 © Xicor, Inc. 1994, 1995, 1996 Patents Pending 6539-1.7 9/16/96 T0/C1/D2 SH 1 Characteristics subject to change without notice X68257 PIN DESCRIPTIONS PIN CONFIGURATION Address/Data (A/D0–A/D7) PDIP SOIC Multiplexed low-order addresses and data. The addresses flow into the device while AS is HIGH. After AS transitions from a HIGH to LOW the addresses are latched. Once the addresses are latched these pins input data or output data depending on R/W, SEL, and CE. Addresses (A8–A14) High order addresses flow into the device when AS = VIH and are latched when AS goes LOW. Chip Enable (CE) A14 1 28 A12 2 27 AS 3 26 SEL 4 25 CE 5 24 NC 6 23 NC 7 X68257 22 NC 8 21 NC VCC R/W A13 A8 A9 A11 E A10 CE 9 20 The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, AS is LOW, and CE is LOW, the X68257 is placed in the low power standby mode. NC 10 19 A/D0 11 18 A/D1 12 17 A/D2 13 16 A/D5 A/D4 Chip Enable (CE) VSS 14 15 A/D3 A/D7 A/D6 Chip Enable is active HIGH. When CE is used to select the device, the CE must be tied HIGH. 6539 FHD F01.3 3 2 A13 A14 NC 4 R/W A12 Read/Write (R/W) AS When the X68257 is to be used in a 68XX-based system, SEL is tied to VSS. VCC PLCC Program Store Enable (SEL) SEL 5 1 32 31 30 29 A8 CE 6 28 A9 NC 7 27 A11 NC 8 26 NC Address Strobe (AS) NC 9 25 E NC 10 24 A10 NC 11 23 CE NC 12 22 A/D7 13 21 14 15 16 17 18 19 20 A/D6 A/D4 A/D3 Address Strobe Address Inputs/Data I/O Address Inputs Enable Input Read/Write Input Chip Enable Device Select—Connect to VSS Ground Supply Voltage No Connect NC AS A/D0–A/D7 A8–A14 E R/W CE, CE SEL VSS VCC NC Description A/D1 Symbol VSS A/D0 PIN NAMES A/D2 Addresses flow through the latches to address decoders when AS is HIGH and are latched when AS transitions from a HIGH to LOW. X68257 A/D5 When the X68257 is to be used in a 68XX-based system, R/W is tied directly to the microcontroller’s R/W output. 6539 FHD F01A.5 6539 PGM T01.2 2 X68257 PRINCIPLES OF OPERATION DEVICE OPERATION The X68257 is a highly integrated peripheral device for a wide variety of single-chip microcontrollers. The X68257 provides 32K-bytes of 5V E2PROM which can be used either for program storage, data storage, or a combination of both, in systems based upon Von Neumann (68XX) architectures. The X68257 incorporates the interface circuitry normally needed to decode the control signals and demultiplex the address/data bus to provide a “seamless” interface. Motorola 68XX operation requires the microcontroller AS, E, and R/W outputs to be tied to the X68257 AS, E, and R/W inputs respectively. The falling edge of AS will latch the addresses for both a read and write operation. The state of the R/W output determines the operation to be performed, with the E signal acting as a data strobe. If R/W is HIGH and CE is HIGH (read operation) data will be output on A/D0–A/D7 after E transitions HIGH. If R/W is LOW and CE is HIGH (write operation) data present at A/D0–A/D7 will be strobed into the X68257 on the HIGH to LOW transition of E. The interface inputs on the X68257 are configured such that it is possible to directly connect them to the proper interface signals of the appropriate single-chip microcontroller. The X68257 features the industry standard 5V E2PROM characteristics such as byte or page mode write and Toggle Bit Polling. Typical Application U? 30 29 39 41 40 8 7 6 5 4 3 2 1 25 24 42 43 44 45 46 47 U? XTAL PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 EXTAL RESET IRQ XIRQ PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 MODA MODB PD0 PD1 PD2 PD3 PD4 PD5 AS R/W MISO MOSI SCK SS E PE0 PE1 PE2 PE3 VRH VRL 68HC11 31 32 33 34 35 36 37 38 11 12 12 15 16 17 18 19 16 15 14 13 12 11 10 9 25 24 21 23 2 26 1 5 26 28 3 27 27 22 17 18 19 20 A/D0 A/D1 A/D2 A/D3 A/D4 A/D5 A/D6 A/D7 A8 A9 A10 A11 A12 A13 A14 CE AS R/W VCC CE SEL 20 4 E X68257 22 21 6539 ILL F03.2 3 X68257 MODE SELECTION CE E R/W Mode VSS LOW HIGH HIGH X X HIGH X X HIGH LOW Standby Standby Read Write I/O Power High Z High Z DOUT DIN Standby (CMOS) Standby (TTL) Active Active 6539 PGM T02.2 PAGE WRITE OPERATION Regardless of the microcontroller employed, the X68257 supports page mode write operations. This allows the microcontroller to write from 1 to 128 bytes of data to the X68257. Each individual write within a page write operation must conform to the byte write timing requirements. The rising edge of E starts a timer delaying the internal programming cycle 100µs. Therefore, each successive write operation must begin within 100µs of the last byte written. The following waveforms illustrate the sequence and timing requirements. Page Write Timing Sequence for E Controlled Operation OPERATION BYTE 1 BYTE 0 BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR NEXT WRITE OPERATION CE AS A/D0–A/D7 A8–A14 AIN AIN DIN An DIN An AIN AIN DIN An DIN An AIN AIN DIN An ADDR AIN Next Address E R/W tBLC tWC 6539 FHD F07.1 Note: (1) For each successive write within a page write cycle A7–A14 must be the same. 4 X68257 Toggle Bit Polling subsequent attempts to read the device. When the internal cycle is complete, the toggling will cease and the device will be accessible for additional read or write operations. Because the typical write timing is less than the specified 5ms, Toggle Bit Polling has been provided to determine the early end of write. During the internal programming cycle I/O6 will toggle from “1” to “0” and “0” to “1” on Toggle Bit Polling E Control OPERATION LAST BYTE WRITTEN I/O6=X I/O6=X I/O6=X I/O6=X AIN AIN AIN AIN X68257 READY FOR NEXT OPERATION CE AS A/D0–A/D7 A8–A14 AIN DIN An DOUT An DOUT An DOUT An DOUT An AIN ADDR E R/W 6539 FHD F08.2 5 X68257 Software Data Protection SYMBOL TABLE Software Data Protection (SDP) is employed to protect the entire array against inadvertent writes. To write to the X68257, a three-byte command sequence must precede the byte(s) being written. WAVEFORM All write operations, both the command sequence and any data write operations must conform to the page write timing requirements. Writing with SDP WRITE AA TO 5555 WRITE 55 TO 2AAA WRITE A0 TO 5555 PERFORM BYTE OR PAGE WRITE OPERATIONS WAIT tWC EXIT ROUTINE 6539 FHD F09.1 6 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance X68257 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS .................................. –1V to +7V D.C. Output Current ............................................. 5mA Lead Temperature (Soldering, 10 seconds) .............................. 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits Commercial Industrial Military 0°C –40°C –55°C +70°C +85°C +125°C X68257 5V ±10% 6539 PGM T04.1 6539 PGM T03.1 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions CE = VIL, All I/O’s = Open, Other Inputs = VCC, AS = VIH CE = VSS, All I/O’s = Open,Other Inputs = VCC – 0.3V, AS = VSS CE = VIH, All I/O’s = Open, Other Inputs = VIH, AS = VIL VIN = VSS to VCC VOUT = VSS to VCC, E = VIL ICC VCC Current (Active) 60 mA ISB1(CMOS) VCC Current (Standby) 500 µA ISB2(TTL) VCC Current (Standby) 6 mA ILI ILO VlL(1) VIH(1) VOL VOH Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage 10 10 0.8 VCC + 0.5 0.4 µA µA V V V V –1 2 2.4 IOL = 2.1mA IOH = –400µA 6539 PGM T05.1 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol CI/O(2) CIN(2) Test Max. Units Conditions Input/Output Capacitance Input Capacitance 10 6 pF pF VI/O = 0V VIN = 0V 6539 PGM T06 POWER-UP TIMING Symbol Parameter Max. Units tPUR(2) tPUW(2) Power-Up to Read Power-Up to Write 1 5 ms ms 6539 PGM T07 Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 7 X68257 A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels TEST CIRCUIT 0V to 3V 5V 10ns 1.92KΩ 1.5V OUTPUT 6539 PGM T08.1 1.37KΩ 100pF 6539 FHD F04.2 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) E Controlled Read Cycle Symbol Parameter Min. PWASH tASL tAHL tACC tDHR tCSL PWEH tES tEH tRWS tHZ(3) tLZ(3) Address Strobe Pulse Width Address Setup Time Address Hold Time Data Access Time Data Hold Time CE Setup Time E Pulse Width Enable Setup Time E Hold Time R/W Setup Time E LOW to High Z Output E HIGH to Low Z Output 80 20 30 Max. 120 0 7 150 30 20 20 50 0 Units ns ns ns ns ns ns ns ns ns ns ns ns 6539 PGM T09.1 E Controlled Read Cycle CE PWASH tCSL tEH tEH tES AS tASL A/D0–A/D7 tAHL AIN DOUT tACC A8–A14 tDHR A8–A14 tHZ R/W tRWS tEH E PWEH 6539 FHD F05.2 Note: (3) This parameter is periodically sampled and not 100% tested. 8 X68257 E Controlled Write Cycle Symbol PWASH tASL tAHL tDSW tDHW tCSL PWEH tWC tES tRWS tEH 6539 FHD F05.2 tBLC Parameter Min. Address Strobe Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time CE Setup Time E Pulse Width Write Cycle Time Enable Setup Time R/W Setup Time E Hold Time Byte Load Time (Page Write) 80 20 30 50 30 7 120 Max. 5 30 20 20 0.5 100 Units ns ns ns ns ns ns ns ms ns ns ns µs 6539 PGM T10 E Controlled Write Cycle CE PWASH tCSL tEH tEH tES AS tASL A/D0–A/D7 tAHL AIN DIN tDSW A8–A14 tDHW A8–A14 tEH tRWS R/W E PWEH Note: 6539 FHD F06.2 (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 9 X68257 WR Controlled Write Cycle Symbol Parameter tLHLL tAVLL tLLAX tDVWH tWHDX tELLL tWLWH tWRS tWRH tBLC tWC (7) Min. ALE Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Chip Enable Setup Time WR Pulse Width WR Setup Time WR Hold Time Byte Load Time (Page Write) Write Cycle Time 80 20 30 50 30 7 120 30 20 0.5 Max. Units 100 5 ns ns ns ns ns ns ns ns ns µs ms 6539 PGM T11 WR Controlled Write Timing Diagram OPERATION BYTE 1 BYTE 0 BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR NEXT WRITE OPERATION CE AS A/D0–A/D7 A8–A14 AIN AIN DIN An DIN An AIN AIN DIN An DIN An AIN AIN DIN ADDR An AIN Next Address E R/W tBLC tWC 6539 FHD F07.1 Note: (7) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 10 X68257 PACKAGING INFORMATION 28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 1.470 (37.34) 1.400 (35.56) 0.557 (14.15) 0.510 (12.95) PIN 1 INDEX PIN 1 0.085 (2.16) 0.040 (1.02) 1.300 (33.02) REF. 0.160 (4.06) 0.125 (3.17) SEATING PLANE 0.030 (0.76) 0.015 (0.38) 0.160 (4.06) 0.120 (3.05) 0.110 (2.79) 0.090 (2.29) 0.065 (1.65) 0.040 (1.02) 0.022 (0.56) 0.014 (0.36) 0.625 (15.88) 0.590 (14.99) 0° 15° TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 3926 FHD F04 11 X68257 PACKAGING INFORMATION 28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.299 (7.59) 0.290 (7.37) 0.419 (10.64) 0.394 (10.01) 0.020 (0.508) 0.014 (0.356) 0.713 (18.11) 0.697 (17.70) 0.105 (2.67) 0.092 (2.34) BASE PLANE SEATING PLANE 0.012 (0.30) 0.003 (0.08) 0.050 (1.270) BSC 0.050" TYPICAL 0.0200 (0.5080) X 45° 0.0100 (0.2540) 0.050" TYPICAL 0.013 (0.32) 0.008 (0.20) 0° – 8° 0.42" MAX 0.0350 (0.8890) 0.0160 (0.4064) FOOTPRINT 0.030" TYPICAL 28 PLACES NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES 3926 FHD F17 12 X68257 PACKAGING INFORMATION 32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J 0.050" TYPICAL 0.420 (10.67) 0.030" TYPICAL 32 PLACES 0.050" TYPICAL 0.510" TYPICAL 0.400" 0.050 (1.27) TYP. 0.300" REF 0.410" FOOTPRINT 0.045 (1.14) x 45° 0.021 (0.53) 0.013 (0.33) TYP. 0.017 (0.43) 0.495 (12.57) 0.485 (12.32) TYP. 0.490 (12.45) 0.453 (11.51) 0.447 (11.35) TYP. 0.450 (11.43) 0.300 (7.62) REF. SEATING PLANE ±0.004 LEAD CO – PLANARITY — 0.015 (0.38) 0.095 (2.41) 0.060 (1.52) 0.140 (3.56) 0.100 (2.45) TYP. 0.136 (3.45) 0.048 (1.22) 0.042 (1.07) PIN 1 0.595 (15.11) 0.585 (14.86) TYP. 0.590 (14.99) 0.553 (14.05) 0.547 (13.89) TYP. 0.550 (13.97) 0.400 (10.16)REF. 3° TYP. NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY 3926 FHD F13 13 X68257 ORDERING INFORMATION X68257 X X Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C Device Package P = 28-Lead Plastic DIP S = 28-Lead SOIC J = 32-Lead PLCC LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. 14