X28HT512 X28HT512 512K 64K x 8 Bit High Temperature, 5 Volt, Byte Alterable E2PROM FEATURES • 175°C Full Functionality • • DESCRIPTION The X28HT512 is an 64K x 8 CMOS E2PROM, fabricated with Xicor’s proprietary, high performance, floating gate CMOS technology which provides Xicor products superior high temperature performance characteristics. Like all Xicor programmable nonvolatile memories the X28HT512 is a 5V only device. The X28HT512 features the JEDEC approved pinout for bytewide memories, compatible with industry standard EPROMS. Simple Byte and Page Write —Single 5V Supply —Self-Timed —No Erase Before Write —No Complex Programming Algorithms —No Overerase Problem Highly Reliable Direct Write™ Cell —Endurance: 10,000 Write Cycles —Data Retention: 100 Years —Higher Temperature Functionality is Possible by Operating in the Byte Mode The X28HT512 supports a 128-byte page write operation, effectively providing a 39µs/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. PIN CONFIGURATION FLAT PACK CERDIP SOIC (R) PGA VBB 1 32 VCC NC 2 31 WE A15 3 30 NC A12 4 29 A14 A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE A0 12 21 I/O0 I/O1 13 20 I/O7 I/O6 14 19 I/O2 VSS 15 18 I/O5 I/04 16 17 I/O3 X28HT512 I/O0 I/O2 I/O3 I/O5 I/O6 15 17 19 21 22 A1 13 A0 14 A2 12 A3 11 A4 10 9 CE I/O1 VSS I/O4 I/O7 16 18 20 23 24 X28HT512 A5 A10 25 OE 26 A11 27 A9 28 A8 29 A13 30 NC 32 A14 31 (BOTTOM VIEW) A6 8 A12 6 A7 7 A15 5 NC 2 V NC 4 VCC NC 36 34 3 BB NC 1 WE 35 NC 33 6614 FHD F23 6614 FHD F02.1 © Xicor, Inc. 1991, 1995, 1996 Patents Pending 6614-1.5 8/5/97 T2/C0/D0 EW 1 Characteristics subject to change without notice X28HT512 PIN DESCRIPTIONS Write Enable (WE) Addresses (A0–A15) The Write Enable input controls the writing of data to the X28HT512. The Address inputs select an 8-bit memory location during a read or write operation. PIN NAMES Chip Enable (CE) Symbol A0–A15 I/O0–I/O7 WE CE OE VBB VCC VSS NC The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/Data Out (I/O0–I/O7) Data is written to or read from the X28HT512 through the I/O pins. Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable –3V +5V Ground No Connect 6614 PGM T01 Back Bias Voltage (VBB) It is required to provide -3V on pin 1. This negative voltage improves higher temperature functionality. FUNCTIONAL DIAGRAM A7–A15 X BUFFERS LATCHES AND DECODER A0–A6 Y BUFFERS LATCHES AND DECODER 512K-BIT E2PROM ARRAY I/O BUFFERS AND LATCHES I/O0–I/O7 DATA INPUTS/OUTPUTS CE OE WE CONTROL LOGIC AND TIMING VCC VSS 6614 FHD F01 VBB 2 X28HT512 DEVICE OPERATION • Default VCC Sense—All write functions are inhibited when VCC is ≤3.4V. • Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. Write cycle timing specifications must be observed concurrently. Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. SYSTEM CONSIDERATIONS Because the X28HT512 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins share the same bus. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28HT512 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. It has been demonstrated that markedly higher temperature performance can be obtained from this device if CE is left enabled throughout the read and write operation. Page Write Operation To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. The page write feature of the X28HT512 allows the entire memory to be written in 2.5 seconds. Page write allows two to one hundred twenty-eight bytes of data to be consecutively written to the X28HT512 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A15) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. Because the X28HT512 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twentyseven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100µs. In addition, it is recommended that a 4.7µF electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. HARDWARE DATA PROTECTION The X28HT512 provides three hardware features that protect nonvolatile data from inadvertent writes. • Noise Protection—A WE pulse typically less than 10ns will not initiate a write cycle. 3 X28HT512 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias X28HT512 ................................. –40°C to +175°C Voltage on any Pin with Respect to VSS ....................................... –1V to +7V D.C. Output Current ............................................. 5mA Lead Temperature (Soldering, 10 seconds) .............................. 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMEND OPERATING CONDITIONS Temperature High Temp Max. Supply Voltage Limits +175°C X28HT512 Back Bias Voltage (VBB) 5V ±5% –3V ±10% Min. –40°C 6614 PGM T02.1 6614 PGM T03.1 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.) Limits Symbol Parameter Min. Max. Units ICC VCC Current (Active) (TTL Inputs) 50 mA ISB1 VCC Current (Standby) (TTL Inputs) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Back Bias Voltage 3 mA 20 20 0.6 VCC + 1 0.5 µA µA V V V V µA ILI ILO VlL(1) VIH(1) VOL VOH VBB –1 2.2 2.6 200 Notes: (1) VIL min. and VIH max. are for reference only and are not tested. 4 Test Conditions CE = OE = VIL, WE = VIH, All I/O’s = Open, Address Inputs = .4V/2.4V Levels @ f = 5MHz CE = VIH, OE = VIL All I/O’s = Open, Other Inputs = VCC VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH IOL = 1mA IOH = –400µA VBB = –3V±10% 6614 PGM T04.2 X28HT512 POWER-UP TIMING Symbol Parameter Max. Units tPUR(2) tPUW(2) Power-up to Read Operation Power-up to Write Operation 100 5 µs ms 6614 PGM T05 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol Parameter Max. Units Test Conditions CI/O(2) CIN(2) Input/Output Capacitance Input Capacitance 10 10 pF pF VI/O = 0V VIN = 0V 6614 PGM T06 ENDURANCE AND DATA RETENTION Parameter Min. Endurance Data Retention 10,000 100 Max. Units Cycles per Byte Years 6614 PGM T11 A.C. CONDITIONS OF TEST Input Pulse Levels MODE SELECTION 0V to 3V Input Rise and Fall Times Input and Output Timing Levels 10ns CE L L H OE L H X WE H L X X X L X X H 1.5V 6614 PGM T07 Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit I/O DOUT DIN High Z Power Active Active Standby — — — — 6614 PGM T08 EQUIVALENT A.C. LOAD CIRCUIT SYMBOL TABLE WAVEFORM 5V 1.92KΩ OUTPUT 1.37KΩ 100pF 6614 FHD F22.2 Note: (2) This parameter is periodically sampled and not 100% tested. 5 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance X28HT512 A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits X28HT512-20 X28HT512-25 Symbol tRC tCE tAA tOE tLZ(3) tOLZ(3) tHZ(3) tOHZ(3) tOH Parameter Min. Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE LOW to Active Output OE LOW to Active Output CE HIGH to High Z Output OE HIGH to High Z Output Output Hold from Address Change Max. 200 Min. Max. 250 200 200 80 0 0 250 250 80 0 0 80 80 0 80 80 0 Units ns ns ns ns ns ns ns ns ns 6614 PGM T09.1 Read Cycle tRC ADDRESS tCE CE tOE OE WE VIH tOLZ tOHZ tLZ DATA I/O HIGH Z tOH DATA VALID tHZ DATA VALID tAA 6614 FHD F05 Notes: (3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. 6 X28HT512 WRITE CYCLE LIMITS Symbol Parameter Min. tWC(4) tAS tAH tCS tCH tCW tOES tOEH tWP tWPH tDV tDS tDH tDW tBLC Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time CE Pulse Width OE HIGH Setup Time OE HIGH Hold Time WE Pulse Width WE HIGH Recovery Data Valid Data Setup Data Hold Delay to Next Write Byte Load Cycle Max. 10 20 100 0 0 200 10 10 200 200 1 100 25 10 0.4 100 Units ms ns ns ns ns ns ns ns ns ns µs ns ns µs µs 6614 PGM T10.1 WE Controlled Write Cycle tWC ADDRESS tAS tAH tCS tCH CE OE tOES tOEH tWP WE tDV DATA IN DATA VALID tDS DATA OUT tDH HIGH Z 6614 FHD F06 Notes: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to complete the internal write operation. 7 X28HT512 CE Controlled Write Cycle tWC ADDRESS tAS tAH tCW CE tWPH tOES OE tOEH tCS tCH WE tDV DATA IN DATA VALID tDS tDH HIGH Z DATA OUT 6614 FHD F07 Page Write Cycle OE (5) CE tWP tBLC WE tWPH ADDRESS * (6) I/O LAST BYTE BYTE 0 BYTE 1 BYTE 2 BYTE n *For each successive write within the page write operation, A7–A15 should be the same or writes to an unknown address could occur. BYTE n+1 BYTE n+2 tWC 6614 FHD F08 Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. (6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. 8 X28HT512 PACKAGING INFORMATION 32-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D 1.690 (42.95) MAX. 0.610 (15.49) 0.500 (12.70) PIN 1 0.005 (0.13) MIN. 0.100 (2.54) MAX. SEATING PLANE 0.232 (5.90) MAX. 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN. 0.200 (5.08) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) TYP. 0.018 (0.46) 0.065 (1.65) 0.033 (0.84) TYP. 0.055 (1.40) 0.023 (0.58) 0.014 (0.36) TYP. 0.018 (0.46) 0.620 (15.75) 0.590 (14.99) TYP. 0.614 (15.60) 0° 15° 0.015 (0.38) 0.008 (0.20) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F09 9 X28HT512 PACKAGING INFORMATION 32-LEAD CERAMIC FLAT PACK TYPE F 1.228 (31.19) 1.000 (25.40) PIN 1 INDEX 1 0.019 (0.48) 0.015 (0.38) 32 0.050 (1.27) BSC 0.830 (21.08) MAX. 0.045 (1.14) MAX. 0.005 (0.13) MIN. 0.488 0.430 (10.93) 0.007 (0.18) 0.004 (0.10) 0.120 (3.05) 0.090 (2.29) 0.370 (9.40) 0.270 (6.86) 0.347 (8.82) 0.330 (8.38) 0.045 (1.14) 0.026 (0.66) 0.030 (0.76) MIN NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F20 10 X28HT512 PACKAGING INFORMATION 36-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K 15 17 19 21 22 A 0.008 (0.20) 13 14 12 11 16 18 20 23 24 25 26 0.050 (1.27) A 10 9 27 28 8 7 29 30 NOTE: LEADS 5, 14, 23, & 32 TYP. 0.100 (2.54) ALL LEADS 6 TYP. 0.180 (.010) (4.57 ± .25) 4 CORNERS 5 2 36 34 32 4 3 1 35 33 31 TYP. 0.180 (.010) (4.57 ± .25) 4 CORNERS 0.120 (3.05) 0.100 (2.54) 0.072 (1.83) 0.062 (1.57) PIN 1 INDEX 0.770 (19.56) 0.750 (19.05) SQ 0.020 (0.51) 0.016 (0.41) A A 0.185 (4.70) 0.175 (4.45) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F21 11 X28HT512 PACKAGING INFORMATION 32-LEAD CERAMIC SMALL OUTLINE GULL WING PACKAGE TYPE R 0.060 NOM. SEE DETAIL “A” FOR LEAD INFORMATION 0.020 MIN. 0.165 TYP. 0.340 ±0.007 0.015 R TYP. 0.015 R TYP. 0.035 TYP. 0.035 MIN. DETAIL “A” 0.050" TYPICAL 0.0192 0.0138 0.050" TYPICAL 0.840 MAX. 0.750 ±0.005 0.050 0.560" TYPICAL FOOTPRINT 0.030" TYPICAL 32 PLACES 0.440 MAX. 0.560 NOM. NOTES: 1. ALL DIMENSIONS IN INCHES 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES 3926 FHD F27 12 X28HT512 ORDERING INFORMATION X28HT512 X X -X Access Time –25 = 250ns –20 = 200ns Device Temperature Range Blank = 25°C to +175°C Package D = 32-Lead CerDip F = 32-Lead Flat Pack K = 36-Lead Pin Grid Array R = 32-Lead Ceramic SOIC LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. 13