ISO 7816 Compatible X76F641 64K 8Kx8+32x8 Secure SerialFlash FEATURES DESCRIPTION • 64-bit Password Security —Five 64-bit Passwords for Read, Program and Reset • 8192 Byte+32 Byte Password Protected Arrays —Seperate Read Passwords —Seperate Write Passwords —Reset Password • Programmable Passwords • Retry Counter Register —Allows 8 tries before clearing of both arrays —Password Protected Reset • 32-bit Response to Reset (RST Input) • 32 byte Sector Program • 400kHz Clock Rate • 2 wire Serial Interface • Low Power CMOS —2.0 to 5.5V operation —Standby current Less than 1µA —Active current less than 3 mA • High Reliability Endurance: —100,000 Write Cycles • Data Retention: 100 years • Available in: —8 lead EIAJ SOIC —SmartCard Module The X76F641 is a Password Access Security Supervisor, containing one 65536-bit Secure SerialFlash array and one 256-bit Secure SerialFlash array. Access to each memory array is controlled by five 64-bit passwords each. These passwords protect read and write operations of the memory array. A separate RESET password is used to reset the passwords and clear the memory arrays in the event the read and write passwords are lost. The X76F641 features a serial interface and software protocol allowing operation on a popular two wire bus. The bus signals are a clock Input (SCL) and a bidirectional data input and output (SDA). The X76F641 also features a synchronous response to reset providing an automatic output of a hard-wired 32-bit data stream conforming to the industry standard for memory cards. The X76F641 utilizes Xicor’s proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. Functional Diagram DATA TRANSFER SCL SDA INTERFACE ARRAY ACCESS ENABLE 8K BYTE SerialFlash ARRAY ARRAY 0 (PASSWORD PROTECTED) LOGIC PASSWORD ARRAY AND PASSWORD VERIFICATION LOGIC 32 BYTE SerialFlash ARRAY ARRAY 1 (PASSWORD PROTECTED) RST RESET RETRY COUNTER RESPONSE REGISTER 7025 FM 01 Xicor, Inc. 1994, 1995, 1996 Patents Pending 9900-5004.5 3/9/99 EP 1 Characteristics subject to change without notice X76F641 PIN DESCRIPTIONS PIN NAMES Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Symbol Serial Data (SDA) SDA is a true three state serial data input/output pin. During a read cycle, data is shifted out on this pin. During a write cycle, data is shifted in on this pin. In all other cases, this pin is in a high impedance state. Reset (RST) RST is a device reset pin. When RST is pulsed high the X76F641 will output 32 bits of fixed data which conforms to the standard for “synchronous response to reset”. The part must not be in a write cycle for the response to reset to occur. See Figure 11. If there is power interrupted during the Response to Reset, the response to reset will be aborted and the part will return to the standby state. The response to reset is "mask programmable" only! Description SDA Serial Data Input/Output SCL Serial Clock Input RST Reset Input Vcc Supply Voltage Vss Ground NC No Connect PIN CONFIGURATION Smart Card EIAJ SOIC VSS 1 8 VCC NC 2 7 RST DEVICE OPERATION SDA 3 6 SCL There are two primary modes of operation for the X76F641; Protected READ and protected WRITE. Protected operations must be performed with one of four 8-byte passwords. NC 4 5 NC The basic method of communication for the device is generating a start condition, then transmitting a command, followed by the correct password. All parts will be shipped from the factory with all passwords equal to ‘0’. The user must perform ACK Polling to determine the validity of the password, before starting a data transfer (see Acknowledge Polling.) Only after the correct password is accepted and a ACK polling has been performed, can the data transfer occur. VCC GND RST NC SCL SDA NC NC 7025 FM 02 After each transaction is completed, the X76F641 will reset and enter into a standby mode. This will also be the response if an unsuccessful attempt is made to access a protected array. To ensure the correct communication, RST must remain LOW under all conditions except when running a “Response to Reset sequence”. Data is transferred in 8-bit segments, with each transfer being followed by an ACK, generated by the receiving device. If the X76F641 is in a nonvolatile write cycle a “no ACK” (SDA=High) response will be issued in response to loading of the command byte. If a stop is issued prior to the nonvolatile write cycle the write operation will be terminated and the part will reset and enter into a standby mode. The basic sequence is illustrated in Figure 1. 2 X76F641 Start Condition All commands are preceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X76F641 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Figure 1. X76F641 Device Operation LOAD COMMAND BYTE LOAD 8-BYTE PASSWORD A start may be issued to terminate the input of a control byte or the input data to be written. This will reset the device and leave it ready to begin a new read or write command. Because of the push/pull output, a start cannot be generated while the part is outputting data. Starts are inhibited while a write is in progress. VERIFY PASSWORD ACCEPTANCE BY USE OF PASSWORD ACK POLLING Stop Condition All communications must be terminated by a stop condition. The stop condition is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to reset the device during a command or data input sequence and will leave the device in the standby power mode. As with starts, stops are inhibited when outputting data and while a write is in progress. LOAD 2 BYTE ADDRESS READ/WRITE DATA BYTES Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Twc OR DATA ACK POLLING 7025 FM 03 Retry Counter The X76F641 contains a retry counter. The retry counter allows 8 accesses with an invalid password before any action is taken. The counter will increment with any combination of incorrect passwords. If the retry counter overflows, all memory areas are cleared and the device is locked by preventing any read or write array password matches. The passwords are unaffected. If a correct password is received prior to retry counter overflow, the retry counter is reset and access is granted. In order to reset the operation of a locked up device, a special reset command must be used with a RESET password. The X76F641 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write condition have been selected, the X76F641 will respond with an acknowledge after the receipt of each subsequent eight-bit word. Reset Device Command The reset device command is used to clear the retry counter and reactivate the device. When the reset device command is used prior to the retry counter overflow, the retry counter is reset and no arrays or passwords are affected. If the retry counter has overflowed, all memory areas are cleared and all commands are blocked and the retry counter is disabled. Issuing a valid reset device command (with reset password) to the device resets and re-enables the retry counter and re-enables the other commands. Again, the passwords are not affected. Device Protocol The X76F641 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as a receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X76F641 will be considered a slave in all applications. Reset Password Command A reset password command will clear both arrays and set all passwords to all zero. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figure 2 and Figure 3. 3 X76F641 Figure 2. Data Validity SCL SDA Data Stable Data Change 7025 FM 04 Figure 3. Definition of Start and Stop Conditions SCL SDA Start Condition Stop Condition 7025 FM 05 Table 1. X76F641 Instruction Set 1st Byte after Start 1st Byte after Password 2nd Byte after Password Command Description Password used 1000 0000 High Address Low address Read (Array 0) Read 0 1000 1000 High Address Low address Read (Array 1) Read 1 1001 0000 High Address Low address Sector Write (Array 0) Write 0 1001 1000 High Address Low address Sector Write (Array 1) Write 1 1010 0000 0000 0000 0000 0000 Change Read 0 Password Read 0 1010 1000 0000 0000 0000 0000 Change Read 1 Password Read 1 1011 0000 0000 0000 0000 0000 Change Write 0 Password Write 0 1011 1000 0000 0000 0000 0000 Change Write 1 Password Write 1 1100 0000 0000 0000 0000 0000 Change Reset Password Reset 1110 0000 not used not used Reset Password Command Reset 1110 1000 not used not used Reset Device Command Reset 1111 0000 not used not used ACK Polling command (Ends Password operation) None All the rest Reserved 7025 FM T04 Notes: Illegal command codes will be disregarded. The part will respond with a “no-ACK” to the illegal byte and then return to the standby mode. All write/read operations require a password. 4 X76F641 PROGRAM OPERATIONS Sector Programming The sector program mode requires issuing the 8-bit write command followed by the password, password Ack command, the address and then the data bytes transferred as illustrated in figure 4. Up to 32 bytes may be transferred. After the last byte to be transferred is acknowledged a stop condition is issued which starts the nonvolatile write cycle. Write Password 7 COMMAND Write Password 0 Wait tWC OR Repeated ACK Polling Command ACK ACK ACK ACK SDA S ACK POLLING COMMAND Data 0 A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A10 A9 A8 START If ACK, Then Password Matches ... ACK Data 31 STOP ACK ACK 5 ACK S ACK NACK S ACK START Figure 4. Sector Programming Wait tWC Data ACK Polling 7025 FM 07 X76F641 ACK Polling Once a stop condition is issued to indicate the end of the host’s write sequence, the X76F641 initiates the internal nonvolatile write cycle. In order to take advantage of the typical 5ms write cycle, ACK polling can begin immediately. This involves issuing the start condition followed by the new command code of 8 bits (1st byte of the protocol.) If the X76F641 is still busy with the nonvolatile write operation, it will issue a “no-ACK” in response. If the nonvolatile write operation has completed, an “ACK” will be returned and the host can then proceed with the rest of the protocol. requires the master to perform an ACK polling with the specific code of F0h. As with regular Acknowledge polling the user can either time out for 10ms, and then issue the ACK polling once, or continuously loop as described in the flow. Password ACK Polling Sequence PASSWORD LOAD COMPLETED ENTER ACK POLLING ISSUE START Data ACK Polling Sequence WRITE SEQUENCE COMPLETED ENTER ACK POLLING ISSUE PASSWORD ACK COMMAND ISSUE START ACK RETURNED? ISSUE NEW COMMAND CODE NO YES PROCEED ACK RETURNED? NO 7025 FM 09 If the password that was inserted was correct, then an “ACK” will be returned once the nonvolatile cycle is over, in response to the ACK polling cycle immediately following it. YES PROCEED 7025 FM 08 If the password that was inserted was incorrect, then a “no ACK” will be returned even if the nonvolatile cycle is over. Therefore, the user cannot be certain that the password is incorrect until the 10ms write cycle time has elapsed. After the password sequence, there is always a nonvolatile write cycle. This is done to discourage random guesses of the password if the device is being tampered with. In order to continue the transaction, the X76F641 6 X76F641 Figure 5. Acknowledge Polling SCL 8th clk. of 8th pwd. byte SDA ‘ACK’ clk 8th clk ‘ACK’ 8th bit ‘ACK’ clk START condition ACK or no ACK 7025 FM 10 Sequential Read The host can read sequentially within an array after the password acceptance sequence. The data output is sequential, with the data from address n followed by the data from n+1. The address counter for read operations increments all address bits, allowing the entire memory array contents to be serially read during one operation. At the end of the address space (address 1FFFh for array 0, 1Fh for array 1), the counter “rolls over” to address 0 and the X76F641 continues to output data for each acknowledge received. Refer to figure 7 for the address, acknowledge and data transfer sequence. An acknowledge must follow each 8-bit data transfer. After the last bit has been read, a stop condition is generated without a preceding acknowledge. READ OPERATIONS Read operations are initiated in the same manner as write operations but with a different command code. Random Read The master issues the start condition and a Read instruction and password, performs a Password Ack Polling, then issues the word address. Once the password has been acknowledged and first byte has been read, another start can be issued followed by a new 8-bit address. Random reads are allowed, but only the low order 8 bits can change. This limits random reads to a 256 byte block. Therefore, with a single password cycle only a 256 byte block of array 0 may be accessed randomly. To randomly access another block of array 0, a stop must be issued followed by a new command/address/password sequence. A random read of the array 1 can access all locations without another password command sequence. START Figure 6. Random Read Read Password 7 COMMAND Read Password 0 ACK ACK ACK ACK SDA S Wait tWC OR Repeated ACK Polling Command Data X STOP S S ACK ACK ACK ACK NACK S START A7 A6 A5 A4 A3 A2 A1 A0 ACK POLLING COMMAND A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A10 A9 A8 START If ACK, then Password Matches Data Y 7025 FM 11 7 X76F641 START Figure 7. Sequential Read Read Password 7 COMMAND Read Password 0 Wait tWC OR Repeated ACK Polling Command ACK ACK ACK ACK SDA S STOP ACK ACK ACK POLLING COMMAND A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A10 A9 A8 START If ACK, then Password Matches S ACK ACK ACK NACK S Data X Data 0 7025 FM 12 PASSWORDS After this time, it cannot be determined if the password has been loaded correctly, without trying the new password. To determine if the new password has been loaded correctly the data ACK polling command is issued immediately following the stop bit. If it returns an ACK, then the two passes of the new password entry do not match. If it returns a "no ACK" then the passwords match and a high voltage cycle is in progress. The high voltage cycle is complete when a subsequent data ACK command returns an "ACK". The sequence in Figure 8 shows how to change (program) the passwords. The programming of passwords is done twice prior to the nonvolatile write cycle in order to verify that the new password is consistent. After the eight bytes are entered in the second pass, a comparison takes place. A mismatch will cause the part to reset and enter into the standby mode. Data ACK polling can be used to determine if a password has been loaded correctly, however the data ACK command must be issued less than 2ms after the stop bit. There is no way to read any of the passwords. START Figure 8. Change Passwords Old Password 7 COMMAND Old Password 0 Wait tWC OR Repeated ACK Polling Command START If ACK, then Password Matches ACK POLLING COMMAND ACK ACK ACK ACK SDA S New Password 7 Two bytes of “0” Password 0 Data ACK Polling STOP New Password 7 New Password 0 ACK ACK NACK ACK ACK S ACK ACK ACK ACK ACK S If immediate ACK, then New Password error If immediate NACK, followed by ACK after ~5ms then New Password OK 7025 FM 13 8 X76F641 If ACK, then Device reset SDA S STOP Reset Password COMMAND Reset Password 0 Reset Password 7 Wait tWC OR Repeated ACK Polling Command START ACK POLLING COMMAND S NACK ACK ACK ACK ACK S ACK START Figure 9. Reset Password 7025 FM 14 Reset Password 7 Reset Device COMMAND SDA S If ACK, then Device reset STOP Reset Password 0 Wait tWC OR Repeated ACK Polling Command START ACK POLLING COMMAND S NACK ACK ACK ACK ACK S ACK START Figure 10. Reset Device 7025 FM 15 RESPONSE TO RESET (DEFAULT = 19 41 AA 55) is pulsed HIGH and the CLK is within the RST pulse (meet the tNOL spec.) in the middle of an ISO transaction, it will output the 32 bit sequence again (starting at bit 0). Otherwise, this aborts the ISO operation and the part returns to standby state. If the RST is pulsed HIGH and the CLK is outside the RST pulse (in the middle of an ISO transaction), this aborts the ISO operation and the part returns to standby state. The ISO Response to reset is controlled by the RST and CLK pins. When RST is pulsed high during a clock pulse, the device will output 32 bits of data, one bit per clock, and it resets to the standby state. This conforms to the ISO standard for “synchronous response to reset”. The part must not be in a write cycle for the response to reset to occur. If there is power interrupted during the Response to Reset, the response to reset will be aborted and the part will return to the standby state. A Response to Reset is not available during a nonvolatile write cycle. After initiating a nonvolatile write cycle the RST pin must not be pulsed until the nonvolatile write cycle is complete. If not, the ISO response will not be activated. If the RST 9 X76F641 Figure 11. Response to RESET (RST) RST SCK 1 0 0 1 1 0 0 0 SO LSB 1 0 0 0 0 0 1 0 MSB LSB Byte 0 0 1 0 1 0 1 0 1 MSB MSB LSB MSB LSB 2 1 1 0 1 0 1 0 1 0 3 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature under Bias ......................–65°C to +135°C Storage Temperature ...........................–65°C to +150°C Voltage on any Pin with Respect to VSS ......................................–1V to +7V D.C. Output Current..................................................5mA Lead Temperature (Soldering, 10 seconds)................................. 300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Commercial Extended Min. Max. Supply Voltage Limits 0°C +70°C X76F641 4.5V to 5.5V –20°C +85°C X76F641 – 2.0 2.0V to 3.6V 7025 FM T05 7025 FM T06 10 X76F641 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Limits Min. Max. Parameter Units Test Conditions ICC1 VCC Supply Current (Read) 1 mA fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz, SDA = Open RST = VSS ICC2(3) VCC Supply Current (Write) 3 mA fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz, SDA = Open RST = VSS ISB1(1) VCC Supply Current (Standby) 50 µA VIL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 400 KHz, fSDA = 400 KHz ISB2(1) VCC Supply Current (Standby) 1 µA VSDA = VSCC = VCC Other = GND or VCC–0.3V ILI Input Leakage Current 10 µA VIN = VSS to VCC ILO Output Leakage Current 10 µA VOUT = VSS to VCC VIL1(2) Input LOW Voltage VCC x 0.3 V VCC = 5.5V VIH1(2) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VCC = 5.5V VIL2(2) Input LOW Voltage VCC x 0.1 V VCC = 2.0V VIH2(2) Input HIGH Voltage VCC x 0.9 VCC + 0.5 V VCC = 2.0V VOL Output LOW Voltage V IOL = 3mA –0.5 –0.5 0.4 7002 FM T07 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol COUT(3) CIN(3) Test Max. Units Conditions Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (RST, SCL) 6 pF VIN = 0V 7002 FM T08 NOTES: (1) Must perform a stop command after a read command prior to measurement (2) VIL min. and VIH max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS Input Pulse Levels 5V 3V 1533Ω OUTPUT Input Rise and Fall Times 1.3KΩ Input and Output Timing Level Output Load OUTPUT 100pF 100pF VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 100pF 7002 FM T09 7025 FM 17 11 X76F641 AC CHARACTERISTICS AC Specifications (Over the recommended operating conditions) Symbol Parameter Min Typ(1) Max Units 400 KHz fSCL SCL Clock Frequency 0 tIN(1) Pulse width of spikes which must be suppressed by the input filter 50 100 tAA SCL LOW to SDA Data Out Valid 0.1 0.3 tBUF Time the bus must be free before a new transmit can start 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 tR SDA and SCL Rise Time 20 + 0.1 x Cb(2) 300 ns tF SDA and SCL Fall Time 20 + 0.1 x Cb(2) 300 ns fSCL_RST SCL Clock Frequency during Response to Reset 400 kHz tSR Device Select to RST active 200 ns tNOL RST to SCL Non-Overlap 500 ns tRST RST High Time 2.25 µs tSU:RST Response to Reset Setup Time 1.25 µs tLOW_RST Clock LOW during Response to Reset 1.25 µs tHIGH_RST Clock HIGH during Response to Reset 1.25 µs tRDV RST LOW to SDA Valid During Response to Reset 0 500 ns tCDV CLK LOW to SDA Valid During Response to Reset 0 500 ns tDHZ Device Deselect to SDA high impedance 0 500 ns ns 0.9 300 µs ns Notes: 1. Typical values are for TA = 25˚C and VCC = 5.0V Notes: 2. Cb = Total Capacitance of one bus line in pf. 7025 FM T14 12 X76F641 RESET AC SPECIFICATIONS Power Up Timing tPUR (1) tPUW(1) Typ(2) Max. Units Time from Power Up to Read 1 mS Time from Power Up to Write 5 mS Symbol Parameter Min. 7025 FM T11 Notes: 1. Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 2. Typical values are for TA = 25˚C and VCC = 5.0V Nonvolatile Write Cycle Timing Symbol tWC(1) Parameter Min. Typ.(1) Max. Units 5 10 mS Write Cycle Time 7025 FM T12 Notes: 1. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. TIMING DIAGRAMS Bus Timing tF tR SCL tHIGH tLOW tSU:DAT tSU:STA tHD:DAT tHD:STA SDA IN tSU:STO tAA tDH tBUF SDA OUT 7025 FM 18 Write Cycle Timing SCL SDA 8th bit of last byte ACK tWC Stop Condition Start Condition 7025 FM 19 13 X76F641 RST Timing Diagram – Response to a Synchronous Reset RST tRST tNOL tHIGH_RST tNOL 1st clk pulse CLK 2nd clk pulse tSU:RST tRDV I/O 3rd clk pulse tLOW_RST tCDV DATA BIT (2) DATA BIT (1) RST CLK I/O DATA BIT (N+1) DATA BIT (N) (N+2) 7025 FM 21 Pull Up Resistance in KΩ GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS 100 V CCMAX R MIN = -------------------------- = 1.8 K Ω I OLMIN 80 60 RMAX 40 20 tR R MAX = -----------------C BUS RMIN 20 40 60 80 100 Bus capacitance in pF tR = maximum allowable SDA rise time 7025 FM 22 14 X76F641 8-LEAD PLASTIC, 0.200” WIDE SMALL OUTLINE GULLWING PACKAGE TYP “A” (EIAJ SOIC) 0.020 (.508) 0.012 (.305) .213 (5.41) .205 (5.21) .330 (8.38) .300 (7.62) PIN 1 ID .050 (1.27) BSC .212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78) .013 (.330) .004 (.102) 0 8 REF .010 (.254) .007 (.178) .035 (.889) .020 (.508) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 7025 FM 24 15 X76F641 8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X 8 CONTACT MODULE 6 CONTACT MODULE 11.4 8 1. 59 10.62 1.31 0.2 1.215 12.6 1.62 1.31 0.2 1 90° 1.62 0.15 1.3 2.54 2.54 35mm TAPE 35mm TAPE 1.422 35 23.02 14.25 4.75 1.422 REJECT PUNCH POSITION 8.82 NOTE: ALL MEASUREMENTS IN MILLIMETERS 16 1.3 X76F641 ORDERING INFORMATION X76F641 X X –X Device VCC Limits Blank = 5V ±10% 2.0 = 2.0V to 3.6V Temperature Range Blank = Commercial = 0°C to +70°C E = Extended = –20°C to +85°C Package A = 8-Lead SOIC (EIAJ) H = Die in Waffle Packs W = Die in Wafer Form X = Smart Card Module LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 17