X76F100 1K 128 x 8 Bit Secure SerialFlash FEATURES DESCRIPTION • 64-bit password security • One array (112-bytes) two passwords (16-bytes) —Read password —Write password • Programmable passwords • Retry counter register —Allows 8 tries before clearing of the array • 32-bit response to reset (rst input) • 8-byte sector Write Mode • 1MHz clock rate • 2-wire serial interface • Low power CMOS —3.0 to 5.5V operation —Standby current less than 1µA —Active current less than 3 mA • High reliability endurance: —100,000 write cycles • Data retention: 100 years • Available in: —8-lead PDIP, SOIC, MSOP, and smart car module The X76F100 is a Password Access Security Supervisor, containing one 896-bit Secure SerialFlash array. Access to the memory array can be controlled by two 64-bit passwords. These passwords protect read and write operations of the memory array. The X76F100 features a serial interface and software protocol allowing operation on a popular two wire bus. The bus signals are a clock Input (SCL) and a bidirectional data input and output (SDA). Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X76F100 also features a synchronous response to reset providing an automatic output of a hard-wired 32-bit data stream conforming to the industry standard for memory cards. The X76F100 utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. BLOCK DIAGRAM CS Chip Enable Data Transfer SCL SDA Array Access Enable Interface Logic Password Array and Password Verification Logic 8K Byte SerialFlash Array Array 0 (Password Protected) 32 Byte SerialFlash Array Array 1 (Password Protected) RST Reset Response Register REV 1.0 6/22/00 www.xicor.com Retry Counter Characteristics subject to change without notice. 1 of 16 X76F100 PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is an open drain serial data input/output pin. During a read cycle, data is shifted out on this pin. During a write cycle, data is shifted in on this pin. In all other cases, this pin is in a high impedance state. Chip Select (CS) When CS is high, the X76F100 is deselected and the SDA pin is at high impedance and unless an internal write operation is underway, the X76F100 will be in standby mode. CS low enables the X76F100, placing it in the active mode. To ensure the correct communication, RST must remain LOW under all conditions except when running a “Response to Reset sequence”. Data is transferred in 8-bit segments, with each transfer being followed by an ACK, generated by the receiving device. If the X76F100 is in a nonvolatile write cycle a “no ACK” (SDA=High) response will be issued in response to loading of the command byte. If a stop is issued prior to the nonvolatile write cycle the write operation will be terminated and the part will reset and enter into a standby mode. The basic sequence is illustrated in Figure 1. PIN NAMES Symbol Description CS Reset (RST) RST is a device reset pin. When RST is pulsed high while CS is low the X76F100 will output 32 bits of fixed data which conforms to the standard for “synchronous response to reset”. CS must remain LOW and the part must not be in a write cycle for the response to reset to occur. See Figure 7. If at any time during the response to reset CS goes HIGH, the response to reset will be aborted and the part will return to the standby state. The response to reset is “mask programmable” only! SDA Serial Data Input/Output SCL Serial Clock Input RST Reset Input VCC Supply Voltage VSS Ground NC No Connect PIN CONFIGURATION Smart Card PDIP DEVICE OPERATION The X76F100 memory array consists of fourteen 8-byte sectors. Read or write access to the array always begins at the first address of the sector. Read operations then can continue indefinitely. Write operations must total 8-bytes. There are two primary modes of operation for the X76F100; Protected READ and protected WRITE. Protected operations must be performed with one of two 8byte passwords. The basic method of communication for the device is established by first enabling the device (CS LOW), generating a start condition, then transmitting a command, followed by the correct password. All parts will be shipped from the factory with all passwords equal to ‘0’. The user must perform ACK Polling to determine the validity of the password, before starting a data transfer (see Acknowledge Polling.) Only after the correct password is accepted and a ACK polling has been performed, can the data transfer occur. REV 1.0 6/22/00 Chip Select Input VCC 1 8 RST NC 2 7 SCL NC 3 6 SDA VSS 4 5 CS SOIC VSS 1 8 VCC CS 2 7 RST VCC GND SDA 3 6 SCL RST CS NC 4 5 NC SCL SDA NC NC MSOP VSS 1 8 NC 2 7 CS 3 6 SDA 4 5 www.xicor.com VCC NC RST SCL Characteristics subject to change without notice. 2 of 16 X76F100 After each transaction is completed, the X76F100 will reset and enter into a standby mode. This will also be the response if an unsuccessful attempt is made to access a protected array. Figure 1. X76F100 Device Operation Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X76F100 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Load Command/Address Byte Load 8-Byte Password A start may be issued to terminate the input of a control byte or the input data to be written. This will reset the device and leave it ready to begin a new read or write command. Because of the push/pull output, a start cannot be generated while the part is outputting data. Starts are inhibited while a write is in progress. Verify Password Acceptance by Use of Ack Polling Read/Write Data Bytes Retry Counter The X76F100 contains a retry counter. The retry counter allows 8 accesses with an invalid password before any action is taken. The counter will increment with any combination of incorrect passwords. If the retry counter overflows, the memory area and both of the passwords are cleared to “0”. If a correct password is received prior to retry counter overflow, the retry counter is reset and access is granted. Device Protocol The X76F100 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as a receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X76F100 will be considered a slave in all applications. REV 1.0 6/22/00 Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figure 2 and Figure 3. Stop Condition All communications must be terminated by a stop condition. The stop condition is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to reset the device during a command or data input sequence and will leave the device in the standby power mode. As with starts, stops are inhibited when outputting data and while a write is in progress. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. The X76F100 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write condition have been selected, the X76F100 will respond with an acknowledge after the receipt of each subsequent eight-bit word. www.xicor.com Characteristics subject to change without notice. 3 of 16 X76F100 Figure 2. Data Validity SCL SDA Data Stable Data Change Figure 3. Definition of Start and Stop Conditions SCL SDA Start Condition Stop Condition Table 1. X76F100 Instruction Set Command after Start Command Description Password Used 1 0 0 S3 S2 S1 S00 Sector Write Write 1 0 0 S3 S2 S1 S0 1 Sector Read Read 1 1 1 1 1 1 0 0 Change Write Password Write 1 1 1 1 1 1 1 0 Change Read Password Write 0 1 0 1 0 1 0 1 Password ACK Command None Illegal command codes will be disregarded. The part will respond with a “no-ACK” to the illegal byte and then return to the standby mode. All write/read operations require a password. PROGRAM OPERATIONS Sector Write The sector write mode requires issuing the 8-bit write command followed by the password and then the data bytes transferred as illustrated in Figure 4. The write command byte contains the address of the sector to be written. Data is written starting at the first address of a sector and eight bytes must be transferred. After the last byte to be transferred is acknowledged a stop condition is issued which starts the nonvolatile write cycle. If more or less than 8-bytes are transferred, the data in the sector remains unchanged. REV 1.0 6/22/00 ACK Polling Once a stop condition is issued to indicate the end of the host’s write sequence, the X76F100 initiates the internal nonvolatile write cycle. In order to take advantage of the typical 5ms write cycle, ACK polling can begin immediately. This involves issuing the start condition followed by the new command code of 8-bits (1st byte of the protocol.) If the X76F100 is still busy with the nonvolatile write operation, it will issue a “no-ACK” in response. If the nonvolatile write operation has completed, an “ACK” will be returned and the host can then proceed with the rest of the protocol. www.xicor.com Characteristics subject to change without notice. 4 of 16 X76F100 Data ACK Polling Sequence Password ACK Polling Sequence Write Sequence Completed Enter ACK Polling Password Load Completed Enter ACK Polling Issue START Issue START Issue New Command Code Issue Password ACK Command ACK returned? NO ACK returned? YES YES PROCEED PROCEED After the password sequence, there is always a nonvolatile write cycle. This is done to discourage random guesses of the password if the device is being tampered with. In order to continue the transaction, the X76F100 requires the master to perform a password ACK polling sequence with the specific command code of 55h. As with regular Acknowledge polling the user can either time out for 10ms, and then issue the ACK polling once, or continuously loop as described in the flow. If the password that was inserted was correct, then an “ACK” will be returned once the nonvolatile cycle in response to the password ACK polling sequence is over. If the password that was inserted was incorrect, then a “no ACK” will be returned even if the nonvolatile cycle is over. Therefore, the user cannot be certain that the password is incorrect until the 10ms write cycle time has elapsed. REV 1.0 6/22/00 NO READ OPERATIONS Read operations are initiated in the same manner as write operations but with a different command code. Sector Read With sector read, a sector address is supplied with the read command. Once the password has been acknowledged data may be read from the sector. An acknowledge must follow each 8-bit data transfer. A read operation always begins at the first byte in the sector, but may stop at any time. Random accesses to the array are not possible. Continuous reading from the array will return data from successive sectors. After reading the last sector in the array, the address is automatically set to the first sector in the array and data can continue to be read out. After the last bit has been read, a stop condition is generated without sending a preceding acknowledge. www.xicor.com Characteristics subject to change without notice. 5 of 16 X76F100 START Figure 4. Sector Write Sequence (Password Required) Host Commands Write Password 7 Write Command Write Password 0 Wait tWC OR Password ACK Command ACK ACK ACK ACK SDA S X76F100 Response STOP Password ACK Command ACK Host Commands ACK START If ACK, Then Password Matches P Wait tWC Data ACK Polling ACK ACK ACK ACK X76F100 Responce No-ACK S Figure 5. Acknowledge Polling SCL 8th CLK of 8th Pwd. Byte SDA ‘ACK’ CLK 8th CLK ‘ACK’ 8th Bit ‘ACK’ CLK Start Condition ACK or no ACK START Figure 6. Sector Read Sequence (Password Required) Host Commands Read Password 0 Wait tWC OR Password ACK Command ACK ACK ACK SDA S ACK X76F100 Response Read Password 7 Read Command STOP Password ACK Command ACK Host Commands ACK START If ACK, Then Password Matches P REV 1.0 6/22/00 ACK X76F100 Response No-ACK S Data 0 www.xicor.com Data n Characteristics subject to change without notice. 6 of 16 X76F100 PASSWORDS Passwords are changed by sending the “change read password” or “change write password” commands in a normal sector write operation. A full eight bytes containing the new password must be sent, following successful transmission of the current write password and a valid password ACK response. The user can use a repeated ACK Polling command to check that a new password has been written correctly. An ACK indicates that the new password is valid. There is no way to read any of the passwords. Response to Reset (Default = 19 00 AA 55) The ISO Response to reset is controlled by the RST, CS and CLK pins. When RST is pulsed high, while CS is low, the device will output 32-bits of data, one bit per clock. This conforms to the ISO standard for “synchronous response to reset”. CS must remain LOW and the part must not be in a write cycle for the response to reset to occur. After initiating a nonvolatile write cycle the RST pin must not be pulsed until the nonvolatile write cycle is complete. If not, the ISO response will not be activated. Also, any attempt to pulse the RST pin in the middle of an ISO transaction will stop the transaction with the SDA pin in high impedance. The user will have to issue a stop condition and start the transaction again. If at any time during the Response to Reset CS goes HIGH, the response to reset will be aborted and the part will return to the standby state. A Response to Reset is not available during a nonvolatile write cycle. Continued clocks after the 32-bits, will output the 32-bit sequence again, starting at byte 0. Figure 7. Response to RESET(RST) CS RST SCK SO 1 0 0 1 1 0 0 0 LSB Byte REV 1.0 6/22/00 0 0 0 0 0 0 0 0 MSB LSB 0 0 1 0 1 0 1 0 1 www.xicor.com MSB MSB LSB MSB LSB 1 1 0 1 0 1 0 1 0 2 3 Characteristics subject to change without notice. 7 of 16 X76F100 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias ....................–65°C to +135°C Storage temperature ........................–65°C to +150°C Voltage on any pin with respect to VSS ......................................... –1V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds).........300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits Commercial 0°C +70°C X76F100 4.5V to 5.5V Industrial –40°C +85°C X76F100-3 3.0V to 5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Unit Test Conditions ICC1 VCC Supply Current (Read) 1 mA fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 kHz, SDA = Open RST = CS = VSS ICC2(3) VCC Supply Current (Write) 3 mA fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 kHz, SDA = Open RST = CS = VSS ISB1(1) VCC Supply Current (Standby) 1 µA VIL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 400 kHz, fSDA = 400 kHz ISB2(1) VCC Supply Current (Standby) 1 µA VSDA = VSCC = VCC Other = GND or VCC–0.3V ILI Input Leakage Current 10 µA VIN = VSS to VCC ILO Output Leakage Current 10 µA VOUT = VSS to VCC VCC x 0.3 V VCC x 0.7 VCC + 0.5 V (2) Input LOW Voltage (2) VIH Input HIGH Voltage VOL Output LOW Voltage VIL –0.5 0.4 V IOL = 3mA CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol (3) COUT (3) CIN Test Max. Unit Conditions Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (RST, SCL, CS) 6 pF VIN = 0V Notes: (1) Must perform a stop command after a read command prior to measurement. (2) VIL min. and VIH max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested. REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 8 of 16 X76F100 AC CHARACTERISTICS (TA = -40°C to +85°C, VCC = +3.0V to +5.5V, unless otherwise specified.) Symbol fSCL Parameter SCL Clock Frequency (3) Min. Max. Unit 0 1 MHz 0.9 µs tAA SCL LOW to SDA Data Out Valid 0.1 tBUF Time the Bus Must Be Free Before a New Transmission Can Start 1.2 µs Start Condition Hold Time 0.6 µs tLOW Clock LOW Period 1.2 µs tHIGH Clock HIGH Period 0.6 µs tHD:STA tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 0.6 µs tHD:DAT Data In Hold Time 10 ns tSU:DAT Data In Setup Time 100 SDA and SCL Rise Time tR tSU:STO 300 ns (2) 300 ns 20+0.1XCb SDA and SCL Fall Time tF ns (2) 20+0.1XCb Stop Condition Setup Time 0.6 µs 0 µs 500 ns tDH Data Out Hold Time tNOL RST to SCL Non-Overlap tRDV RST LOW to SDA Valid During Response to Reset 0 450 ns tCDV CLK LOW to SDA Valid During Response to Reset 0 450 ns Device Deselect to SDA high impedance 0 450 ns tSR Device Select to RST active 0 ns tRST RST High Time 1.5 µs tSU:RST RST Setup Time 500 ns tSU:CS CS Setup Time 200 ns tSU:CS CS Hold Time 100 ns tDHZ(1) (1) Notes: (1) These Specs are not defined in the ISO 7816-3 Standard, since CS is not defined. (2) Cb = total capacitance of one bus line in pF (3) tAA = 1.1µs Max below VCC = 3.0V. RESET AC SPECIFICATIONS Power Up Timing Symbol (1) (1) tPUR tPUW Parameter Min. Typ.(2) Max. Unit Time from Power Up to Read 1 ms Time from Power Up to Write 5 ms Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated.These parameters are periodically sampled and not 100% tested. (2) Typical values are for TA = 25°C and VCC = 5.0V REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 9 of 16 X76F100 Nonvolatile Write Cycle Timing Symbol Parameter (1) tWC Note: Min. Typ.(1) Max. Unit 5 10 ms Write Cycle Time (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Bus Timing tF tHIGH tHD:STA tHD:DAT tLOW tR SCL tSU:STA tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT Write Cycle Timing SCL 8th Bit of Last Byte SDA ACK tWC Stop Condition Start Condition CS Timing Diagram (Selecting/Deselecting the Part) SCL tHD:CS tSU:CS CS from Master REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 10 of 16 X76F100 RST Timing Diagram—Response to a Synchronous Reset tSR CS RST tRST tNOL CLK tHIGH_RST tNOL 1st CLK Pulse 2nd CLK Pulse tSU:RST tRDV tCDV Data Bit (2) Data Bit (1) I/O 3rd CLK Pulse tLOW_RST CS RST CLK tDHZ (N+2) Data Bit (N+1) Data Bit (N) I/O Pull Up Resistance in KΩ GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS 100 V CCMAX R MIN = -------------------------- = 1.8 K Ω I OLMIN 80 60 RMAX 40 20 tR R MAX = -----------------C BUS RMIN 20 40 60 80 100 tR = maximum allowable SDA rise time Bus Capacitance in pF REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 11 of 16 X76F100 PACKAGING INFORMATION 8-Lead Miniature Small Outline Gull Wing Package Type M 0.118 ± 0.002 (3.00 ± 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) Typ. R 0.014 (0.36) 0.118 ± 0.002 (3.00 ± 0.05) 0.030 (0.76) 0.0216 (0.55) 0.036 (0.91) 0.032 (0.81) 0.040 ± 0.002 (1.02 ± 0.05) 7° Typ. 0.008 (0.20) 0.004 (0.10) 0.0256" Typical 0.007 (0.18) 0.005 (0.13) 0.025" Typical 0.150 (3.81) Ref. 0.193 (4.90) Ref. 0.220" FOOTPRINT 0.020" Typical 8 Places NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS) REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 12 of 16 X76F100 PACKAGING INFORMATION 8-Lead Plastic Dual In-Line Package Type P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. Half Shoulder Width On All End Pins Optional 0.145 (3.68) 0.128 (3.25) Seating Plane 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) .073 (1.84) Max. 0.060 (1.52) 0.020 (0.51) 0.020 (0.51) 0.016 (0.41) 0.325 (8.25) 0.300 (7.62) 0° 15° Typ. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 13 of 16 X76F100 PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) 0.050"Typical 0.050" Typical 0° - 8° 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) 0.030" Typical 8 Places FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 14 of 16 X76F100 PACKAGING INFORMATION 8 Pad Chip on Board Smart Card Module Type X 0.465 ± 0.002 (11.81 ± 0.05) 0.285 (7.24) Max. See Note 7 Sht. 2 0.088 (2.24) Min Epoxy Free Area (Typ.) R. 0.078 (2.00) 0.069 (1.75) Min Epoxy Free Area (Typ.) 0.270 (6.86) Max. See Note 7 Sht. 2 0.420 ± 0.002 (10.67 ± 0.05) A A 0.008 ± 0.001 (0.20 ± 0.03) 0.210 ± 0.002 (5.33 ± 0.05) 0.233 ± 0.002 (5.92 ± 0.05) Die SECTION A-A 0.0235 (0.60) Max. 0.015 (0.38) Max. 0.008 (0.20) Max. Glob Size FR4 Tape See Detail Sheet 3 Copper, Nickel Plated, Gold Flash 0.146 ± 0.002 0.174 ± 0.002 (4.42 ± 0.05) R. 0.013 (0.33) (8x) (3.71 ± 0.05) VCC VSS RST CS SCL SDA NC NC 0.105 ± 0.002 (2.67 ± 0.05) Typ. (8x) 0.105 ± 0.002 (8x) (2.67 ± 0.05) NOTE: ALL DIMENSIONS IN INCHES AND (MILLIMETERS) REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 15 of 16 X76F100 Ordering Information X76F100 X Device X –X VCC Limits Blank = 5V ±10% 3.0 = 3.0V to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial= –40°C to +85°C Package S8 = 8-Lead SOIC M8 = 8-Lead MSOP P = 8-Lead PDIP H = Die in Waffle Packs W = Die in Wafer Form X = Smart Card Module Part Mark Convention 8-Lead MSOP 8-Lead SOIC/PDIP EYWW XXX X76F100 X XX AAQ = 3.0 to 5.5V, 0 to +70°C AAR = 3.0 to 5.5V, -40 to +85°C AAS = 4.5 to 5.5V, 0 to +70°C AAT = 4.5 to 5.5V, -40 to +85°C Blank = 8-Lead SOIC D = 3.0 to 5.5V, 0 to +70°C E = 3.0 to 5.5V, -40 to +85°C Blank = 4.5 to 5.5V, 0 to +70°C I = 4.5 to 5.5V, -40 to +85°C LIMITED WARRANTY ©Xicor, Inc. 2000 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 16 of 16 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.