APPLICATION NOTES AND DEVELOPMENT SYSTEM
A V A I L A B L E
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
Single Supply / Low Power / 1024-tap / SPI bus
X9111
Preliminary Information
Single Digitally-Controlled (XDCP™) Potentiometer
FEATURES
DESCRIPTION
• 1024 Resistor Taps – 10-Bit Resolution
• SPI Serial Interface for write, read, and transfer
operations of the potentiometer
• Wiper Resistance, 40Ω Typical @ 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power Up.
• Standby Current < 3µA Max
• VCC: 2.7V to 5.5V Operation
• 100KΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100, 000 Data Changes Per Bit Per
Register
• 14-Lead TSSOP, 15-Lead CSP (Chip Scale
Packaging)
• Low Power CMOS
• Single Supply version of the X9110
The X9111 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 1023 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. The potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and
four non-volatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the
contents of the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
VCC
SPI
Bus
Interface
Address
Data
Status
Bus
Interface &
Control
RH
Write
Read
Transfer
Control
VSS
REV 1.1.15 5/9/03
Power On Recall
100KΩ
1024-taps
POT
Wiper Counter
Register (WCR)
Data Registers
(DR0-DR3)
NC
www.xicor.com
Wiper
RW
RL
Characteristics subject to change without notice.
1 of 21
X9111 – Preliminary Information
DETAILED FUNCTIONAL DIAGRAM
VCC
Power On
Recall
HOLD
CS
SCK
SO
SI
A0
DR0 DR1
Interface
and
Control
Circuitry
Data
DR2 DR3
Wiper
Counter
Register
(WCR)
RH
100KΩ
1024-taps
RL
Control
A1
RW
WP
VSS
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
REV 1.1.15 5/9/03
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Characteristics subject to change without notice.
2 of 21
X9111 – Preliminary Information
PIN CONFIGURATION
TSSOP
SO
A0
NC
CS
SCK
SI
VSS
14
1
13
2
3
12
4 X9111 11
5
10
6
9
8
7
CSP
2
1
SO
VCC
RL
A0
NC
RH
CS
NC
RW
SCK
WP
HOLD
SI
VSS
A1
3
X9111
VCC
RL
RH
RW
A
B
HOLD
A1
WP
C
D
E
PIN ASSIGNMENTS
Pin
(TSSOP)
Pin
(CSP)
Symbol
1
A3
SO
Serial Data Output
2
B3
A0
Device Address
3
B2, C2
NC
No Connect
4
C3
CS
Chip Select
5
D3
SCK
6
E3
SI
Serial Data Input
7
E2
VSS
System Ground
8
D2
WP
Hardware Write Protect
9
E1
A1
Device Address
10
D1
HOLD
Device Select. Pause the Serial Bus
11
C1
RW
Wiper Terminal of the Potentiometer
12
B1
RH
High Terminal of the Potentiometer
13
A1
RL
Low Terminal of the Potentiometer
14
A2
VCC
REV 1.1.15 5/9/03
Function
Serial Clock
System Supply Voltage
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Characteristics subject to change without notice.
3 of 21
X9111 – Preliminary Information
PIN DESCRIPTIONS
Potentiometer Pins
Bus Interface Pins
RH, RL
SERIAL OUTPUT (SO)
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
RW
SERIAL INPUT (SI)
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
X9111.
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS)
The VCC pin is the system supply voltage. The VSS pin
is the system ground.
Other Pins
NO CONNECT (NC)
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH at
all times.
DEVICE ADDRESS (A0, A1)
The address inputs are used to set the 8-bit slave
address. A match in the slave address serial data
stream must be made with the address input (A1–A0)
in order to initiate communication with the X9111.
CHIP SELECT (CS)
When CS is HIGH, the X9111 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9111, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
REV 1.1.15 5/9/03
Pin should be left open. This pin is used for Xicor
manufacturing and test purposes.
PRINCIPLES OF OPERATION
DEVICE DESCRIPTION
Serial Interface
The X9111 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked-in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9111 is comprised of a resistor array (see Figure
1). The array contains the equivalent of 1023 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within the individual array only one switch
may be turned on at a time.
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Characteristics subject to change without notice.
4 of 21
X9111 – Preliminary Information
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
RH
Serial
Bus
Input
From Interface
Circuitry
Register 1
(DR1)
Register 0
(DR0)
10
Register 2
(DR2)
10
Parallel
Bus
Input
Register 3
(DR3)
Wiper
Counter
Register
(WCR)
C
O
U
N
T
E
R
D
E
C
O
D
E
If WCR = 000[HEX] then RW = RL
If WCR = 3FF[HEX] then RW = RH
RL
R
W
These switches are controlled by a Wiper Counter
Register (WCR). The 10-bits of the WCR (WCR[9:0])
are decoded to select, and enable, one of 1024
switches.
Wiper Counter Register (WCR)
The X9111 contains a Wiper Counter Register (see
Table 1) for the XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of 1024 switches
along its resistor array. The contents of the WCR can
be altered in one of three ways: (1) it may be written
directly by the host via the write Wiper Counter
Register instruction (serial load); (2) it may be written
indirectly by transferring the contents of one of four
associated Data Registers via the XFR Data Register;
(3) it is loaded with the contents of its Data Register
zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9111 is powereddown. Although the register is automatically loaded
with the value in R0 upon power-up, this may be
different from the value present at power-down. Powerup guidelines are recommended to ensure proper
loadings of the R0 value into the WCR.
REV 1.1.15 5/9/03
Data Registers (DR3 to DR0)
The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the Wiper Counter Register.
All operations changing data in one of the Data
Registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
A DR[9:0] is used to store one of the 1024 wiper
position (0 ~1023). Table 2.
Status Register (SR)
This 1-bit status register is used to store the system
status (see Table 3).
WIP: Write In Progress status bit, read only.
– When WIP=1, indicates that high-voltage write cycle
is in progress.
– When WIP=0, indicates that no high-voltage write
cycle is in progress.
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Characteristics subject to change without notice.
5 of 21
X9111 – Preliminary Information
Table 1. Wiper Latch, WL (10-bit), WCR9–WCR0: Used to store the current wiper position (Volatile, V)
WCR9
WCR8
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
V
V
V
(MSB)
(LSB)
Table 2. Data Register, DR (10-bit), Bit 9–Bit 0: Used to store wiper positions or data (Non-Volatile, NV)
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
Table 3. Status Register, SR (1-bit)
WIP
(LSB)
DEVICE INSTRUCTIONS
Identification Byte (ID and A)
The first byte sent to the X9111 from the host, following
a CS going HIGH to LOW, is called the Identification
Byte. The most significant four bits of the slave address
are a device type identifier. The ID[3:0] bits is the
device ID for the X9111; this is fixed as 0101[B] (refer
to Table 4).
The A1–A0 bits in the ID byte are the internal slave
address. The physical device address is defined by the
state of the A1–A0 input pins. The slave address is
externally specified by the user. The X9111 compares
the serial data stream with the address input state; a
successful compare of the address bits is required for
the X9111 to successfully continue the command
sequence. Only the device whose slave address
matches the incoming device address sent by the
master executes the instruction. The A1–A0 inputs can
be actively driven by CMOS input signals or tied to VCC
or VSS. The R/W bit is used to set the device to either
read or write mode.
Instruction Byte and Register Selection
The next byte sent to the X9111 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[2:0]). The RB and RA bits point to one of the
four registers. The format is shown in Table 5.
Table 4. Identification Byte Format
Internal Slave
Address
Device Type
Identifier
ID3
ID2
ID1
ID0
0
1
0
1
0
A1
Read or
Write Bit
A0
(MSB)
R/W
(LSB)
Table 5. Instruction Byte Format
Register
Selection
Instruction
Opcode
I2
(MSB)
REV 1.1.15 5/9/03
I1
I0
0
RB
RB
0
0
1
1
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RA
RA
0
1
0
1
Register
DR0
DR1
DR2
DR3
0
0
(LSB)
Characteristics subject to change without notice.
6 of 21
X9111 – Preliminary Information
Five of the seven instructions are four bytes in length.
These instructions are:
– Read Wiper Counter Register – read the current
wiper position of the selected pot,
– Write Wiper Counter Register – change current
wiper position of the selected pot,
– Read Data Register – read the contents of the
selected data register;
– Write Data Register – write a new value to the
selected data register.
– Read Status – This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The basic sequence of the four byte instructions is
illustrated in Figure 3. These four-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between the potentiometer and one of its associated
registers. The Read Status Register instruction is the
only unique format (see Figure 4).
Two instructions require a two-byte sequence to
complete (see Figure 2). These instructions transfer
data between the host and the X9111; either between
the host and one of the Data Registers or directly
between the host and the Wiper Counter Register.
These instructions are:
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
See Instruction format for more details.
Write in Process (WIP bit)
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command (see
Figure 4).
Power Up and Down Requirements
There are no restrictions on the power-up condition of
VCC and the voltages applied to the potentiometer pins
provided that the VCC is always more positive than or
equal to the voltages at RH, RL, and RW, i.e., VCC ≥
RH, RL, RW. There are no restrictions on the powerdown condition. However, the datasheet parameters
for the DCP do not apply until 1millisecond after VCC
reaches its final value.
Figure 2. Two-Byte Instruction Sequence
CS
SCK
SI
1
0
ID3 ID2 ID1 ID0
0
0
1
0
Device ID
REV 1.1.15 5/9/03
0
A1 A0 R/W I2
Internal
Address
I1
I0
RB RA
Instruction
Opcode
Register
Address
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0
0
0
0
Characteristics subject to change without notice.
7 of 21
X9111 – Preliminary Information
Figure 3. Four-Byte Instruction Sequence (Write or Read for WCR or Data Registers)
CS
SCK
SI
0
1 0 1
0 X X 0
0 X X X X X X
A1 A0 R/W I2 I1 I0 0 RB RA 0 0
ID3 ID2 ID1 ID0 0
Device ID
0
0
Internal
Address
Instruction Register
Opcode Address
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
Wiper
Position
Figure 4. Four-Byte Instruction Sequence (Read Status Registers)
CS
SCK
SI
0
1 0 1
0
1
ID3 ID2 ID1 ID0 0 A1 A0 R/W I2 I1
Device ID
REV 1.1.15 5/9/03
Internal
Address
I0
0 X X 0
0 X X X X X X X X
0 RB RA 0
0
Instruction Register
Address
Opcode
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0 0 0 0 0 0 0
WIP
Status
Bit
Characteristics subject to change without notice.
8 of 21
X9111 – Preliminary Information
Table 6. Instruction Set
Instruction Set
Instruction
R/W
I3
I2
I1
0
RB
RA
0
0
Read Wiper Counter
Register
1
1
0
0
0
0
0
0
0
Read the contents of the Wiper
Counter Register
Write Wiper Counter
Register
0
1
0
1
0
0
0
0
0
Write new value to the Wiper
Counter Register
Read Data Register
1
1
0
1
0
1/0
1/0
0
0
Read the contents of the Data
Register pointed to RB-RA
Write Data Register
0
1
1
0
0
1/0
1/0
0
0
Write new value to the Data
Register pointed to RB-RA
XFR Data Register to
Wiper Counter Register
1
1
1
0
0
1/0
1/0
0
0
Transfer the contents of the Data
Register pointed to by RB-RA to
the Wiper Counter Register
XFR Wiper Counter
Register to Data Register
0
1
1
1
0
1/0
1/0
0
0
Transfer the contents of the Wiper
Counter Register to the Data
Register pointed to by RB-RA
Read Status (WIP bit)
1
0
1
0
0
0
0
0
1
Read the status of the internal write
cycle, by checking the WIP bit
(read status register).
Note:
Operation
(1) 1/0 = data is one or zero
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
CS
Falling
Edge 0
1
0
1
Device
Addresses
0 A1 A0
Instruction
Opcode
R/ W = 1
Device Type
Identifier
1
0
0
Register
Addresses
0
0
0
0
0
Wiper Position
(Sent by X9111 on SO)
W
X X X X X X C
R
9
Wiper Position
(sent by X9111 on SO)
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
CS
W Rising
C Edge
R
0
Write Wiper Counter Register (WCR)
CS
Falling
Edge 0
1
0
1
Device
Addresses
0 A1 A0
Instruction
Opcode
R/ W = 0
Device Type
Identifier
1
0
1
Register
Addresses
0
0
0
0
0
Wiper Position
(Sent by Master on SI)
W
X X X X X X C
R
9
Wiper Position
(Sent by Master on SI)
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
CS
W Rising
C Edge
R
0
Read Data Register (DR)
CS
Falling
Edge 0
1
0
REV 1.1.15 5/9/03
1
Device
Addresses
0 A1 A0
Instruction
Opcode
R/ W = 1
Device Type
Identifier
1
0
1
Register
Addresses
0 RB RA 0
Wiper Position
(Sent by X9111 on SO)
0
W
X X X X X X C
R
9
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Wiper Position
(sent by X9111 on SO)
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
CS
W Rising
C Edge
R
0
Characteristics subject to change without notice.
9 of 21
X9111 – Preliminary Information
CS
Falling
Edge 0
1
0
1
Device
Addresses
0 A1 A0
Instruction
Opcode
R/ W = 0
Device Type
Identifier
Register
Addresses
1 1 0 0 RB RA 0
Wiper Position or Data
(Sent by Master on SI)
W
0 X X X X X X C
R
9
W
C
R
8
Wiper Position or Data
(Sent by Master on SI)
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
CS
W Rising
C Edge
R
0
HIGH-VOLTAGE
WRITE CYCLE
Write Data Register (DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS
Falling
Edge 0
1
0
1
Device
Addresses
Instruction
Opcode
R/ W = 1
Device Type
Identifier
0 A1 A0
1
1
0
Register
Addresses
0 RB RA 0
0
CS
Rising
Edge
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge 0
1
0
1
Device
Addresses
0 A1 A0
R/ W = 0
Device Type
Identifier
Instruction
Opcode
1
1
1
0
Register
Addresses
RB
RA
0
0
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
Read Status Register (SR)
CS
Falling
Edge 0
1
0
1
Device
Addresses
0 A1 A0
R/ W = 1
Device Type
Identifier
Instruction
Opcode
0
1
0
0
Register
Addresses
0
0
0
1
Status Data
(Sent by Slave on SO)
Status Data
(Sent by Slave on SO)
X X X X X X X X
0
0
0
0
0
0
0 WIP
CS
Rising
Edge
Notes: (1) “A0 and A1”: stand for the device address sent by the master.
(2) WCRx refers to wiper position data in the Wiper Counter Register
(3) “X”: Don’t Care.
REV 1.1.15 5/9/03
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Characteristics subject to change without notice.
10 of 21
X9111 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... –65°C to +135°C
Storage temperature......................... –65°C to +150°C
Voltage on SCK any address input
with respect to VSS ................................. –1V to +7V
∆V = | (VH–VL) | ......................................................5V
Lead temperature (soldering, 10 seconds) ........ 300°C
IW (10 seconds) ..................................................±6mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
Max.
Device
Supply Voltage (VCC) Limits
Commercial
0°C
+70°C
X9111
5V ±10%
Industrial
–40°C
+85°C
X9111-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended industrial operation conditions unless otherwise stated.)
Limits
Symbol
Parameter
RTOTAL
End to End Resistance
Min.
Typ.
Max.
100
End to End Resistance Tolerance
Units
Test Conditions
kΩ
±20
%
Power Rating
50
mW
IW
Wiper Current
±3
mA
RW
Wiper Resistance
40
110
Ω
Wiper Current = ± 50µA,
VCC = 5V
150
300
Ω
Wiper Current = ± 50µA,
VCC = 3V
5
V
VSS = 0V
VTERM
Voltage on any RH or RL Pin
Noise
Resolution
VSS
-120
dBV
1.6
%
(1)
Absolute Linearity
±1.5
Relative
Linearity(2)
±0.5
Temperature Coefficient of RTOTAL
Potentiometer Capacitancies
MI(3)
Rw(n)(actual) – Rw(n)(expected),
where n=8 to 1006
±2.0
MI(3)
Rw(n)(actual) – Rw(n)(expected)(6)
±0.5
MI(3)
Rw(m + 1) – [Rw(m) + MI], where
m=8 to 1006
±1.0
MI(3)
Rw(m + 1) – [Rw(m) + MI](6)
ppm/°C
20
10/10/25
Ref: 1V
±1
±300
Ratiometric Temp. Coefficient
CH/CL/CW
25°C, each pot
ppm/°C
pF
See Macro model
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 1023 or (RH – RL) / 1023, single pot
(4) n = 0, 1, 2, …,1023; m =0, 1, 2, …, 1022.
(5) ESD Rating on RH, RL, RW pins is 1.5KV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0KV.
REV 1.1.15 5/9/03
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Characteristics subject to change without notice.
11 of 21
X9111 – Preliminary Information
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
400
µA
fSCK = 2.5 MHz, SO = Open, VCC=5.5V
Other Inputs = VSS
5
mA
fSCK = 2.5MHz, SO = Open, VCC=5.5V
Other Inputs = VSS
ICC1
VCC supply current
(active)
ICC2
VCC supply current
(nonvolatile write)
ISB
VCC current (standby)
3
µA
SCK = SI = VSS, Addr. = VSS,
CS = VCC = 5.5V
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 1
V
VIL
Input LOW voltage
–1
VCC x 0.3
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
VOL
Output LOW voltage
VCC - 0.8
V
IOH = -1mA, VCC ≥ +3V
VOL
Output LOW voltage
VCC - 0.4
V
IOH = -0.4mA, VCC ≤ +3V
1
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum Endurance
100,000
Data changes per bit per register
Data Retention
100
years
CAPACITANCE
Symbol
(6)
CIN/OUT
(6)
COUT
(6)
CIN
Test
Max.
Units
Test Conditions
Input/Output capacitance (SI)
8
pF
VOUT = 0V
Output capacitance (SO)
8
pF
VOUT = 0V
Input capacitance (A0, CS, WP, HOLD, and SCK)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
(6)
tr VCC
Parameter
VCC power-up rate
Min.
Max.
Units
0.2
50
V/ms
(7)
Power-up to initiation of read operation
1
ms
(7)
Power-up to initiation of write operation
50
ms
tPUR
tPUW
Notes: (6) This parameter is not 100% tested
(7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be
issued. These parameters are not 100% tested.
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Characteristics subject to change without notice.
12 of 21
X9111 – Preliminary Information
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
EQUIVALENT A.C. LOAD CIRCUIT
3V
5V
1462Ω
SPICE Macromodel
1382Ω
RTOTAL
SO pin
SO pin
2714Ω
1217Ω
100pF
RL
RH
100pF
CW
CL
10pF
CL
10pF
25pF
RW
AC TIMING
Symbol
Parameter
Min.
Max.
Units
2.0
MHz
fSCK
SSI/SPI clock frequency
tCYC
SSI/SPI clock cycle time
400
ns
tWH
SSI/SPI clock high time
150
ns
tWL
SSI/SPI clock low time
150
ns
tLEAD
Lead time
150
ns
tLAG
Lag time
150
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
50
ns
tRI
SI, SCK, HOLD and CS input rise time
50
ns
tFI
SI, SCK, HOLD and CS input fall time
50
ns
500
ns
100
ns
tDIS
SO output disable time
0
tV
SO output valid time
tHO
SO output hold time
tRO
SO output rise time
50
ns
tFO
SO output fall time
50
ns
0
ns
tHOLD
HOLD time
400
ns
tHSU
HOLD setup time
50
ns
tHH
HOLD hold time
50
ns
tHZ
HOLD low to output in high Z
100
ns
tLZ
HOLD high to output in low Z
100
ns
TI
Noise suppression time constant at
SI, SCK, HOLD and CS inputs
20
ns
tCS
CS deselect time
100
ns
tWPASU
WP, A0, A1 setup time
0
ns
tWPAH
WP, A0, A1 hold time
0
ns
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Characteristics subject to change without notice.
13 of 21
X9111 – Preliminary Information
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
Typ.
Max.
Units
5
10
ms
XDCP TIMING
Symbol
Parameter
Min.
Max.
Units
tWRPO
Wiper response time after the third (last) power supply is stable
5
10
µs
Wiper response time after instruction issued (all load
instructions)
5
10
µs
tWRL
SYMBOL TABLE
WAVEFORM
REV 1.1.15 5/9/03
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
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Characteristics subject to change without notice.
14 of 21
X9111 – Preliminary Information
TIMING DIAGRAMS
Input Timing
tCS
CS
SCK
tSU
tH
tLAG
tCYC
tLEAD
...
tWH
tWL
...
SI
MSB
SO
High Impedance
tRI
tFI
LSB
Output Timing
CS
SCK
...
tV
tDIS
...
MSB
SO
SI
tHO
LSB
ADDR
Hold Timing
CS
tHSU
SCK
tHH
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
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15 of 21
X9111 – Preliminary Information
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
MSB
SI
tWRL
LSB
RW
SO
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
WP
A0
A1
tWPASU
tWPAH
.
REV 1.1.15 5/9/03
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Characteristics subject to change without notice.
16 of 21
X9111 – Preliminary Information
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysterisis
R2
VS
VS
–
+
VO
100KΩ
–
VO
+
}
}
TL072
R1
R2
10KΩ
10KΩ
+12V
REV 1.1.15 5/9/03
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
10KΩ
-12V
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Characteristics subject to change without notice.
17 of 21
X9111 – Preliminary Information
Application Circuits (Continued)
Attenuator
Filter
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
VO = G VS
-1/2 ≤ G ≤ +1/2
R1
R2
}
}
Inverting Amplifier
Equivalent L-R Circuit
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
REV 1.1.15 5/9/03
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Characteristics subject to change without notice.
18 of 21
X9111 – Preliminary Information
15-Bump Chip Scale Package (CSP B15)
Package Outline Drawing
9111TBZ
YWW I
Lot#
a
f
k
d
A3
A2
A1
B3
B2
B1
C3
C2
C1
D3
D2
D1
E3
E2
E1
m
b
j
e
l
Top View (Sample Marking)
Bottom View (Bumped Side)
Side View
e
Side View
Package Dimensions
Package Width
Package Length
Package Height
Body Thickness
Ball Height
Ball Diameter
Ball Pitch - Width
Ball Pitch - Length
Ball to Edge Spacing – Width
Ball to Edge Spacing - Length
REV 1.1.15 5/9/03
c
Ball Matrix
Symbol
a
b
c
d
e
f
j
k
l
m
Min
2.535
3.272
0.644
0.444
0.200
0.300
0.758
0.626
Millimeters
Nominal
2.565
3.302
0.677
0.457
0.220
0.320
0.5
0.5
0.783
0.651
Max
2.595
3.332
0.710
0.470
0.240
0.340
3
2
A
SO
Vcc
1
RL
B
A0
NC*
RH
C
CS
NC*
RW
D
E
SCK
SI
WP
Vss
HOLD
A1
* True no-connect bump
0.808
0.676
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Characteristics subject to change without notice.
19 of 21
X9111 – Preliminary Information
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Code V14
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.041 (1.05)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.15 5/9/03
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20 of 21
X9111 – Preliminary Information
ORDERING INFORMATION
X9111
Y
P
T
V
VCC Limits
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
V14 = 14-Lead TSSOP
B15 = 15-Lead CSP
Potentiometer Organization
Pot
T=
100KΩ
LIMITED WARRANTY
©Xicor, Inc. 2003 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
REV 1.1.15 5/9/03
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21 of 21