APPLICATION NOTES
A V A I L A B L E
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Noise/Low Power/2-Wire Bus
X9428
Single Digitally Controlled Potentiometer (XDCP™)
FEATURES
DESCRIPTION
• Solid state potentiometer
• 2-wire serial interface
• Register oriented format
—Direct Read/Write/Transfer Wiper Position
—Store as many as Four Positions per
Potentiometer
• Power supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = –2.7V to –5.5V
• Low power CMOS
—Standby current < 1µA
—Ideal for Battery Operated Applications
• High reliability
—Endurance–100,000 Data Changes per Bit per
Register
—Register Data Retention–100 years
• 4-bytes of nonvolatile memory
• 10K Ohm resistor array
• Resolution: 64 taps each potentiometer
• SOIC and TSSOP packages
The X9428 integrates a digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents of
the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
VSS
V+
V–
R0 R1
SCL
SDA
A0
A2
Interface
and
Control
Circuitry
8
R2 R3
A3
Data
Wiper
Counter
Register
(WCR)
VH/RH
VL/RL
VW/RW
WP
REV 1.1.5 7/8/03
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Characteristics subject to change without notice.
1 of 20
X9428
PIN DESCRIPTIONS
PIN CONFIGURATION
Host Interface Pins
DIP/SOIC
VCC
1
16
V+
A2
2
15
NC
RL/VL
3
14
A0
RH/VH
4
13
NC
RW/VW
5
12
A3
SDA
6
11
SCL
WP
VSS
7
10
NC
8
9
V–
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9428.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs. An open drain output requires the
use of a pull-up resistor. For selecting typical values,
refer to the guidelines for calculating typical values on
the bus pull-up resistors graph.
X9428
TSSOP
Device Address (A0, A2, A3)
The Address inputs are used to set the least significant
3 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9428. A maximum of 8 devices may occupy the
2-wire serial bus.
A2
1
14
VCC
RL
2
13
V+
RH
3
12
A0
RW
4
11
NC
SDA
5
10
A3
WP
6
9
SCL
VSS
7
8
V–
X9428
Potentiometer Pins
RH/VH, RL/VL
The RH/VH and RL/VL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
RW/VW
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input WP
The WP pin when low prevents nonvolatile writes to the
Data Registers.
Analog Supply V+, VThe Analog Supply V+, V- are the supply voltages for
the XDCP analog section.
REV 1.1.5 7/8/03
PIN NAMES
Symbol
Description
SCL
Serial clock
SDA
Serial data
A0, A2, A3
RH/VH, VL/RH
RW/VW
WP
V+,V-
Device address
Potentiometer Pins
(terminal equivalent)
Potentiometer Pin (wiper equivalent)
Hardware write protection
Analog and voltage follower
VCC
System supply voltage
VSS
System ground
NC
No connection
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Characteristics subject to change without notice.
2 of 20
X9428
PRINCIPLES OF OPERATION
The X9428 is a highly integrated microcircuit
incorporating a resistor array and its associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9428 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9428 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9428 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (tHIGH). The X9428 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
REV 1.1.5 7/8/03
The X9428 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9428 will respond with a final acknowledge.
Array Description
The X9428 is comprised of a resistor array. The array
contains 63 discrete resistive segments that are
connected in series. The physical ends of the array are
equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9428
this is fixed as 0101[B].
Figure 1. Slave Address
Device Type
Identifier
0
1
0
1
A3
A2
0
A0
Device Address
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0, A2, A3 inputs. The X9428 compares the
serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9428 to respond with an acknowledge. The A0,
A2, A3 inputs can be actively driven by CMOS input
signals or tied to VCC or VSS.
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Characteristics subject to change without notice.
3 of 20
X9428
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9428
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9428 is still busy with the write operation no ACK will
be returned. If the X9428 has completed the write
operation an ACK will be returned, and the master can
then proceed with the next operation.
Flow 1. ACK Polling Sequence
Issue
START
ACK
Returned?
Issue STOP
I3
I2
I1
I0
R1
R0
0
0
Instructions
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers
that is to be acted upon when a register oriented
instruction is issued. Bits 0 and 1 are defined to be 0.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9428; either between the host and one
of the Data Registers or directly between the host and
the Wiper Counter Register. These instructions are:
Read Wiper Counter Register (read the current wiper
position of the selected pot), write Wiper Counter
Register (change current wiper position of the selected
pot), read Data Register (read the contents of the
selected nonvolatile register) and write Data Register
(write a new value to the selected Data Register). The
sequence of operations is shown in Figure 4.
NO
YES
Further
Operation?
Register
Select
Four of the seven instructions end with the
transmission of the instruction byte. The basic
sequence is illustrated in Figure 3. These two-byte
instructions exchange data between the Wiper Counter
Register and one of the Data Registers. A transfer from
a Data Register to a Wiper Counter Register is
essentially a write to a static RAM. The response of the
wiper to this action will be delayed tWRL. A transfer
from the Wiper Counter Register (current wiper
position), to a Data Register is a write to nonvolatile
memory and takes a minimum of tWR to complete.
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue Slave
Address
Figure 2. Instruction Byte Format
NO
YES
Issue
Instruction
Issue STOP
Proceed
Proceed
Instruction Structure
The next byte sent to the X9428 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of four associated registers. The format is
shown below in Figure 2.
REV 1.1.5 7/8/03
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Characteristics subject to change without notice.
4 of 20
X9428
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
0
A0
A
C
K
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9428 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(tHIGH) while SDA is HIGH, the selected wiper will
I3
I2
I1
I0
R1 R0 0
0
A
C
K
S
T
O
P
move one resistor segment towards the VH/RH
terminal. Similarly, for each SCL clock pulse while SDA
is LOW, the selected wiper will move one resistor
segment towards the VL/RL terminal. A detailed
illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
Table 1. Instruction Set
Instruction
I3
I2
Instruction Set
I1 I0 R1 R0
1
0
0
1
0
0
X1
X0
0
0
0
Read the contents of the Wiper Counter Register
0
0
0
Write new value to the Wiper Counter Register
0
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
1
0
1
0
1
0
1
1
1/0 1/0
0
Write Data Register
1
1
0
0
1/0 1/0
0
XFR Data Register to
Wiper Counter Register
XFR Wiper Counter
Register to Data Register
Increment/Decrement
Wiper Counter Register
1
1
0
1
1/0 1/0
0
1
1
1
0
1/0 1/0
0
0
0
1
0
Note:
0
0
0
Operation
Read the contents of the Data Register pointed to
by R1–R0
0 Write new value to the Data Register pointed to by
R1–R0
0 Transfer the contents of the Data Register pointed
to by R1–R0 to its Wiper Counter Register
0 Transfer the contents of the Wiper Counter Register
to the Data Register pointed to by R1–R0
1/0 Enable Increment/decrement of the Wiper Counter
Register
(7) 1/0 = data is one or zero
REV 1.1.5 7/8/03
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Characteristics subject to change without notice.
5 of 20
X9428
Figure 4. Three-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 0
A0 A
C
K
I3
I2
I1 I0
R1 R0 0
0
A
C
K
0
0
D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
Figure 5. Increment/Decrement Instruction Sequence
SCL
SDA
X
S
T
A
R
T
0
1
0
1
A3 A2 0
A0
A
C
K
I3
I2
I1
I0
X
R1 R0
0
0
A
C
K
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
Issued
tWRID
SCL
SDA
VW/RW
REV 1.1.5 7/8/03
Voltage Out
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Characteristics subject to change without notice.
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X9428
Figure 7. Acknowledge Response from Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
Acknowledge
Figure 8. Detailed Potentiometer Block Diagram
Serial Data Path
Serial
Bus
Input
From Interface
Circuitry
Register 0
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
C
o
u
n
t
e
r
Register 1
8
Register 2
VH/RH
6
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Register 3
D
e
c
o
d
e
INC/DEC
Logic
UP/DN
Modified SCL
UP/DN
VL/RL
CLK
VW/RW
REV 1.1.5 7/8/03
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Characteristics subject to change without notice.
7 of 20
X9428
DETAILED OPERATION
Register Descriptions
The potentiometer has a Wiper Counter Register and
four Data Registers. A detailed discussion of the
register organization and array operation follows.
Wiper Counter Register
The X9428 contains a Wiper Counter Register. The
Wiper Counter Register can be envisioned as a 6-bit
parallel and serial load counter with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered
in four ways: it may be written directly by the host via
the write Wiper Counter Register instruction (serial
load); it may be written indirectly by transferring the
contents of one of four associated Data Registers via
the XFR Data Register instruction (parallel load); it can
be modified one step at a time by the Increment/
Decrement instruction. Finally, it is loaded with the
contents of its Data Register zero (DR0) upon powerup.
The WCR is a volatile register; that is, its contents are
lost when the X9428 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be different
from the value present at power-down.
Data Registers
The potentiometer has four nonvolatile Data Registers.
These can be read or written directly by the host and
data can be transferred between any of the four Data
Registers and the Wiper Counter Register. It should be
noted all operations changing data in one of these
registers is a nonvolatile operation and will take a
maximum of 10ms.
Data Registers, (6-Bit), Nonvolatile
D5
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
NV
(MSB)
(LSB)
Four 6-bit Data Registers for each XDCP. (eight 6-bit
registers in total).
– {D5~D0}: These bits are for general purpose not
volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the Wiper Counter
Register on power-up.
Wiper Counter Register, (6-Bit), Volatile
WP5
WP4
WP3
WP2
WP1
WP0
V
V
V
V
V
V
(MSB)
(LSB)
One 6-bit wiper counter register for each XDCP. (Four
6-bit registers in total.)
– {D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
REV 1.1.5 7/8/03
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Characteristics subject to change without notice.
8 of 20
X9428
Instruction Format
Notes: (1)
(2)
(3)
(4)
(5)
“MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
“A3 ~ A0”: stands for the device addresses sent by the master.
“X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
“I”: stands for the increment operation, SDA held high during active SCL phase (high).
“D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A 0 A
3 2
0
T
instruction
wiper position
S
S
opcode
(sent by slave on SDA)
A
A
W W W W W W
C
C
K 1 0 0 1 0 0 0 0 K 0 0 P P P P P P
5 4 3 2 1 0
M
A
C
K
S
T
O
P
instruction
wiper position
S
S
opcode
(sent by master on SDA)
A
A
W W W W W W
C
C
1
0
1
0
0
0
0
0
0
0
P P P P P P
K
K
5 4 3 2 1 0
S
A
C
K
S
T
O
P
wiper position/data
S
(sent by slave on SDA)
A
W W W W W W
C
0
0
P P P P P P
K
5 4 3 2 1 0
M
A
C
K
S
T
O
P
Write Wiper Counter Register (WCR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A 0 A
3 2
0
T
Read Data Register (DR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A 0 A
3 2
0
T
instruction
register
S
opcode
addresses
A
C
R R
K 1 0 1 1 1 0 0 0
Write Data Register (DR)
S device type
device
instruction
register
S
T identifier
addresses
opcode
addresses
A
A
C
R R
R 0 1 0 1 A A 0 A
1 1 0 0
0 0
3 2
0 K
1 0
T
wiper position/data
S
(sent by master on SDA)
A
W W W W W W
C
0 0 P P P P P P
K
5 4 3 2 1 0
S
A
C
K
S
T HIGH-VOLTAGE
O WRITE CYCLE
P
XFR Data Register (DR) to Wiper Counter Register (WCR)
S device type
device
instruction
register
S
T identifier
addresses
opcode
addresses
A
A
C
A
A
A
R R
R 0 1 0 1
0
1 1 0 1
0 0
3 2
0 K
1 0
T
REV 1.1.5 7/8/03
S
A
C
K
S
T
O
P
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Characteristics subject to change without notice.
9 of 20
X9428
XFR Wiper Counter Register (WCR) to Data Register (DR)
S device type
device
T identifier
addresses
A
R 0 1 0 1 A A 0 A
3 2
0
T
instruction
register
S
opcode
addresses
A
C
R R
K 1 1 1 0 1 0 0 0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register (WCR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A 0 A
3 2
0
T
increment/decrement
instruction
S
S
opcode
(sent by master on SDA)
A
A
C
C I/ I/
I/ I/
K 0 0 1 0 0 0 0 0 K D D . . . . D D
SYMBOL TABLE
REV 1.1.5 7/8/03
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
INPUTS
OUTPUTS
120
Must be
steady
Will be
steady
100
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Resistance (K)
WAVEFORM
S
T
O
P
80
60
V
RMIN = CC MAX =1.8KΩ
IOL MIN
RMAX =
tR
CBUS
Max.
Resistance
40
20 Min.
Resistance
0
0 20 40 60
80 100 120
Bus Capacitance (pF)
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Characteristics subject to change without notice.
10 of 20
X9428
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ....................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Voltage on SDA, SCL or any address
input with respect to VSS .........................–1V to +7V
Voltage on V+ (referenced to VSS)......................... 10V
Voltage on V- (referenced to VSS)......................... -10V
(V+) – (V-).............................................................. 12V
Any VH/RH ............................................................... V+
Any VL/RL ................................................................. VLead temperature (soldering, 10 seconds)........ 300°C
IW (10 seconds)................................................ ±12mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Device
Supply Voltage (VCC) Limits
Commercial
0°C
+70°C
X9428
5V ±10%
Industrial
–40°C
+85°C
X9428-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
Max.
Unit
End to end resistance tolerance
±20
%
Power rating
50
mW
IW
Wiper current
RW
Wiper resistance
V+
VVTERM
Voltage on V+ pin
Voltage on V- pin
Min.
Typ.
±6
mA
250
Ω
Wiper current = ± 1mA, VCC = 3V
40
100
Ω
Wiper current = ± 1mA, VCC = 5V
V
+4.5
+5.5
X9428-2.7
+2.7
+5.5
X9428
-5.5
-4.5
X9428-2.7
-5.5
-2.7
V-
V+
Noise
Resolution (4)
dBV
%
Potentiometer Capacitances
REV 1.1.5 7/8/03
MI(3)
Vw(n)(actual)—Vw(n)(expected)
±0.2
MI(3)
Vw(n + 1)—[Vw(n) + MI]
ppm/°C
±20
10/10/25
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Ref: 1kHz
±1
±300
Ratiometric Temperature Coefficient
CH/CL/CW
V
1.6
linearity (2)
Temperature Coefficient of RTOTAL
V
-140
Absolute linearity (1)
Relative
25°C, each pot
150
X9428
Voltage on any VH/RH or VL/RL pin
Test Conditions
ppm/°C
pF
See Circuit #3,
Spice Macromodel
Characteristics subject to change without notice.
11 of 20
X9428
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
1
mA
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
100
µA
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
ICC1
VCC supply current
(nonvolatile write)
ICC2
VCC supply current
(move wiper, write, read)
ISB
VCC current (standby)
1
µA
SCL = SDA = VCC, Addr. = VSS
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC x 0.5
V
VIL
Input LOW voltage
–0.5
VCC x 0.1
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH—RL)/63, single pot
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
Years
CAPACITANCE
Symbol
(5)
(5)
CI/O
CIN
Test
Max.
Unit
Test Conditions
Input/output capacitance (SDA)
8
pF
VI/O = 0V
Input capacitance (A0, A1, A2, A3, and SCL)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
Parameter
Min.
(6)
Power-up to initiation of read operation
(6)
tPUW
Power-up to initiation of write operation
tRVCC(7)
VCC Power up ramp rate
tPUR
0.2
Typ.
Max.
Unit
1
ms
5
ms
50
V/msec
POWER-UP AND POWER-DOWN
There are no restrictions on the power-up or power-down sequencing of the bias supplies VCC, V+, and V- provided
that all three supplies reach their final values within 1msec of each other. However, at all times, the voltages on the
potentiometer pins must be less than V+ and more than V–. The recall of the wiper position from nonvolatile
memory is not in effect until all supplies reach their final value.
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
REV 1.1.5 7/8/03
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Characteristics subject to change without notice.
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X9428
A.C. TEST CONDITIONS
Circuit #3 SPICE Macro Model
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
RTOTAL
RH
CL
CH
CW
RL
10pF
EQUIVALENT A.C. LOAD CIRCUIT
10pF
5V
2.7V
25pF
RW
1533Ω
SDA Output
100pF
100pF
AC TIMING (over recommended operating conditions)
Symbol
Parameter
Min.
Max.
Unit
400
kHz
fSCL
Clock frequency
100
tCYC
Clock cycle time
2500
ns
tHIGH
Clock high time
600
ns
tLOW
Clock low time
1300
ns
tSU:STA
Start setup time
600
ns
tHD:STA
Start hold time
600
ns
tSU:STO
Stop setup time
600
ns
tSU:DAT
SDA data input setup time
100
ns
tHD:DAT
SDA data input hold time
30
ns
tR
SCL and SDA rise time
300
ns
tF
SCL and SDA fall time
300
ns
tAA
SCL low to SDA data output valid time
900
ns
tDH
SDA data output hold time
50
ns
Noise suppression time constant at SCL and SDA inputs
50
ns
TI
1300
ns
tSU:WPA
WP, A0, A1, A2 and A3 setup time
0
ns
tHD:WPA
WP, A0, A1, A2 and A3 hold time
0
ns
tBUF
REV 1.1.5 7/8/03
Bus free time (prior to any transmission)
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X9428
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
tWR
Typ.
Max.
Unit
5
10
ms
High-voltage write cycle time (store instructions)
XDCP TIMING
Symbol
tWRPO
Parameter
Min.
Max.
Unit
10
µs
Wiper response time after the third (last) power supply is stable
tWRL
Wiper response time after instruction issued (all load instructions)
10
µs
tWRID
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
10
µs
Note:
(8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL.
TIMING DIAGRAMS
START and STOP Timing
(START)
(STOP)
tF
tR
SCL
tSU:STA
tHD:STA
tSU:STO
tR
tF
SDA
Input Timing
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
tHD:DAT
tBUF
Output Timing
SCL
SDA
tDH
tAA
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14 of 20
X9428
XDCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
SDA
tWRL
VW/RW
XDCP Timing (for Increment/Decrement Instruction)
SCL
SDA
Wiper Register Address
Inc/Dec
Inc/Dec
tWRID
VW/RW
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(Any Instruction)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A2, A3
REV 1.1.5 7/8/03
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X9428
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
VW/RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysteresis
R2
VS
VS
–
+
VO
100KΩ
–
VO
+
}
}
TL072
R1
R2
10KΩ
10KΩ
+12V
REV 1.1.5 7/8/03
10KΩ
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
-12V
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X9428
Application Circuits (continued)
Attenuator
Filter
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
All RS = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2pRC)
VO = G VS
-1/2 ≤ G ≤ +1/2
R1
R2
}
}
Inverting Amplifier
Equivalent L-R Circuit
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
REV 1.1.5 7/8/03
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Characteristics subject to change without notice.
17 of 20
X9428
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.5 7/8/03
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18 of 20
X9428
PACKAGING INFORMATION
16-Lead Plastic SOIC (300 Mil Body) Package Type S
0.290 (7.37)
0.299 (7.60)
0.393 (10.00)
0.420 (10.65)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.403 (10.2 )
0.413 ( 10.5)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50) X 45°
0.050" Typical
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.050"
Typical
0.420"
0.015 (0.40)
0.050 (1.27)
FOOTPRINT
0.030" Typical
16 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.5 7/8/03
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X9428
Ordering Information
X9428
Y
P
T
V
VCC Limits
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
P = 16-Lead Plastic DIP*
S = 16-Lead SOIC
V = 14-Lead TSSOP
Potentiometer Organization
Y=
2KΩ
W=
10KΩ
*Note: P package only available as X9428WP16I-2.7 for prototyping. Other resistor values not available in package.
LIMITED WARRANTY
©Xicor, Inc. 2000 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
REV 1.1.5 7/8/03
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Characteristics subject to change without notice.
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