XC73144 144-Macrocell CMOS EPLD Product Specifications Features The Universal Interconnect Matrix connects the Function Blocks to each other and to all input pins, providing 100% connectivity between the Function Blocks. This allows logic functions to be mapped into the Function Blocks and interconnected without routing restrictions. • High-Performance EPLD – 7.5 ns pin-to-pin speed on all fast inputs – 100 MHz maximum clock frequency • Advanced Dual-Block architecture – Four Fast Function Blocks – Twelve High-Density Function Blocks The XC73144 is designed in a 0.8 µ CMOS EPROM technology. In addition, the XC73144 includes a programmable power management feature to specify high-performance or lowpower operation on an individual Macrocell-by-Macrocell basis. Unused Macrocells are automatically turned off to minimize power dissipation. Designers can operate speed-critical paths at maximum performance, while noncritical paths dissipate less power. • 100% interconnect matrix • High-Speed arithmetic carry network – 1 ns ripple-carry delay per bit – 43 MHz 16-bit accumulators • 144 Macrocells with programmable I/O architecture • Up to 132 inputs programmable as direct, latched, or registered Xilinx development software (XEPLD) supports all members of XC7300 family. The designer can create, implement, and verify digital logic circuits for EPLD devices using the Xilinx XEPLD Development System. Designs can be represented as schematics consisting of XEPLD library components, as behavioral descriptions, or as a mixture of both. The XEPLD translator automatically performs logic optimization, collapsing, mapping and routing without user intervention. After compiling the design, XEPLD translator produces documentation for design analysis and creates a programming file to configure the device. • All outputs with 24 mA drive • 3.3 V or 5 V I/O operation • Meets JEDEC Standard (8-1A) for 3.3 V ± 0.3 V • Power management options • Multiple security bits for design protection • 160-pin plastic quad flat pack and 225-pin ball-gridarray packages • 100% PCI compliant The following lists some of the XEPLD Development System features. • Programmable slew rate • Programmable ground control • Familiar design approach similar to TTL and PLD techniques General Description The XC73144 is a member of the Xilinx Dual-Block EPLD family. It consists of four Fast Function Blocks and twelve High-Density Function Blocks interconnected by a central Universal Interconnect Matrix (UIM). The sixteen Function Blocks in the XC73144 are PAL-like structures, complete with programmable product term arrays and programmable multilevel Macrocells. Each Function Block receives 24 inputs, contains nine Macrocells configurable for registered or combinatorial logic and produces nine outputs which feedback to the UIM and output pins. • Converts netlist to fuse map in minutes using a 386/ 486 PC or workstation platform • Interfaces to standard third-party CAE schematics, simulation tools, and behavioral languages • Timing simulation using Viewsim, OrCAD VST, Mentor, LMC and other tools compatible with the Xilinx Netlist Format (XNF) 2-65 This document was created with FrameMaker 4 0 2 XC73144 Programmable Logic Device BG225 19 18 17 15 13 11 H1 H2 G1 G3 E1 F3 I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI 6 12 12 FFB1 N3 P4 P5 N6 P7 R6 P8 R8 N8 MC1-1 MC2-9 I/FO I/FO MC1-2 MC2-8 I/FO I/FO MC1-3 MC2-7 I/FO I/FO MC1-4 MC2-6 I/FO I/FO MC1-5 MC2-5 I/FO I/FO MC1-6 MC2-4 I/FO I/FO MC1-7 MC2-3 I/FO I/FO MC1-8 MC2-2 I/FO I/FO MC1-9 MC2-1 I/FO 12 12 3 3 9 9 9 MC3-9 I/FO MC4-2 MC3-8 I/FO I/FO MC4-3 MC3-7 I/FO I/FO MC4-4 MC3-6 I/FO I/FO MC4-5 MC3-5 I/FO I/FO MC4-6 MC3-4 I/FO I/FO MC4-7 MC3-3 I/FO I/FO MC4-8 MC3-2 I/FO I/FO MC4-9 MC3-1 I/FO 12 12 3 3 9 9 AND ARRAY MC4-1 I/FO 9 18 54 Arithmetic I/O/FI MC5-8 I/O/FI MC16-3 MC5-7 I/O/FI I/O MC16-4 MC5-6 I/O I/O MC16-5 MC5-5 I/O I/O MC16-6 MC5-4 I/O I/O/FI MC16-7 MC5-3 I/O I/O/FI MC16-8 MC5-2 I/O I/O/FI MC16-9 MC5-1 I/O I/O MC15-1 MC6-9 I/O/FI I/O MC15-2 MC6-8 I/O/FI I/O MC15-3 MC6-7 I/O/FI I/O MC15-4 MC6-6 I/O I/O MC15-5 MC6-5 I/O I/O MC15-6 MC6-4 I/O I/O/FI MC15-7 MC6-3 I/O I/O/FI MC15-8 MC6-2 I/O I/O/FI MC15-9 MC6-1 I/O 21 21 UIM MC7-9 I/O/FI MC14-2 MC7-8 I/O/FI MC14-3 MC7-7 I/O/FI O/FCLK1 MC14-4 O/FCLK2 MC14-5 O MC14-6 I/O/FI MC14-7 I/O/FI MC14-8 I/O/FI MC14-9 21 21 K9 R10 P9 M14 N15 N10 R12 P12 P13 MC7-6 O/FOE1 MC7-5 O/FOE0 MC7-4 O/CKEN1 MC7-3 O/CKEN0 MC7-2 O MC7-1 O O MC13-1 MC8-9 I/O/FI O MC13-2 MC8-8 I/O/FI O MC13-3 MC8-7 I/O/FI O MC13-4 MC8-6 O O MC13-5 MC8-5 O MC8-4 O MC8-3 O 21 21 O MC13-6 I/O/FI MC13-7 I/O/FI MC13-8 MC8-2 O I/O/FI MC13-9 MC8-1 O I/O MC12-1 MC9-9 I/O/FI I/O MC12-2 72 69 57 67 55 50 48 45 43 F1 G2 F2 C1 D2 C2 B2 E2 E3 16 14 12 8 6 2 159 9 7 D7 D9 D12 E11 D10 E10 G12 F12 132 131 119 118 – – – – – MC9-8 I/O/FI I/O MC12-3 MC9-7 I/O/FI C8 A8 B8 C9 C14 D13 A10 B9 A13 140 139 138 135 113 115 136 134 126 I/O MC12-4 MC9-6 I/O I/O MC12-5 MC9-5 I/O I/O MC12-6 MC9-4 I/O I/O/FI MC12-7 MC9-3 I/O I/O/FI MC12-8 MC9-2 I/O I/O/FI MC12-9 MC9-1 I/O B12 B13 B14 D14 E14 F13 G14 F15 G15 124 122 117 111 108 106 104 103 102 AND ARRAY FB9 21 21 FB11 FB10 I/O MC11-1 MC10-9 I/O/FI I/O MC11-2 MC10-8 I/O/FI I/O MC11-3 MC10-7 I/O/FI I/O MC11-4 MC10-6 I/O I/O MC11-5 MC10-5 I/O I/O MC11-6 MC10-4 I/O I/O/FI MC11-7 MC10-3 I/O I/O/FI MC11-8 MC10-2 I/O I/O/FI MC11-9 MC10-1 I/O AND ARRAY N12 P14 N14 M15 K14 J13 J15 H14 G13 R13 R11 R7 P10 N7 P6 R4 N5 R2 FB8 FB12 77 79 82 90 92 95 97 98 101 AND ARRAY MC14-1 O AND ARRAY O AND ARRAY 62 63 64 86 88 68 71 73 75 96 93 91 89 87 84 78 76 74 FB7 O/FCLK0 AND ARRAY M10 L10 L12 K12 K11 L11 M11 J12 G12 AND ARRAY AND ARRAY 21 21 FB13 – – – – – 65 66 83 85 K15 L15 K13 L14 L13 P15 N13 R14 N11 FB6 FB14 K2 L1 N2 M3 P3 P1 L3 M1 P2 AND ARRAY MC5-9 I/O FB15 25 27 33 35 42 34 32 29 37 149 – 150 – 3 – 5 – – FB5 MC16-2 AND ARRAY B10 A5 A4 B4 B3 C3 C10 A11 B6 Shift MC16-1 I/O 21 21 AND ARRAY 130 147 151 153 155 158 129 133 145 D5 D6 E5 E6 G4 E4 J4 F4 F5 42 I/O AND ARRAY F14 E15 D15 E13 B15 A14 C11 A12 C13 142 143 144 146 148 152 154 156 4 54 Carry Serial FB16 105 107 109 112 114 123 125 128 116 A7 A6 B7 C6 B5 A3 C5 A2 B1 9 18 42 22 23 24 26 28 30 FFB3 I/FO AND ARRAY N9 L4 M7 M5 L5 L6 M4 M6 M9 J1 K1 J2 K3 L2 N1 9 FFB4 53 – 52 – 39 – 38 – – PQ160 FFB2 I/FO AND ARRAY 36 44 47 49 54 56 58 59 60 BG225 6 12 AND ARRAY PQ160 Serial Shift Arithmetic Carry Figure 1. XC73144 Functional Block, Diagram 2-66 X5653 XC73144 CMOS EPLD Absolute Maximum Ratings Symbol Parameter Value Units VCC Supply voltage with respect to GND -0.5 to 7.0 V VIN DC Input voltage with respect to GND -0.5 to VCC +0.5 V VTS Voltage applied to 3-state output with respect to GND -0.5 to VCC +0.5 V TSTG Storage temperature -65 to +150 °C TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol Parameter Min TA = 0oC to 70oC Max Units Supply voltage relative to GND Commercial VCCINT/ VCCIO Supply voltage relative to GND Industrial 4.75 5.25 V TA = -40oC to 85oC 4.5 5.5 V Supply voltage relative to GND Military TA = -55oC to TC = +125oC 4.5 5.5 V VCCIO I/O supply voltage relative to GND 3.0 3.6 V VIL Low-level input voltage 0 0.8 V VIH High-level input voltage 2.0 VO Output voltage 0 TIN Input signal transition time The XC73144 features a power-management scheme which permits non-speed-critical paths of a design to be operated at reduced power. Overall power dissipation is often reduced significantly, since, in most systems only a few paths are speed critical. Macrocells can individually be specified for high performance or low power operation by adding attributes to the logic schematic, or declaration statements to the behavioral description. To minimize power dissipation, unused Function Blocks are turned off and unused Macrocells in used Function Blocks are configured for low power operation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC(mA) = MCHP (2.4) + MCLP (2.1) + MC (0.015 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of Macrocells used f = Clock frequency (MHz) V VCCIO V 50.0 ns Figure 2 shows a typical calculation for the XC73144 device, programmed as eight 16-bit counters and operating at the indicated clock frequency. 500 High 300 e anc 400 Typical ICC (mA) Power Management VCC +0.5 form Per er Low Pow 200 100 0 50 Clock Frequency (MHz) 100 X5768 Figure 2. Typical ICC vs Frequency for XC73144 2-67 XC73144 CMOS EPLD DC Characteristics Over Recommended Operating Conditions Symbol Parameter Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA (FO) IOL = 12 mA (I/O) VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCCIO VCC = Max VO = GND or VCCIO VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VO = GND f = 1.0 MHz 5 V TTL High-level output voltage VOH 3.3 V High-level output voltage 5 V Low-level output voltage VOL 3.3 V Low-level output voltage IIL Input leakage current IOZ Output high-Z leakage current CIN Input capacitance for Input and I/O pins CIN Input capacitance for global control pins (FCLK0, FCLK1, FCLK2, FOE0, FOE1) COUT 1 Output capacitance ICC1 2 Supply Current (low power mode) Min VIN = VCC or GND VCCINT = VCCIO = 5 V f = 1.0 MHz @ 25°C Max Units 2.4 V 2.4 V 0.5 V 0.4 V ± 10.0 µA ± 10.0 µA 8.0 pF 12.0 pF 20.0 pF 250 Typ mA Notes: 1. Sample tested 2. Measured with device programmed as eight 16-bit counters Power-up/Reset Timing Parameters Symbol Parameter Min tWMR Master Reset input Low pulse width 100 tRESET Configuration completion time Typ Due to the large number of high current drivers available on the XC73144, two programmable signal management features have been included – slew rate control (SRC) and ground control (GC). Slew rate control is primarily for external system benefit, to reduce ringing and other coupling phenomenon. SRC permits designers to select either 1 V/ns or 1.5 V/ns slew rate on a pin-by-pin basis for any output or I/O signal. This can be done with PLUSASM or schematically, as needed. The defafult slew rate is 1 V/ns. To assign the pins with equations (PLUSASM), the designer needs to only declare them as follows: FAST ON <signal name list> This will assign the signals in the list to have a 1.5 V/ns slew rate. Omitting the signal name list will globally set all signals to be 1.5 V/ns. Specific signals therefore can be declared with 1 V/ns slew rate as follows: FAST OFF <signal name list> 2-68 Units ns 80 Slew Rate and Programmable Ground Control Max 160 µs Schematic control of SRC is also straightforward. Again, the default is 1 V/ns, but to assign specific pins fast, the designer need only attach the “FAST” attribute to the I/O or output buffer or the corresponding pin. Programmable ground control is useful for internal chip signal management. The output buffers of the Fast Function Blocks have an impedance of around 7 Ω when switching high to low, where the High Density Function Blocks impedance is around 14 Ω. Since this low impedance is negligible compared to the impedance of the pin inductance when output current transients occur, a reasonable ground connection can be made by driving unused output pins low and physically attaching them to external ground. The XC73144 architecture permits the automatic assignment of external ground signals to all Macrocells that are not declared as primary outputs or I/Os. Note that the logical function of the buried Macrocell is fully preserved, while its output driver is driving low and physically attached to ground. Should designers not wish to employ programmable ground control, they need only declare all such pins as primary I/Os whether they will be attached externally or not. XC73144 CMOS EPLD Fast Function Block (FFB) External AC Characteristics 3 (Com Only) XC73144-10 XC73144-12 XC73144-15 (Com Only) (Com/Ind Only) Min Min XC73144-7 Symbol Parameter frequency 1, 2 fCF Max count tSUF Fast input setup time before FCLK ↑ tHF Fast input hold time after FCLK ↑ tCOF FCLK ↑ to output valid Fast input to output tPDFO 105.0 1 4.0 1, 2 I/O to output valid tCWF Fast clock pulse width Max Min Max Min Max Units 100.0 80.0 66.7 MHz 5.0 6.0 7.0 ns 0 0 valid 1, 2 tPDFU Max 0 0 ns 5.5 8.0 9.0 12.0 ns 7.5 10.0 12.0 15.0 ns 13.5 19.0 22.0 27.0 ns 4.0 5.0 5.5 6.0 ns High-Density Function Block (FB) External AC Characteristics XC73144-7 (Com Only) XC73144-10 XC73144-12 XC73144-15 (Com Only) (Com/Ind Only) Symbol Parameter Min fC Max count frequency 1, 2 83.3 62.5 55.6 45.5 MHz tSU I/O setup time before FCLK ↑ 1, 2 12.0 16.0 18.0 22.0 ns tH I/O hold time after FCLK ↑ 0 0 0 0 ns tCO FCLK ↑ to output valid tPSU I/O setup time before p-term clock ↑ tPH I/O hold time after p-term clock ↑ tPCO P-term clock ↑ to output valid Max Min 7.0 2 4.0 0 1, 2 Max Min 10.0 Max Min 12.0 Max 15.0 Units ns 6.0 7.0 9.0 ns 0 0 0 ns 15.0 20.0 23.0 28.0 ns 18.0 25.0 30.0 36.0 ns tPD I/O to output valid tCW Fast clock pulse width 4.0 5.0 5.5 6.0 ns tPCW P-term clock pulse width 5.0 6.0 7.5 8.5 ns Preliminary Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional logic delay of tFLOGILP – tFLOGI or t LOGILP – tLOGI. 2. Specifications account for logic paths that use the maximum number of available product terms for a given Macrocell. 3. All appropriate AC specifications tested using Figure 3 as the test load circuit. 2-69 XC73144 CMOS EPLD Fast Function Block (FFB) Internal AC Characteristics Symbol Parameter tFLOGI FFB logic array XC73144-7 XC73144-10 XC73144-12 (Com Only) (Com Only) (Com/Ind Only) Min Min delay 2 Max 1.5 tFLOGILP Low-power FFB logic array delay 2 Max Min 1.5 3.5 Min 2.0 5.5 2.5 Max XC73144-15 2.0 7.0 3.0 Max 8.0 ns ns tFSUI FFB register setup time 1.5 tFHI FFB register hold time 2.5 tFCOI FFB register clock-to-output delay 1.0 1.0 1.0 1.0 ns tFPDI FFB register pass through delay 0.5 0.5 1.0 1.0 ns tFAOI FFB register async. set delay 2.0 2.5 3.0 4.0 ns tPTXI FFB p-term assignment delay 0.8 1.0 1.2 1.5 ns tFFD FFB feedback delay 4.0 5.0 6.5 8.0 ns 2.5 4.0 Units 3.0 ns 3.0 ns High-Density Function Block (FB) Internal AC Characteristics Symbol Parameter XC73144-7 XC73144-10 XC73144-12 (Com Only) (Com Only) (Com/Ind Only) Min Min Max Max Min Max XC73144-15 Min Max Units 5.0 ns FB logic array delay 2 tLOGILP Low power FB logic delay 2 tSUI FB register setup time 1.5 tHI FB register hold time 3.5 tCOI FB register clock-to-output delay 1.0 1.0 1.0 1.0 ns tPDI FB register pass through delay 1.5 2.5 4.0 4.0 ns tAOI FB register async. set/reset delay 2.5 3.0 4.0 5.0 ns tLOGI 3.5 3.5 7.0 4.0 7.5 2.5 9.0 3.0 3.5 11.0 4.0 4.0 ns ns 5.0 ns tRA Set/reset recovery time before FCLK ↑ tHA Set/reset hold time after FCLK ↑ tPRA tPHA tPCI FB p-term clock delay 1.0 0 0 0 ns tOEI FB p-term output enable delay 3.0 4.0 5.0 7.0 ns 5.0 6.0 8.0 12.0 ns 1.0 1.5 2.0 3.0 tCARY8 15.0 19.0 21.0 25.0 ns 0 0 0 0 ns Set/reset recovery time before p-term clock ↑ 7.5 10.0 12.0 15.0 ns Set/reset hold time after p-term clock ↑ 5.0 6.0 8.0 9.0 ns ALU carry delay within 1 FB 4 Carry lookahead delay per additional Functional tCARYFB Block 4 ns Preliminary Notes: 2. Specifications account for logic paths that use the maximum number of available product terms for a given Macrocell. 4. Arithmetic carry delays are measured as the increase in required set-up time to adjacent Macrocell(s) for adder with registered outputs. 2-70 XC73144 Programmable Logic Device I/O Block External AC Characteristics Symbol Parameter XC73144-7 XC73144-10 XC73144-12 (Com Only) (Com Only) (Com/Ind Only) Min Min fIN Max pipeline frequency (input register to FFB or FB register) 2 83.3 tSUIN Input register/latch setup time before FCLK ↑ 4.0 tHIN Input register/latch hold time after FCLK ↑ tCOIN FCLK ↑ to input register/latch output Max 62.5 0 Min Min Max Units 45.5 MHz 5.0 6.0 7.0 ns 0 0 0 ns 3.5 5.0 Max 55.6 2.5 tCESUIN Clock enable setup time before FCLK ↑ Max XC73144-15 4.0 7.0 8.0 5.0 ns 10.0 ns tCEHIN Clock enable hold time after FCLK ↑ 0 0 0 ns tCWHIN FCLK pulse width high time 4.0 5.0 5.5 6.0 ns tCWLIN FCLK pulse width low time 4.0 5.0 5.5 6.0 ns 0 Internal AC Characteristics Symbol Parameter XC73144-7 XC73144-10 XC73144-12 (Com Only) (Com Only) (Com/Ind Only) XC73144-15 Min Min Min Max Min Max Max Max Units tIN Input pad and buffer delay 2.5 3.5 4.0 5.0 ns tFOUT FFB output buffer and pad delay 3.0 4.5 5.0 7.0 ns tOUT FB output buffer and pad delay 4.5 6.5 8.0 10.0 ns tUIM Universal Interconnect Matrix delay 6.0 9.0 10.0 12.0 ns tFOE FOE input to output valid 7.5 10.0 12.0 15.0 ns tFOD FOE input to output disable 7.5 10.0 12.0 15.0 ns tFCLKI Fast clock buffer delay 1.5 2.5 3.0 4.0 ns Preliminary Note: 2. Specifications account for logic paths that use the maximum number of available product terms for a given Macrocell. VTEST R1 Device Output Test Point CL R2 Device Input Rise and Fall Times < 3 ns Output Type VCCIO VTEST R1 R2 CL FO 5.0 V 5.0 V 160 Ω 120 Ω 35 pF 3.3 V 3.3 V 260 Ω 360 Ω 35 pF X3491 Figure 3. AC Load Circuit 2-71 XC73144 Programmable Logic Device XC73144 Pinouts BG225 PQ160 Input XC73144 Output BG225 PQ160 VCCIO Input XC73144 Output D3 1 N4 41 E4 - I/FO MC3-4 P3 42 O/FCLK2 VCCIO MC14-5 F4 - I/FO MC3-2 R2 43 I/O MC6-1 C2 2 O/CKEN1 MC7-4 P4 44 I/FO MC1-2 F5 - I/FO MC3-1 N5 45 I/O MC6-2 G4 3 I/FO MC3-5 R3 46 B1 4 I/FO MC2-1 M5 - I/FO VCCINT MC4-4 J4 5 I/FO MC3-3 P5 47 I/FO MC1-3 D2 6 O/FOE0 MC7-5 R4 48 I/O MC6-3 E3 7 O MC7-1 L6 - I/FO MC4-6 C1 8 O/FOE1 MC7-6 M6 - I/FO MC4-8 E2 9 O MC7-2 N6 49 I/FO MC1-4 D1 10 P6 50 I/O MC6-4 F3 11 I/FI F2 12 I/O/FI E1 13 I/FI G2 14 I/O/FI G3 15 I/FI VCCINT/VPP MC7-7 MC7-8 51 52 I/FO GND MC4-7 M9 53 I/FO MC4-9 P7 54 I/FO MC1-5 N7 55 I/O MC6-5 R6 56 I/FO MC1-6 R7 57 I/O/FI MC6-7 F1 16 I/O/FI G1 17 I/FI H2 18 I/FI P8 58 I/FO MC1-7 H1 19 I/FI R8 59 I/FO MC1-8 H3 20 GND N8 60 I/FO J3 21 MR N9 61 VCCIO I/FI MC7-9 R5 M7 MC1-9 VCCIO K5 - M10 - O J1 22 I/FI L10 - O MC13-2 K1 23 I/FI R9 62 I/O MC12-1 R10 63 I/O MC12-2 P9 64 I/O MC12-3 L11 65 O MC13-6 M11 66 I/O/FI M12 - J2 24 I/FI K2 25 O K3 26 I/FI L1 27 O L2 28 I/FI M1 29 I/O/FI N1 30 I/FI M2 31 L3 32 I/O/FI MC14-7 N2 33 O/FCLK0 P1 34 M3 35 N3 36 K4 - MC14-1 MC14-2 MC14-8 MC13-1 MC13-7 GND P10 67 I/O MC6-6 N10 68 R11 69 I/O I/O/FI MC12-6 MC6-8 P11 70 MC14-3 R12 71 I/O/FI O MC14-6 R13 72 I/O/FI MC6-9 O/FCLK1 MC14-4 P12 73 I/O/FI MC12-8 I/FO MC1-1 N11 74 I/O MC5-1 I/FO MC4-1 P13 75 I/O/FI MC12-9 GND GND MC12-7 L4 - I/FO MC4-2 R14 76 I/O MC5-2 P2 37 I/O/FI MC14-9 N12 77 I/O MC11-1 M4 38 I/FO MC4-3 N13 78 I/O MC5-3 L5 39 I/FO MC4-5 P14 79 I/O MC11-2 R1 40 R15 80 GND 2-72 GND 2-73 XC73144 Pinouts (continued) BG225 PQ160 M13 L12 K12 N14 K11 J12 P15 G12 M14 L13 N15 L14 M15 K13 K14 L15 J14 J13 K15 J15 H14 H15 H13 F11 G13 G15 F15 G14 F14 F13 E15 E14 D15 C15 D14 E13 C14 B15 D13 C13 F12 E12 B14 E11 D12 A15 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Input XC73144 Output BG225 PQ160 VCCIO O O I/O O I/O/FI I/O I/O/FI I/O I/O I/O I/O I/O I/O/FI I/O I/O/FI C12 B13 A14 B12 C11 A13 D11 B11 A12 E10 D10 C10 B10 D9 D7 A11 B9 C9 A10 A9 B8 A8 C8 C7 A7 A6 B7 B6 C6 D6 E6 A5 B5 D5 E5 A4 A3 B4 C5 D4 B3 A2 C4 C3 B2 A1 MC13-3 MC13-4 MC11-3 MC13-5 MC13-8 MC5-4 MC13-9 MC12-4 MC5-5 MC12-5 MC5-6 MC11-4 MC5-7 MC11-5 MC5-8 VCCINT I/O I/O/FI I/O/FI I/O/FI MC11-6 MC5-9 MC11-7 MC11-8 GND GND VCCINT I/O I/O I/O I/O I/O I/O I/O I/O I/O MC11-9 MC10-1 MC10-2 MC10-3 MC16-1 MC10-4 MC16-2 MC10-5 MC16-3 GND I/O I/O I/O I/O I/O I/OFI O O I/O/FI O I/O/FI MC10-6 MC16-4 MC9-5 MC16-5 MC9-4 MC16-9 MC8-1 MC8-2 MC10-7 MC8-6 MC8-7 GND 2-74 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Input XC73144 Output VCCIO I/O/FI I/O I/O/FI I/O/FI I/O MC10-8 MC16-6 MC10-9 MC16-7 MC9-1 GND I/O/FI MC16-8 MC8-4 MC8-5 MC15-7 MC15-1 MC8-8 MC8-9 MC15-8 MC9-2 MC9-6 MC9-3 I/O/FI I/O I/O/FI I/O/FI I/O/FI I/O I/O I/O GND I/O/FI I/O/FI I/O/FI MC9-7 MC9-8 MC9-9 VCCIO I/FO I/FO I/FO I/O/FI I/FO I/FO I/FO I/O I/FO I/FO I/FO I/O I/FO I/O I/FO MC2-9 MC2-8 MC2-7 MC15-9 MC2-6 MC3-8 MC3-6 MC15-2 MC2-5 MC3-9 MC3-7 MC15-3 MC2-4 MC15-4 MC2-3 GND I/O I/FO MC15-5 MC2-2 VCCINT I/O O/CKEN0 MC15-6 MC7-3 GND XC73144 CMOS EPLD For a detailed description of the device architecture, see the XC7300 CMOS EPLD Family data sheet, page 2-1 through 2-10. For a detailed description of the device timing, see pages 2-9, 2-10 and 2-50 through 2-52. For package physical dimensions and thermal data, see Section 4. Ordering Information XC73144 - 7 PQ 160 C Device Type Temperature Range Speed Number of Pins Speed Options -15 15 ns pin-to-pin delay -12 12 ns pin-to-pin delay -10 10 ns pin-to-pin delay (commercial only) -7 7.5 ns pin-to-pin delay (commercial only) Package Type Packaging Options PQ160 160-Pin Plastic Quad Flat Pack BG225 225-Pin Plastic Ball-Grid-Array Temperature Options C Commercial 0oC to 70oC I Industrial -40oC to 85oC Component Availability Pins 44 Type Plastic Ceramic Plastic PQFP PLCC CLCC Plastic PLCC WC44 PC68 Code PC44 68 PQ44 100 84 Ceramic Plastic Ceramic CLCC CLCC PLCC PC84 WC68 -15 XC73144 -12 -10 -7 C = Commercial = 0° to +70°C I = Industrial = -40° to 85°C Parenthesis indicate future product plans 2-75 WC84 160 225 Plastic Ceramic PQFP PGA 144 Plastic PQFP Plastic Ceramic BGA BGA PQ100 PQ160 BG225 WB225 CI CI C C CI CI C C CI CI C C PG144 X5654