XILINX XC4000

XC4000
Logic Cell Array Family

Product Specifications
Features
Description
• Third Generation Field-Programmable Gate Arrays
The XC4000 family of Field-Programmable Gate Arrays
(FPGAs) provides the benefits of custom CMOS VLSI,
while avoiding the initial cost, time delay, and inherent risk
of a conventional masked gate array.
–
–
–
–
–
–
–
–
•
Abundant flip-flops
Flexible function generators
On-chip ultra-fast RAM
Dedicated high-speed carry-propagation circuit
Wide edge decoders (four per edge)
Hierarchy of interconnect lines
Internal 3-state bus capability
Eight global low-skew clock or signal distribution
network
Flexible Array Architecture
– Programmable logic blocks and I/O blocks
– Programmable interconnects and wide decoders
The XC4000 family provides a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs),
interconnected by a powerful hierarchy of versatile routing
resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs).
XC4000 devices have generous routing resources to accommodate the most complex interconnect patterns. They
are customized by loading configuration data into the internal memory cells. The FPGA can either actively read its
configuration data out of external serial or byte-parallel
PROM (master modes), or the configuration data can be
written into the FPGA (slave and peripheral modes).
• Sub-micron CMOS Process
– High-speed logic and Interconnect
– Low power consumption
The XC4000 family is supported by powerful and sophisticated software, covering every aspect of design: from
schematic entry, to simulation, to automatic block placement and routing of interconnects, and finally the creation
of the configuration bit stream.
• Systems-Oriented Features
–
–
–
–
–
IEEE 1149.1-compatible boundary-scan logic support
Programmable output slew rate (2 modes)
Programmable input pull-up or pull-down resistors
12-mA sink current per output
24-mA sink current per output pair
Since Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hardware must be adapted to different user applications. FPGAs
are ideal for shortening the design and development cycle,
but they also offer a cost-effective solution for production
rates well beyond 1000 systems per month.
• Configured by Loading Binary File
– Unlimited reprogrammability
– Six programming modes
• XACT Development System runs on ’386/’486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700
series
– Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
– Fully automatic partitioning, placement and routing
– Interactive design editor for design optimization
– 288 macros, 34 hard macros, RAM/ROM compiler
For a detailed description of the device features, architecture, configuration methods and pin descriptions, see
pages 2-9 through 2-45.
Table 1. The XC4000 Family of Field-Programmable Gate Arrays
Device
XC4003
XC4005
XC4006
XC4008 XC4010/10D
XC4013
XC4020
XC4025
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs (per side)
Max RAM Bits
Number of IOBs
3,000
10 x 10
100
360
30
3,200
80
5,000
14 x 14
196
616
42
6,272
112
6,000
16 x 16
256
768
48
8,192
128
8,000
18 x 18
324
936
54
10,368
144
13,000
24 x 24
576
1,536
72
18,432
192
20,000
28 x 28
784
2,016
84
25,088
224
25,000
32 x 32
1,024
2,560
96
32,768
256
*XC4010D has no RAM
2-47
10,000
20 x 20
400
1,120
60
12,800*
160
XC4000 Logic Cell Array Family
Absolute Maximum Ratings
Symbol
Description
Units
VCC
Supply voltage relative to GND
–0.5 to +7.0
V
VIN
Input voltage with respect to GND
–0.5 to VCC +0.5
V
VTS
Voltage applied to 3-state output
–0.5 to VCC +0.5
V
TSTG
Storage temperature (ambient)
–65 to + 150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
+ 260
°C
TJ
Junction temperature
+ 150
°C
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.
Operating Conditions
Symbol
VCC
Description
Min
Max
Units
Supply voltage relative to GND Commercial 0°C to 85°C junction
4.75
5.25
V
Supply voltage relative to GND Industrial -40°C to 100°C junction
4.5
5.5
V
5.5
V
VCC
V
0.8
V
Supply voltage relative to GND
Military –55°C to 125°C case
4.5
VIH
High-level input voltage (XC4000 has TTL-like input thresholds)
2.0
VIL
Low-level input voltage (XC4000 has TTL-like input thresholds)
0
TIN
Input signal transition time
250
ns
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
DC Characteristics Over Operating Conditions
Symbol
Description
Min
Max
2.4
Units
VOH
High-level output voltage @ IOH = –4.0 mA, VCC min
V
VOL
Low-level output voltage @ IOL = 12.0 mA, VCC min (Note 1)
ICCO
Quiescent LCA supply current (Note 2)
IIL
Leakage current
CIN
Input capacitance (sample tested)
IRIN
Pad pull-up (when selected) @ VIN = 0V (sample tested)
0.02
0.25
mA
IRLL
Horizontal Long Line pull-up (when selected) @ logic Low
0.2
2.5
mA
0.4
–10
V
10
mA
+10
µA
15
pF
Note: 1. With 50% of the outputs simultaneously sinking 12 mA.
2. With no output current loads, no active input or longline pull-up resistors, all package pins at VCC or GND, and
the LCA configured with a MakeBits tie option.
2-48
Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Description
Symbol
Device
Max
Max
Max
Units
Full length, both pull-ups,
inputs from IOB I-pins
TWAF
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
9.0
10.0
11.0
12.0
13.0
15.0
21.0
8.0
9.0
10.0
11.0
12.0
14.0
19.0
5.0
6.0
7.0
8.0
9.0
11.0
17.0
ns
ns
ns
ns
ns
ns
ns
Full length, both pull-ups
inputs from internal logic
TWAFL
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
12.0
13.0
14.0
15.0
16.0
18.0
24.0
11.0
12.0
13.0
14.0
15.0
17.0
23.0
7.0
8.0
9.0
10.0
11.0
13.0
20.0
ns
ns
ns
ns
ns
ns
ns
Half length, one pull-up
inputs from IOB I-pins
TWAO
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
9.0
10.0
11.0
12.0
13.0
15.0
21.0
8.0
9.0
10.0
11.0
12.0
14.0
19.0
6.0
7.0
8.0
9.0
10.0
12.0
18.0
ns
ns
ns
ns
ns
ns
ns
Half length, one pull-up
inputs from internal logic
TWAOL
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
12.0
13.0
14.0
15.0
16.0
18.0
24.0
11.0
12.0
13.0
14.0
15.0
17.0
23.0
8.0
9.0
10.0
11.0
12.0
14.0
21.0
ns
ns
ns
ns
ns
ns
ns
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (TPID)
and output delay (TOPF or TOPS), as listed on page 2-52.
PRELIMINARY
2-49
XC4000 Logic Cell Array Family
Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Global Signal Distribution
From pad through primary buffer, to any clock K
From pad through secondary buffer, to any clock K
-6
-5
-4
Symbol
Device
Max
Max
Max
TPG
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
7.8
8.0
8.2
8.6
9.0
10.0
17.0
5.8
6.0
6.2
6.6
7.0
8.0
15.0
5.1
5.5
5.7
6.1
6.5
7.5
14.5
ns
ns
ns
ns
ns
ns
ns
TSG
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
8.8
9.0
9.2
9.6
10.0
11.0
18.0
6.8
7.0
7.2
7.6
8.0
9.0
16.0
6.3
6.7
6.9
7.3
7.7
8.7
15.7
ns
ns
ns
ns
ns
ns
ns
Units
Horizontal Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Device
Max
Max
Max
Units
TIO1
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
8.8
10.0
10.6
11.1
11.7
13.0
20.0
6.2
7.0
7.5
8.0
8.5
9.5
16.5
4.4
5.5
6.0
6.5
7.0
7.5
14.5
ns
ns
ns
ns
ns
ns
ns
I going Low to L.L. going from resistive pull-up
High to active Low, (TBUF configured as open drain)
TIO2
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
9.3
10.5
11.1
11.6
12.2
13.5
23.5
6.7
7.5
8.0
8.5
9.0
10.0
20.0
5.0
6.0
6.5
7.0
7.5
8.0
18.0
ns
ns
ns
ns
ns
ns
ns
T going Low to L.L. going from resistive pull-up or
floating High to active Low, (TBUF configured as
open drain or active buffer with I = Low)
TON
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
10.7
12.0
12.6
13.2
13.8
15.1
23.0
9.0
10.0
10.5
11.0
11.5
12.6
20.5
7.2
8.0
8.5
9.0
9.5
11.1
19.0
ns
ns
ns
ns
ns
ns
ns
T going High to TBUF going inactive, not driving L.L.
TOFF
All devices
3.0
2.0
1.8
ns
T going High to L.L. going from Low to High,
pulled up by a single resistor
TPUS
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
24.0
26.0
28.0
30.0
32.0
36.0
52.0
20.0
22.0
24.0
26.0
28.0
32.0
48.0
14.0
16.0
18.0
20.0
22.0
26.0
42.0
ns
ns
ns
ns
ns
ns
ns
T going High to L.L. going from Low to High,
pulled up by two resistors
TPUF
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
11.6
12.0
13.0
14.0
15.0
17.0
24.0
9.0
10.0
11.0
12.0
13.0
15.0
22.0
7.0
8.0
9.0
10.0
11.0
13.0
20.0
ns
ns
ns
ns
ns
ns
ns
Description
TBUF driving a Horizontal Longline (L.L.)
I going High or Low to L.L. going High or Low,
while T is Low, i.e. buffer is constantly active
Symbol
PRELIMINARY
2-50
Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be derived
indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a
discrepancy between these two methods, the values listed below should be used, and the derived values must be ignored.
Speed Grade
Description
Global Clock to Output (fast) using OFF
TPG
.
.
.
.
.
OFF
Global Clock-to-Output Delay
TPG
Global Clock-to-Output Delay
TICKOF
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
15.1
15.5
15.7
16.1
16.5
17.5
25.5
12.5
13.0
13.2
13.6
14.0
15.0
22.0
11.6
12.0
12.2
12.6
13.0
14.0
21.0
ns
ns
ns
ns
ns
ns
ns
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
19.9
20.5
20.7
21.1
21.5
22.5
29.5
15.2
16.0
16.2
16.6
17.0
18.0
25.0
14.4
15.0
15.2
15.6
16.0
17.0
24.0
ns
ns
ns
ns
ns
ns
ns
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
2.4
2.0
1.8
1.4
1.0
0.5
0
2.0
1.5
1.3
0.9
0.5
0
0
1.6
1.2
1.0
0.6
0.2
0
0
ns
ns
ns
ns
ns
ns
ns
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
5.1
5.5
5.7
6.1
6.5
7.5
18.0
4.0
4.5
4.7
5.1
5.5
6.5
16.0
4.0
4.5
4.7
5.1
5.5
6.5
15.5
ns
ns
ns
ns
ns
ns
ns
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
21.5
21.0
20.8
20.4
20.0
19.0
18.0
18.5
18.0
17.8
17.4
17.0
16.0
15.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
ns
ns
ns
ns
ns
ns
ns
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
(Max)
(Max)
X3202
Input Set-up Time, using IFF (no delay)
Input
Set-Up
&
Hold
Time
TPSUF
D
IFF
TPG
(Min)
X3201
Input Hold time, using IFF (no delay)
Input
Set-Up
&
Hold
Time
TPHF
D
IFF
TPG
(Min)
X3201
Input Set-up Time, using IFF (with delay)
Input
Set-Up
&
Hold
Time
TPSU
D
IFF
TPG
(Min)
X3201
Input Hold Time, using IFF (with delay)
Input
Set-Up
&
Hold
Time
TPH
D
TPG
IFF
-4
Device
TICKO
.
.
.
.
.
OFF
-5
Symbol
X3202
Global Clock to Output (slew limited) using OFF
-6
(Min)
X3201
Units
Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). When testing fast outputs, only one
output switches. When testing slew-rate limited outputs, half the number of outputs on one side of the device are switching. These
parameter values are tested and guaranteed for worst-case conditions of supply voltage and temperature, and also with the most
unfavorable clock polarity choice.
TPDLI for -4 Speed Grade
Pad to I1, I2
via transparent
latch, with delay
PRELIMINARY
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
TPICKD for -4 Speed Grade
17.6 ns
17.9 ns
18.0 ns
18.3 ns
18.6 ns
19.3 ns
23.5 ns
Input set-up time
pad to clock (IK)
with delay
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
15.6 ns
15.9 ns
16.0 ns
16.3 ns
16.6 ns
17.3 ns
22.5 ns
X6082
See page 2-52
2-51
XC4000 Logic Cell Array Family
IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Symbol
-6
Min
-5
-4
Max
Min Max
4.0
8.0
26.0
8.0
8.0
3.0
7.0
24.0
7.0
7.0
Min Max Units
Input
Propagation Delays
Pad to I1, I2
Pad to I1, I2, via transparent latch (no delay)
Pad to I1, I2, via transparent latch (with delay)
Clock (IK) toI1, I2, (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
TPID
TPLI
TPDLI
TIKRI
TIKLI
Set-up Time (Note 3)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
TPICK
TPICKD
7.0
25.0
6.0
24.0
4.0
**
ns
ns
Hold Time (Note 3)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
TIKPI
TIKPID
1.0
neg
1.0
neg
1.0
neg
ns
ns
Output
Propagation Delays
Clock (OK) to Pad
(fast)
same
(slew rate limited)
Output (O) to Pad
(fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z (slew-rate independent)
3-state to Pad active and valid (fast)
same
(slew -rate limited)
TOKPOF
TOKPOS
TOPF
TOPS
TTSHZ
TTSONF
TTSONS
Set-up and Hold Times
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
TOOK
TOKO
8.0
0
6.0
0
5.5
0
ns
ns
Clock
Clock High or Low time
TCH/TCL
5.0
4.5
4.0
ns
Global Set/Reset
Delay from GSR net through Q to I1, I2
Delay from GSR net to Pad
GSR width*
TRRI
TRPO
TMRW
7.5
11.5
9.0
13.0
9.0
13.0
17.0
7.0
10.0
7.0
10.0
7.0
10.0
13.0
14.5
18.0
21.0
2.8
6.0
**
6.0
6.0
6.5
9.5
5.5
8.5
6.5
9.5
12.5
13.5
17.0
18.0
13.5
14.0
18.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* Timing is based on the XC4005. For other devices see XACT timing calculator.
** See preceding page
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Slew rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on
ground bounce, see pages 8-8 through 8-10.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up or pull-down resistor or alternatively configured as a driven output or be driven from an external source.
3. Input pad setup times and hold times are specified with respect to the internal clock (IK). To calculate system setup time,
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but do not subtract below zero.
Negative hold time means that the delay in the input data is adequate for the external system hold time to be zero,
provided the input clock uses the Global signal distribution from pad to IK.
2-52
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Symbol
-6
Min
-5
-4
Max
Min Max
Min Max Units
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
C inputs via H’ to X/Y outputs
TILO
TIHO
THHO
6.0
8.0
7.0
4.5
7.0
5.0
4.0
6.0
4.5
ns
ns
ns
CLB Fast Carry Logic
Operand inputs (F1,F2,G1,G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1,F3) to COUT
CIN through function generators to X/Y outputs
CIN to COUT, bypass function generators.
TOPCY
TASCY
TINCY
TSUM
TBYP
7.0
8.0
6.0
8.0
2.0
5.5
6.0
4.0
6.0
1.5
5.0
5.5
3.5
5.5
1.5
ns
ns
ns
ns
ns
Sequential Delays
Clock K to outputs Q
TCKO
5.0
3.0
3.0
ns
Set-up Time before Clock K
F/G inputs
F/G inputs via H’
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F'/G'
CIN input via F'/G' and H'
TICK
TIHCK
THHCK
TDICK
TECCK
TRCK
TCCK
TCHCK
6.0
8.0
7.0
4.0
7.0
6.0
8.0
10.0
Hold Time after Clock K
F/G inputs
F/G inputs via H’
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
TCKI
TCKIH
TCKHH
TCKDI
TCKEC
TCKR
Clock
Clock High time
Clock Low time
4.5
6.0
5.0
3.0
4.0
4.5
6.0
7.5
4.5
6.0
5.0
3.0
3.0
4.0
5.5
7.3
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
TCH
TCL
5.0
5.0
4.5
4.5
4.0
4.0
ns
ns
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
TRPW
TRIO
5.0
Master Set/Reset*
Width (High or Low)
Delay from Global Set/Reset net to Q
TMRW
TMRQ
21.0
* Timing is based on the XC4005. For other devices see XACT timing calculator.
2-53
4.0
9.0
4.0
8.0
18.0
33.0
7.0
ns
ns
28.0
ns
ns
18.0
31.0
XC4000 Logic Cell Array Family
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
CLB RAM Option
Description
Write Operation
Address write cycle time
Write Enable pulse width (High)
Address set-up time before beginning of WE
Address hold time after end of WE
DIN set-up time before end of WE
DIN hold time after end of WE
Read Operation
Address read cycle time
Data valid after address change
(no Write Enable)
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
Read During Write
Data valid after WE going active
(DIN stable before WE)
Data valid after DIN
(DIN change during WE)
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
Data setup time before clock K
Speed Grade
Symbol
-6
Min
-5
Max
-4
Min Max
Min Max Units
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
both
TWC
TWCT
TWP
TWPT
TAS
TAST
TAH
TAHT
TDS
TDST
TDHT
9.0
9.0
5.0
5.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16 x 2
32 x 1
16 x 2
32 x 1
TRC
TRCT
TILO
TIHO
7.0
10.0
5.5
7.5
5.0
7.0
ns
ns
ns
ns
16 x 2
32 x 1
TICK
TIHCK
6.0
8.0
16 x 2
32 x 1
16 x 2
32 x 1
TWO
TWOT
TDO
TDOT
16 x 2
32 x 1
16 x 2
32 x 1
TWCK
TWCKT
TDCK
TDCKT
Note: Timing for the 16 x 1 RAM option is identical to 16 x 2 RAM timing
2-54
6.0
8.0
4.5
7.0
4.5
6.0
12.0
15.0
11.0
14.0
12.0
15.0
11.0
14.0
4.0
6.0
4.5
6.0
10.0
12.0
9.0
11.0
10.0
12.0
9.0
11.0
ns
ns
9.0
11.0
8.5
11.0
9.5
11.5
9.0
11.0
ns
ns
ns
ns
ns
ns
ns
ns
CLB RAM Timing Characteristics
T WC
ADDRESS
WRITE
TAS
T WP
T AH
WRITE ENABLE
T DH
T DS
DATA IN
REQUIRED
TILO
READ
X,Y OUTPUTS
VALID
VALID
READ, CLOCKING DATA INTO FLIP-FLOP
TICK
TCH
CLOCK
T CKO
XQ,YQ OUTPUTS
VALID
(OLD)
VALID
(NEW)
READ DURING WRITE
T WP
WRITE ENABLE
T DH
DATA IN
(stable during WE)
T WO
X,Y OUTPUTS
DATA IN
(changing during WE)
VALID
VALID
OLD
NEW
T WO
X,Y OUTPUTS
VALID
(PREVIOUS)
T DO
VALID
(OLD)
VALID
(NEW)
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
T WP
WRITE ENABLE
TWCK
T DCK
DATA IN
CLOCK
T CKO
XQ,YQ OUTPUTS
X2640
2-55
XC4000 Logic Cell Array Family
XC4003 Pinouts
Pin
Description
VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O (A10)
I/O (A11)
–
I/O (A12)
I/O (A13)
–
–
I/O (A14)
SGCK1 (A15,I/O)
VCC
GND
PGCK1 (A16, I/O)
I/O (A17)
–
–
I/O (TDI)
I/O (TCK)
–
I/O (TMS)
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
I/O
SGCK2 (I/O)
O (M1)
GND
I (M0)
VCC
I (M2)
PGCK2 (I/O)
I/O (HDC)
–
–
I/O
I/O (LDC)
I/O
I/O
I/O
I/O
I/O
I/O (ERR, INIT)
VCC
PC84
2
3
4
–
–
5
6
–
7
8
–
–
9
10
11
12
13
14
–
–
15
16
–
17
18
–
–
19
20
21
22
23
24
–
–
25
26
27
–
–
28
29
30
31
32
33
34
35
36
–
–
–
37
38
39
–
–
40
41
42
PQ100 PG120
92
G3
93
G1
94
F1
95
E1
96
F2
97
F3
98
D1
–
E2*
99
C1
100
D2
–
E3*
–
B1*
1
C2
2
D3
3
C3
4
C4
5
B2
6
B3
–
A1*
–
A2*
7
C5
8
B4
–
A3*
9
B5
10
A4
–
C6
11
A5
12
B6
13
A6
14
B7
15
C7
16
A7
17
A8
18
A9
–
B8
19
C8
20
A10
21
B9
22
A11
–
B10*
23
C9
24
A12
25
B11
26
C10
27
C11
28
D11
29
B12
30
C12
31
A13
–
B13*
–
E11*
32
D12
33
C13
34
E12
35
D13
36
F11
37
E13
38
F12
39
F13
40
G12
Bound
Scan
–
32
35
38
41
44
47
–
50
53
–
–
56
59
–
–
62
65
–
–
68
71
–
74
77
80
83
86
89
–
–
92
95
98
101
104
107
110
113
–
116
119
122
–
125†
–
126†
127
130
–
–
133
136
139
142
145
148
151
154
–
Pin
Description
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
–
I/O
SGCK3 (I/O)
GND
DONE
VCC
PROG
I/O (D7)
PGCK3 (I/O)
–
–
I/O (D6)
I/O
I/O (D5)
I/O (CS0)
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O (D2)
I/O
I/O (D1)
I/O (RCLK-BUSY/RDY)
–
–
I/O (D0, DIN)
SGCK4 (DOUT, I/O)
CCLK
VCC
O (TDO)
GND
I/O (A0, WS)
PGCK4 (A1, I/O)
–
–
I/O (CS1, A2)
I/O (A3)
I/O (A4)
I/O (A5)
I/O
I/O
I/O (A6)
I/O (A7)
GND
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 247 = BSCANT.UPD
2-56
This document was created with FrameMaker 4 0 2
PC84
43
44
45
–
–
46
47
48
49
–
–
50
51
52
53
54
55
56
57
–
–
58
–
59
60
–
–
61
62
63
64
65
66
–
–
67
68
69
70
–
–
71
72
73
74
75
76
77
78
–
–
79
80
81
82
–
–
83
84
1
PQ100 PG120
41
G11
42
G13
43
H13
44
J13
45
H12
46
H11
47
K13
48
J12
49
L13
–
K12*
–
J11*
50
M13
51
L12
52
K11
53
L11
54
L10
55
M12
56
M11
57
N13
–
N12*
–
L9*
58
M10
59
N11
60
M9
61
N10
62
L8
63
N9
64
M8
65
N8
66
M7
67
L7
68
N7
69
N6
70
N5
–
M6
71
L6
72
N4
73
M5
74
N3
–
M4*
–
L5*
75
N2
76
M3
77
L4
78
L3
79
M2
80
K3
81
L2
82
N1
–
M1*
–
J3*
83
K2
84
L1
85
J2
86
K1
87
H3
88
J1
89
H2
90
H1
91
G2
Bound
Scan
–
157
160
163
166
169
172
175
178
–
–
181
184
–
–
–
–
187
190
–
–
193
196
199
202
205
208
211
214
–
–
217
220
223
226
229
232
235
238
–
–
241
244
–
–
–
–
2
5
–
–
8
11
14
17
20
23
26
29
–
XC4005 Pinouts
Pin
Description
Bound
PC84 PQ160 PQ208 PG156 Scan
Pin
Description
Bound
PC84 PQ160 PQ208 PG156 Scan
Pin
Description
Bound
PC84 PQ160 PQ208 PG156 Scan
VCC
I/O (A8)
I/O (A9)
I/O
I/O
–
2
3
4
–
–
–
142
143
144
145
146
–
183
184
185
186
187
188*
H3
H1
G1
G2
G3
–
–
44
47
50
53
–
I/O
–
I/O
SGCK2 (I/O)
O (M1)
GND
–
–
28
29
30
31
35
–
36
37
38
39
45
–
46
47
48
49
C12
–
B13
B14
A15
C13
161
–
164
167
170
–
I/O
–
–
–
–
–
–
–
–
–
–
–
88
89 *
89 *
90 1
–
–
114
115*
115*
116*
117 *
118*
T13
R12*
R12*
T12*
–
–
274
–
–
–
–
–
–
I/O (A10)
I/O (A11)
I/O
I/O
GND
–
5
6
–
–
–
147
148
149
150
189*
190
191
192
193
–
F1
F2
E1
E2
–
56
59
62
65
I (M0)
–
–
–
–
32
–
–
–
–
40
–
–
–
–
50
51*
52*
53*
54*
A16
–
–
–
–
173†
–
–
–
–
GND
I/O
I/O
I/O (D5)
I/O (CS0)
–
–
–
59
60
91
92
93
94
95
119
120
121
122
123
P11
R11
T11
T10
P10
–
277
280
283
286
–
–
–
–
I/O (A12)
–
–
–
–
–
7
151
–
–
152*
153*
154
194
195*
196*
197*
198*
199
F3
–
–
D1*
D2*
E3
–
–
–
–
–
68
VCC
I (M2)
PGCK2 (I/O)
I/O (HDC)
I/O
–
33
34
35
36
–
–
41
42
43
44
45
–
55
56
57
58
59
–
C14
B15
B16
D14
C15
–
–
174†
175
178
181
–
–
–
I/O
I/O
I/O (D4)
I/O
–
–
–
–
61
62
–
–
96
97
98
99
124*
125 *
126
127
128
129
–
–
R10
T9
R9
P9
–
–
289
292
295
298
I/O (A13)
8
155
200
C1
71
I/O
–
46
60
D15
184
VCC
63
100
130
R8
–
–
I/O
I/O
I/O (A14)
SGCK1 (A15, I/O)
–
–
–
9
10
–
156
157
158
159
–
201
202
203
204
–
C2
D3
B1
B2
–
74
77
80
83
I/O
I/O (LDC)
–
–
–
–
37
–
–
–
47
48
49*
50*
–
61
62
63*
64*
65 *
E14
C16
E15*
D16*
–
187
190
–
–
–
GND
I/O (D3)
I/O (RS)
I/O
I/O
64
65
66
–
–
101
102
103
104
105
131
132
133
134
135
P8
T8
T7
T6
R7
–
301
304
307
310
VCC
–
–
–
–
GND
11
–
–
–
–
12
160
–
–
–
–
1
205
206*
207*
208*
1*
2
C3
–
–
–
–
C4
–
–
–
–
–
–
–
GND
I/O
I/O
I/O
I/O
–
–
–
–
38
39
–
51
52
53
54
55
66*
67
68
69
70
71
–
F14
F15
E16
F16
G14
–
–
193
196
199
202
–
–
I/O (D2)
I/O
I/O
I/O
–
–
67
68
–
–
–
–
106
107
108
109
136*
137*
138
139
140
141
–
–
P7
T5
R6
T4
–
–
313
316
319
322
–
PGCK1 (A16, I/O)
I/O (A17)
I/O
I/O
–
–
13
14
–
–
–
–
2
3
4
5
–
3*
4
5
6
7
–
–
B3
A1
A2
C5
–
–
86
89
92
95
–
–
–
I/O
I/O
I/O
I/O (ERR, INIT)
–
–
–
–
40
41
–
–
56
57
58
59
72*
73 *
74
75
76
77
–
–
G15
G16
H16
H15
–
–
205
208
211
214
GND
–
–
–
–
I/O (D1)
–
–
–
–
–
69
110
–
–
111 *
112 *
113
142
143*
144 *
145*
146*
147
P6
–
–
R5*
–
T3
–
–
–
–
–
325
I/O (TDI)
15
6
8
B4
98
VCC
42
60
78
H14
–
I/O
(RCLK-BUSY/RDY)
70
114
148
P5
328
I/O (TCK)
–
–
–
–
16
–
–
–
–
7
8*
9*
–
–
9
10*
11*
12*
13*
A3
A4*
–
–
–
101
–
–
–
–
GND
I/O
I/O
I/O
I/O
43
44
45
–
–
61
62
63
64
65
79
80
81
82
83
J14
J15
J16
K16
K15
–
217
220
223
226
I/O
–
I/O
I/O (D0, DIN)
SGCK4 (DOUT, I/O)
–
–
–
71
72
115
–
116
117
118
149
–
150
151
152
R4
–
R3
P4
T2
331
–
334
337
340
GND
–
10
14
C6
–
–
–
–
84*
–
–
CCLK
73
119
153
R2
–
I/O
I/O
I/O (TMS)
I/O
–
–
–
17
18
–
11
12
13
14
–
15
16
17
18
19*
B5
B6
A5
C7
–
104
107
110
113
–
–
I/O
I/O
I/O
I/O
–
46
47
–
–
–
66
67
68
69
85*
86
87
88
89
–
K14
L16
M16
L15
–
229
232
235
238
VCC
–
–
–
–
74
–
–
–
–
120
–
–
–
–
154
155 *
156 *
157 *
158*
P3
–
–
–
–
–
–
–
–
–
–
–
–
20*
–
–
GND
–
70
90
L14
–
O (TDO)
75
121
159
T1
–
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
–
–
–
–
19
20
21
22
23
24
–
–
–
–
15
16
17
18
19
20
21
22
23
24
–
–
21
22
23
24
25
26
27
28
29
30
31*
32*
B7
A6
A7
A8
C8
B8
C9
B9
A9
B10
–
–
116
119
122
125
–
–
128
131
134
137
–
–
–
–
–
–
I/O
I/O
I/O
I/O
I/O
SGCK3 (I/O)
GND
–
–
–
–
–
48
49
–
–
50
51
52
–
–
–
71*
72*
73
74
75
76
77
78
79
–
91*
92*
93*
94*
95
96
97
98
99
100
101
102*
–
–
N16*
M15*
P16
M14
N15
P15
N14
R16
P14
–
–
–
–
–
241
244
247
250
253
256
–
–
GND
I/O (A0,WS)
PGCK4 (A1,I/O)
I/O
–
I/O
I/O (CS1,A2)
I/O (A3)
–
–
–
–
76
77
78
–
–
–
79
80
–
–
–
–
122
123
124
125
–
126
127
128
129 *
130 *
–
–
160
161
162
163
–
164
165
166
167*
168*
169*
170*
N3
R1
P2
N2
–
M3
P1
N1
M2*
M1*
–
–
–
2
5
8
–
11
14
17
–
–
–
–
I/O
I/O
I/O
25
26
–
25
26
27
33
34
35
C10
A10
A11
140
143
146
DONE
–
–
53
–
–
80
–
–
103
104*
105*
R15
–
–
–
–
–
GND
I/O
I/O
–
–
–
131
132
133
171
172
173
L3
L2
L1
–
20
23
I/O
GND
–
–
–
–
I/O
I/O
–
–
–
–
–
–
27
–
28
29
–
–
30*
31*
32
33
36
37
38*
39*
40*
41*
42
43
B11
C11
–
–
A12*
–
B12
A13
149
–
–
–
–
–
152
155
VCC
–
PROG
I/O (D7)
PGCK3 (I/O)
I/O
–
I/O
54
–
55
56
57
–
–
–
81
–
82
83
84
85
–
86
106
107*
108
109
110
111
–
112
P13
–
R14
T16
T15
R13
–
P12
–
–
–
259
262
265
–
268
I/O (A4)
I/O (A5)
–
–
I/O
I/O
I/O (A6)
I/O (A7)
81
82
–
–
–
–
83
84
134
135
–
136 *
137
138
139
140
174
175
176*
177*
178
179
180
181
K3
K2
–
–
K1
J1
J2
J3
26
29
–
–
32
35
38
41
I/O
–
34
44
A14
158
I/O (D6)
58
87
113
T14
271
GND
1
141
182
H2
–
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 343 = BSCANT.UPD
2-57
This document was created with FrameMaker 4 0 2
XC4000 Logic Cell Array Family
XC4006 Pinouts
PC
Pin
84
Description
PC84
VCC
2
I/O (A8)
3
I/O (A9)
4
I/O
I/O
I/O (A10)
5
I/O (A11)
6
I/O
I/O
GND
I/O
I/O
I/O (A12)
7
I/O (A13)
8
I/O
I/O
I/O (A14)
9
SGCK1 (A15, I/O)
10
VCC
11
GND
12
PGCK1 (A16, I/O)
13
I/O (A17)
14
I/O
I/O
I/O (TDI)
15
I/O (TCK)
16
I/O
I/O
GND
I/O
I/O
I/O (TMS)
17
I/O
18
I/O
I/O
I/O
19
I/O
20
GND
21
VCC
22
PQ
PG
PQ
Boundary
160
156
208
PG156
PQ160
PQ208
Scan Order
H3
142
183
H1
143
184
50
G1
144
185
53
G2
145
186
56
G3
146
187
59
188*
189*
F1
147
190
62
F2
148
191
65
E1
149
192
68
E2
150
193
71
F3
151
194
195*
196*
D1
152
197
74
D2
153
198
77
E3
154
199
80
C1
155
200
83
C2
156
201
86
D3
157
202
89
B1
158
203
92
B2
159
204
95
C3
160
205
206*
207*
208*
1*
C4
1
2
3*
B3
2
4
98
A1
3
5
101
A2
4
6
104
C5
5
7
107
B4
6
8
110
A3
7
9
113
A4
8
10
116
9
11
119
12*
13*
C6
10
14
B5
11
15
122
B6
12
16
125
A5
13
17
128
C7
14
18
131
19*
20*
B7
15
21
134
A6
16
22
137
A7
17
23
140
A8
18
24
143
C8
19
25
B8
20
26
-
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
2-58
Pin
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK2 (I/O)
O M1
(M1)
GND
I (M0)
M0
VCC
I (M2)
M2
PGCK2 (I/O)
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (ERR,INIT)
VCC
PC
84
PC84
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
PQ
PG
Boundary
PQ
208
156
160
PG156
PQ160
PQ208
Scan Order
C9
21
27
146
B9
22
28
149
A9
23
29
152
B10
24
30
155
31*
32*
C10
25
33
158
A10
26
34
161
A11
27
35
164
B11
28
36
167
C11
29
37
38*
39*
A12
30
40
170
31
41
173
B12
32
42
176
A13
33
43
179
A14
34
44
182
C12
35
45
185
B13
36
46
188
B14
37
47
191
A15
38
48
194
C13
39
49
A16
40
50
197†
51*
52*
53*
54*
C14
41
55
B15
42
56
198†
B16
43
57
199
D14
44
58
202
C15
45
59
205
D15
46
60
208
E14
47
61
211
C16
48
62
214
E15
49
63
217
D16
50
64
220
65*
66*
F14
51
67
F15
52
68
223
E16
53
69
226
F16
54
70
229
G14
55
71
232
72*
73*
G15
56
74
235
G16
57
75
238
H16
58
76
241
H15
59
77
244
H14
60
78
-
XC4006 Pinouts (continued)
Pin
Description
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK3 (I/O)
GND
DONE
VCC
PROG
I/O (D7)
PGCK3 (I/O)
I/O
I/O
I/O (D6)
I/O
I/O
I/O
GND
I/O
I/O
I/O (D5)
I/O (CS0)
I/O
I/O
I/O (D4)
I/O
VCC
PC
84
PC84
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
PQ1
PG
PQ
60
156
208
PG156
PQ160
PQ208
J14
61
79
J15
62
80
J16
63
81
K16
64
82
K15
65
83
84*
85*
K14
66
86
L16
67
87
M16
68
88
L15
69
89
L14
70
90
91*
92*
N16
71
93
M15
72
94
P16
73
95
M14
74
96
N15
75
97
P15
76
98
N14
77
99
R16
78
100
P14
79
101
102*
R15
80
103
104*
105*
P13
81
106
107*
R14
82
108
T16
83
109
T15
84
110
R13
85
111
P12
86
112
T14
87
113
T13
88
114
R12
89
115
T12
90
116
117*
118*
P11
91
119
R11
92
120
T11
93
121
T10
94
122
P10
95
123
124*
125*
R10
96
126
T9
97
127
R9
98
128
P9
99
129
R8
100
130
PC
84
PC84
64
65
66
67
68
69
I/O (RCLK-BUSY/RDY)
70
I/O
I/O
I/O (D0, DIN)
71
SGCK4 (DOUT, I/O)
72
CCLK
73
VCC
74
TDO
75
GND
76
I/O (A0, WS)
77
PGCK4 (I/O, A1)
78
I/O
I/O
I/O (CS1,A2)
79
I/O (A3)
80
I/O
I/O
GND
I/O
I/O
I/O (A4)
81
I/O (A5)
82
I/O
I/O
I/O (A6)
83
I/O (A7)
84
GND
1
Boundary
Scan Order
247
250
253
256
259
262
265
268
271
274
277
280
283
286
289
292
295
298
301
304
307
310
313
316
319
322
325
328
331
334
337
340
-
Pin
Description
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O (D2)
I/O
I/O
I/O
GND
I/O
I/O
I/O (D1)
PG
PQ
PQ
156
160
208
PG156
PQ160
PQ208
P8
101
131
T8
102
132
T7
103
133
T6
104
134
R7
105
135
136*
137*
P7
106
138
T5
107
139
R6
108
140
T4
109
141
P6
110
142
143*
144*
R5
111
145
112
146
T3
113
147
P5
114
148
R4
115
149
R3
116
150
P4
117
151
T2
118
152
R2
119
153
P3
120
154
155*
156*
157*
158*
T1
121
159
N3
122
160
R1
123
161
P2
124
162
N2
125
163
M3
126
164
P1
127
165
N1
128
166
M2
129
167
M1
130
168
169*
170*
L3
131
171
L2
132
172
L1
133
173
K3
134
174
K2
135
175
176*
136*
177*
K1
137
178
J1
138
179
J2
139
180
J3
140
181
H2
141
182
* Indicates unconnected package pins.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 391 = BSCAN.UPD
2-59
Boundary
Scan Order
343
346
349
352
355
358
361
364
367
370
373
376
379
382
385
388
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
-
XC4000 Logic Cell Array Family
XC4008 Pinouts
Pin
Description
VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O
I/O
I/O (A10)
I/O (A11)
I/O
I/O
GND
–
–
I/O
I/O
I/O (A12)
I/O (A13)
I/O
–
I/O
I/O (A14)
SGCK1 (A15, I/O)
VCC
–
–
–
–
GND
–
PGCK1 (A16, I/O)
I/O (A17)
I/O
–
I/O
I/O (TDI)
I/O (TCK)
I/O
I/O
–
–
GND
I/O
I/O
I/O (TMS)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
PC
84
PC84
2
3
4
–
–
–
–
5
6
–
–
–
–
–
–
–
7
8
–
–
–
9
10
11
–
–
–
–
12
–
13
14
–
–
–
15
16
–
–
–
–
–
–
–
17
18
–
–
–
–
19
20
21
Boundary
PG
PQ
PQ
191
208
PQ160
PG191
PQ208
Scan Order
160
142
J4
183
–
143
J3
184
56
144
J2
185
59
145
J1
186
62
146
H1
187
65
–
H2
188
68
–
H3
189
71
147
G1
190
74
148
G2
191
77
149
F1
192
80
150
E1
193
83
151
G3
194
–
–
F2*
195*
–
–
D1*
196*
–
152
C1
197
86
153
E2
198
89
154
F3
199
92
155
D2
200
95
156
B1
201
98
–
–
–
–
157
E3
202
101
158
C2
203
104
159
B2
204
107
160
D3
205
–
–
–
206*
–
–
–
207*
–
–
–
208*
–
–
–
1*
–
1
D4
2
–
–
–
3*
–
2
C3
4
110
3
C4
5
113
4
B3
6
116
–
–
–
–
5
C5
7
119
6
A2
8
122
7
B4
9
125
8
C6
10
128
9
A3
11
131
–
B5*
12*
–
–
B6*
13*
–
10
C7
14
–
11
A4
15
134
12
A5
16
137
13
B7
17
140
14
A6
18
143
–
C8
19
146
–
A7
20
149
15
B8
21
152
16
A8
22
155
17
B9
23
158
18
C9
24
161
19
D9
25
–
Pin
Description
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
–
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK2 (I/O)
O M1
(M1)
GND
I M0
(M0)
–
–
–
–
VCC
I M2
(M2)
PGCK2 (I/O)
I/O (HDC)
–
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
–
–
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (ERR, INIT)
VCC
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
2-60
PC
PC84
84
22
23
24
–
–
–
–
25
26
–
–
–
–
–
–
–
27
–
–
–
28
29
30
31
32
–
–
–
–
33
34
35
36
–
–
–
–
37
–
–
–
–
–
–
–
38
39
–
–
–
–
40
41
42
Boundary
PQ
PQ
PG
208
PC160
PG191
PQ208
Scan Order
160
191
20
D10
26
–
21
C10
27
164
22
B10
28
167
23
A9
29
170
24
A10
30
173
–
A11
31
176
–
C11
32
179
25
B11
33
182
26
A12
34
185
27
B12
35
188
28
A13
36
191
29
C12
37
–
–
B13*
38*
–
–
A14*
39*
–
30
A15
40
194
31
C13
41
197
32
B14
42
200
33
A16
43
203
34
B15
44
206
35
C14
45
209
36
A17
46
212
37
B16
47
215
38
C15
48
218
39
D15
49
–
40
A18
50
221†
–
–
51*
–
–
–
52*
–
–
–
53*
–
–
–
54*
–
41
D16
55
–
42
C16
56
222†
43
B17
57
223
44
E16
58
226
–
–
–
–
45
C17
59
229
46
D17
60
232
47
B18
61
235
48
E17
62
238
49
F16
63
241
50
C18
64
244
–
D18*
65*
–
–
F17*
66*
–
51
G16
67
–
52
E18
68
247
53
F18
69
250
54
G17
70
253
55
G18
71
256
–
H16
72
259
–
H17
73
262
56
H18
74
265
57
J18
75
268
58
J17
76
271
59
J16
77
274
60
J15
78
–
XC4008 Pinouts (continued)
Pin
Description
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
–
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK3 (I/O)
GND
–
DONE
–
–
VCC
–
PROG
I/O (D7)
PGCK3 (I/O)
–
I/O
I/O
I/O (D6)
I/O
I/O
I/O
–
–
GND
I/O
I/O
I/O (D5)
I/O (CSO)
I/O
I/O
I/O
I/O
I/O (D4)
I/O
VCC
GND
PC
PC84
84
43
44
45
–
–
–
–
46
47
–
–
–
–
–
–
–
48
49
–
–
50
51
52
–
53
–
–
54
–
55
56
57
–
–
–
58
–
–
–
–
–
–
–
–
59
60
–
–
–
–
61
62
63
64
Boundary
PG
PQ
PQ
PQ160
PG191
PQ208
Scan Order
191
208
160
61
K15
79
–
62
K16
80
277
63
K17
81
280
64
K18
82
283
65
L18
83
286
–
L17
84
289
–
L16
85
292
66
M18
86
295
67
M17
87
298
68
N18
88
301
69
P18
89
304
70
M16
90
–
–
N17*
91*
–
–
R18*
92*
–
71
T18
93
307
72
P17
94
310
73
N16
95
313
74
T17
96
316
75
R17
97
319
76
P16
98
322
77
U18
99
325
78
T16
100
328
79
R16
101
–
–
–
102*
–
80
U17
103
–
–
–
104*
–
–
–
105*
–
81
R15
106
–
–
–
107*
–
82
V18
108
–
83
T15
109
331
84
U16
110
334
–
–
–
–
85
T14
111
337
86
U15
112
340
87
V17
113
343
88
V16
114
346
89
T13
115
349
90
U14
116
352
–
V15*
117*
–
–
V14*
118*
–
91
T12
119
–
92
U13
120
355
93
V13
121
358
94
U12
122
361
95
V12
123
364
–
T11
124
367
–
U11
125
370
96
V11
126
373
97
V10
127
376
98
U10
128
379
99
T10
129
382
100
R10
130
101
R9
131
Pin
PC
Description
PC84
84
I/O (D3)
65
I/O (RS)
66
I/O
–
I/O
–
I/O
–
I/O
–
I/O (D2)
67
I/O
68
I/O
–
I/O
–
GND
–
–
–
–
–
I/O
–
I/O
–
I/O (D1)
69
I/O (RCLK-BUSY/RDY) 70
I/O
–
I/O
–
I/O (D0, DIN)
71
SGCK4 (DOUT, I/O)
72
CCLK
73
VCC
74
–
–
–
–
–
–
–
–
TD0
75
GND
76
I/O (A0, WS)
77
PGCK4 (I/O,A1)
78
–
–
I/O
–
I/O
–
I/O (CS1, A2)
79
I/O (A3)
80
I/O
–
I/O
–
–
–
–
–
GND
–
I/O
–
I/O
–
I/O (A4)
81
I/O (A5)
82
I/O
–
I/O
–
I/O
–
I/O
–
I/O (A6)
83
I/O (A7)
84
GND
1
* Indicates unconnected package pins.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 439 = BSCAN.UPD
2-61
Boundary
PG
PQ
PQ
PQ160
PG191
Scan Order
191 PQ208
208
160
102
T9
132
385
103
U9
133
388
104
V9
134
391
105
V8
135
394
–
U8
136
397
–
T8
137
400
106
V7
138
403
107
U7
139
406
108
V6
140
409
109
U6
141
412
110
T7
142
–
–
V5*
143*
–
–
V4*
144*
–
111
U5
145
415
112
T6
146
418
113
V3
147
421
114
V2
148
424
115
U4
149
427
116
T5
150
430
117
U3
151
433
118
T4
152
436
119
V1
153
–
120
R4
154
–
–
–
155*
–
–
–
156*
–
–
–
157*
–
–
–
158*
–
121
U2
159
–
122
R3
160
–
123
T3
161
2
124
U1
162
5
–
–
–
–
125
P3
163
8
126
R2
164
11
127
T2
165
14
128
N3
166
17
129
P2
167
20
130
T1
168
23
–
R1*
169*
–
–
N2*
170*
–
131
M3
171
–
132
P1
172
26
133
N1
173
29
134
M2
174
32
135
M1
175
35
–
L3
176
38
136
L2
177
41
137
L1
178
44
138
K1
179
47
139
K2
180
50
140
K3
181
53
141
K4
182
–
XC4000 Logic Cell Array Family
XC4010/XC4010D Pinouts
Pin
Description
PC84
VCC
2
I/O (A8)
3
I/O (A9)
4
I/O
I/O
I/O
I/O
I/O (A10)
5
I/O (A11)
6
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O (A12)
7
I/O (A13)
8
I/O
I/O
I/O (A14)
9
SGCK1 (A15, I/O)
10
VCC
11
GND
12
PGCK1 (A16, I/O)
13
I/O (A17)
14
I/O
I/O
I/O (TDI)
15
I/O (TCK)
16
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O (TMS)
17
I/O
18
I/O
I/O
I/O
I/O
I/O
19
I/O
20
GND
21
VCC
22
I/O
23
I/O
24
I/O
-
***
Boundary
††
PQ160 PG191 PQ208 BG225 Scan Order
142
J4
183
D8
143
J3
184
E8
62
144
J2
185
B7
65
145
J1
186
A7
68
146
H1
187
C7
71
H2
188
D7
74
H3
189
E7
77
147
G1
190
A6
80
148
G2
191
B6
83
149
F1
192
A5
86
150
E1
193
B5
89
151
G3
194
**
F2
195
D6
92
D1
196
C5
96
152
C1
197
A4
98
153
E2
198
E6
101
154
F3
199
B4
104
155
D2
200
D5
107
156
B1
201
B3
110
157
E3
202
F6
113
158
C2
203
A2
116
159
B2
204
C3
119
160
D3
205
B2
206*
207*
208*
1*
1
D4
2
A1
3*
2
C3
4
D4
122
3
C4
5
B1
125
4
B3
6
C2
128
5
C5
7
E5
131
6
A2
8
D3
134
7
B4
9
C1
137
8
C6
10
D2
140
9
A3
11
G6
143
B5
12
E4
146
B6
13
D1
149
10
C7
14
**
11
A4
15
F5
152
12
A5
16
E1
155
13
B7
17
F4
158
14
A6
18
F3
161
C8
19
G4
164
A7
20
G3
167
15
B8
21
G2
170
16
A8
22
G1
173
17
B9
23
G5
176
18
C9
24
H3
179
19
D9
25
H2
20
D10
26
H1
21
C10
27
H4
182
22
B10
28
H5
185
23
A9
29
J2
188
Pin
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK2 (I/O)
OM1
(M1)
GND
I M0
(M0)
VCC
I M2
(M2)
PGCK2 (I/O)
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (ERR, INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
*
**
Indicates unconnected package pins.
The following BGA225 balls are connected to ground:
F8, G7, G8, G9, H6, H7, H8, H9, H10, J7, J8, J9, K8
*** The following BG225 balls are unconnected:
E3, E2, F1, F2, J5, K1, L2, K4, P5, L6, N7, P7, R10, P10, M10,
N11, N15, M14, L15, K12, G10, E15, E14, F12, F9, D11, C10,
B10, C6, F7, A3, C4
† Contributes only one bit (.i) to the boundary scan register.
†† XC4010 only. PG191 package not available for XC4010D
2-62
PC84
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
***
Boundary
PQ160 PG191 PQ208 BG225 Scan Order
24
A10
30
J1
191
A11
31
J3
194
C11
32
J4
197
25
B11
33
K2
200
26
A12
34
K3
203
27
B12
35
J6
206
28
A13
36
L1
209
29
C12
37
**
B13
38
L3
212
A14
39
M1
215
30
A15
40
K5
218
31
C13
41
M2
221
32
B14
42
L4
224
33
A16
43
N1
227
34
B15
44
M3
230
35
C14
45
N2
233
36
A17
46
K6
236
37
B16
47
P1
239
38
C15
48
N3
242
39
D15
49
**
40
A18
50
P2
245†
51*
52*
53*
54*
41
D16
55
R1
42
C16
56
M4
246†
43
B17
57
R2
247
44
E16
58
P3
250
45
C17
59
L5
253
46
D17
60
N4
256
47
B18
61
R3
259
48
E17
62
P4
262
49
F16
63
K7
265
50
C18
64
M5
268
D18
65
R4
271
F17
66
N5
274
51
G16
67
**
52
E18
68
R5
277
53
F18
69
M6
280
54
G17
70
N6
283
55
G18
71
P6
286
H16
72
R6
289
H17
73
M7
291
56
H18
74
R7
295
57
J18
75
L7
298
58
J17
76
N8
301
59
J16
77
P8
304
60
J15
78
R8
61
K15
79
M8
62
K16
80
L8
307
63
K17
81
P9
310
64
K18
82
R9
313
65
L18
83
N9
316
L17
84
M9
319
L16
85
L9
322
66
M18
86
N10
325
XC4010/XC4010D Pinouts (continued)
Pin
Description
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK3 (I/O)
GND
DONE
VCC
PROG
I/O (D7)
PGCK3 (I/O)
I/O
I/O
I/O (D6)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O (D5)
I/O (CSO)
I/O
I/O
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O
I/O
I/O (D2)
I/O
I/O
I/O
GND
I/O
††
PC84
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
-
***
PQ160 PG191 PQ208 BG225
67
M17
87
K9
68
N18
88
R11
69
P18
89
P11
70
M16
90
**
N17
91
R12
R18
92
L10
71
T18
93
P12
72
P17
94
M11
73
N16
95
R13
74
T17
96
N12
75
R17
97
P13
76
P16
98
K10
77
U18
99
R14
78
T16
100
N13
79
R16
101
**
102*
80
U17
103
P14
104*
105*
81
R15
106
R15
107*
82
V18
108
M12
83
T15
109
P15
84
U16
110
N14
85
T14
111
L11
86
U15
112
M13
87
V17
113
J10
88
V16
114
L12
89
T13
115
M15
90
U14
116
L13
V15
117
L14
V14
118
K11
91
T12
119
**
92
U13
120
K13
93
V13
121
K14
94
U12
122
K15
95
V12
123
J12
T11
124
J13
U11
125
J14
96
V11
126
J15
97
V10
127
J11
98
U10
128
H13
99
T10
129
H14
100
R10
130
H15
101
R9
131
**
102
T9
132
H12
103
U9
133
H11
104
V9
134
G14
105
V8
135
G15
U8
136
G13
T8
137
G12
106
V7
138
G11
107
U7
139
F15
108
V6
140
F14
109
U6
141
F13
110
T7
142
**
V5
143
E13
Boundary
Scan Order
328
331
334
337
340
343
346
349
352
355
358
361
364
367
370
373
376
379
382
385
388
391
394
397
400
403
406
409
412
415
418
421
424
427
430
433
436
439
442
445
448
451
454
457
Pin
Description
PC84
I/O
I/O
I/O
I/O (D1)
69
I/O (RCLK-BUSY/RDY) 70
I/O
I/O
I/O (D0, DIN)
71
SGCK4 (DOUT, I/O)
72
CCLK
73
VCC
74
TD0
75
GND
76
I/O (A0, WS)
77
PGCK4 (I/O, A1)
78
I/O
I/O
I/O (CS1, A2)
79
I/O (A3)
80
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O (A4)
81
I/O (A5)
82
I/O
I/O
I/O
I/O
I/O (A6)
83
I/O (A7)
84
GND
1
***
Boundary
PQ160 PG191 PQ208 BG225 Scam Order
V4
144
D15
460
111
U5
145
F11
463
112
T6
146
D14
466
113
V3
147
E12
469
114
V2
148
C15
472
115
U4
149
D13
475
116
T5
150
C14
478
117
U3
151
F10
481
118
T4
152
B15
484
119
V1
153
C13
120
R4
154
B14
155*
156*
157*
158*
121
U2
159
A15
122
R3
160
D12
123
T3
161
A14
2
124
U1
162
B13
5
125
P3
163
E11
8
126
R2
164
C12
11
127
T2
165
A13
14
128
N3
166
B12
17
129
P2
167
A12
20
130
T1
168
C11
23
R1
169
B11
26
N2
170
E10
29
131
M3
171
**
132
P1
172
A11
32
133
N1
173
D10
35
134
M2
174
A10
38
135
M1
175
D9
41
L3
176
C9
44
136
L2
177
B9
47
137
L1
178
A9
50
138
K1
179
E9
53
139
K2
180
C8
56
140
K3
181
B8
59
141
K4
182
A8
-
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 487 = BSCAN.UPD
*
**
Indicates unconnected package pins.
The following BGA225 balls are connected to ground:
F8, G7, G8, G9, H6, H7, H8, H9, H10, J7, J8, J9, K8
*** The following BG225 balls are unconnected:
E3, E2, F1, F2, J5, K1, L2, K4, P5, L6, N7, P7, R10, P10, M10,
N11, N15, M14, L15, K12, G10, E15, E14, F12, F9, D11, C10,
B10, C6, F7, A3, C4
†† XC4010 only. PG 191 package not available for XC4010D
2-63
XC4000 Logic Cell Array Family
XC4013/XC4013D Pinouts
Boundary
Pin
Description
PQ160 MQ208 PG223 BG225 PQ240 Scan Order
VCC
142
183
J4
A10
212
74
I/O (A8)
143
184
J3
E8
213
77
I/O (A9)
144
185
J2
F8
214
80
I/O
145
186
J1
B7
215
83
I/O
146
187
H1
A7
216
86
I/O
188
H2
G7
217
89
I/O
189
H3
E7
218
219*
92
I/O (A10)
147
190
G1
F7
220
95
I/O (A11)
148
191
G2
C7
221
VCC
222
98
I/O
H4
B6
223
101
I/O
G4
E6
224
104
I/O
149
192
F1
D7
225
107
I/O
150
193
E1
F6
226
GND
151
194
G3
A5
227
110
I/O
195
F2
B5
228
113
I/O
196
D1
D5
229
116
I/O
152
197
C1
C5
230
119
I/O
153
198
E2
C6
231
122
I/O (A12)
154
199
F3
A4
232
125
I/O (A13)
155
200
D2
D4
233
128
I/O
F4
B4
234
131
I/O
E4
C3
235
134
I/O
156
201
B1
A3
236
137
I/O
157
202
E3
C2
237
140
I/O (A14)
158
203
C2
D6
238
143
SGCK1 (A15, I/O)
159
204
B2
A2
239
VCC
160
205
D3
A6
240
206*
207*
208*
1*
GND
1
2
D4
A1
1
3*
146
PGCK1 (A16,I/O)
2
4
C3
B1
2
149
I/O (A17)
3
5
C4
B3
3
152
I/O
4
6
B3
C4
4
155
I/O
5
7
C5
B2
5
158
I/O (TDI)
6
8
A2
C1
6
161
I/O (TCK)
7
9
B4
E3
7
164
I/O
8
10
C6
D2
8
167
I/O
9
11
A3
D3
9
170
I/O
12
B5
D1
10
173
I/O
13
B6
E5
11
176
I/O
D5
F4
12
179
I/O
D6
E2
13
GND
10
14
C7
E1
14
182
I/O
11
15
A4
E4
15
185
I/O
12
16
A5
F3
16
188
I/O (TMS)
13
17
B7
F2
17
191
I/O
14
18
A6
F5
18
VCC
F1
19
194
I/O
D7
G4
20
197
I/O
D8
G2
21
22*
200
I/O
19
C8
G3
23
203
I/O
20
A7
G6
24
206
I/O
15
21
B8
G5
25
209
I/O
16
22
A8
G1
26
212
I/O
17
23
B9
H5
27
215
I/O
18
24
C9
H7
28
GND
19
25
D9
H1
29
VCC
20
26
D10
H2
30
-
* Indicates unconnected package pins.
† Contributes only one bit (.i) to the boundary scan register.
2-64
Pin
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK2 (I/O)
O (M1)
GND
I (M0)
VCC
I (M2)
PGCK2 (I/O)
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (ERR, INIT)
VCC
Boundary
PQ160 MQ208 PG223 BG225 PQ240 Scan Order
218
21
27
C10
H6
31
221
22
28
B10
H3
32
224
23
29
A9
J6
33
227
24
30
A10
H4
34
230
31
A11
J1
35
233
32
C11
J5
36
37*
236
D11
J2
38
239
D12
J7
39
K1
40
242
25
33
B11
J3
41
245
26
34
A12
K2
42
248
27
35
B12
K5
43
251
28
36
A13
K3
44
29
37
C12
L1
45
254
D13
K6
46
257
D14
L2
47
260
38
B13
J4
48
263
39
A14
M2
49
266
30
40
A15
L5
50
269
31
41
C13
M1
51
272
32
42
B14
H3
52
275
33
43
A16
L3
53
278
34
44
B15
M4
54
281
35
45
C14
N1
55
284
36
46
A17
N2
56
287
37
47
B16
K4
57
290
38
48
C15
L4
58
39
49
D15
41
59
293†
40
50
A18
P1
60
51*
52*
53*
54*
41
55
D16
R6
61
294†
42
56
C16
R2
62
295
43
57
B17
P3
63
298
44
58
E16
M6
64
301
45
59
C17
P2
65
304
46
60
D17
R3
66
307
47
61
B18
N3
67
310
48
62
E17
N5
68
313
49
63
F16
N4
69
316
50
64
C18
R4
70
319
65
D18
P4
71
322
66
F17
N6
72
325
E15
P5
73
328
F15
M5
74
51
67
G16
R5
75
331
52
68
E18
M7
76
334
53
69
F18
P6
77
337
54
70
G17
L6
78
340
55
71
G18
N7
79
80
343
72
H16
P7
81
346
73
H17
M8
82
83*
349
G15
K7
84
352
H15
L7
85
355
56
74
H18
R7
86
358
57
75
J18
N8
87
361
58
76
J17
J8
88
364
59
77
J16
P8
89
60
78
J15
R10
90
-
XC4013/XC4013D Pinouts (continued)
Pin
Description
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK3 (I/O)
GND
DONE
VCC
PROG
I/O (D7)
PGCK3 (I/O)
I/O
I/O
I/O
I/O
I/O (D6)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O (D5)
I/O (CSO)
I/O
I/O
I/O
I/O
I/O (D4)
I/O
VCC
Boundary
PQ160 MQ208 PG223 BG225 PQ240 Scan Order
61
79
K15
R8
91
367
62
80
K16
L8
92
370
63
81
K17
M9
93
373
64
82
K18
P9
94
376
65
83
L18
R9
95
379
84
L17
K8
96
382
85
L16
L9
97
98*
385
L15
K9
99
388
M15
N9
100
101
391
66
86
M18
P10
102
394
67
87
M17
L10
103
397
68
88
N18
N10
104
400
69
89
P18
K10
105
70
90
M16
R11
106
403
N15
N11
107
406
P15
P11
108
409
91
N17
M10
109
412
92
R18
P12
110
415
71
93
T18
R12
111
418
72
94
P17
N12
112
421
73
95
N16
K12
113
424
74
96
T17
P13
114
427
75
97
R17
R13
115
430
76
98
P16
P14
116
433
77
99
U18
K13
117
0
78
100
T16
M13
118
79
101
R16
R15
119
102*
80
103
U17
R14
120
104*
105*
81
106
R15
K15
121
107*
82
108
V18
P15
122
439
83
109
T15
N14
123
442
84
110
U16
L13
124
445
85
111
T14
N13
125
448
86
112
U15
N15
126
451
R14
M11
127
454
R13
M14
128
457
87
113
V17
M12
129
460
88
114
V16
M15
130
463
89
115
T13
L11
131
466
90
116
U14
J12
132
469
117
V15
L14
133
472
118
V14
L12
134
91
119
T12
L15
135
475
R12
J13
136
478
R11
K14
137
481
92
120
U13
K11
138
484
93
121
V13
H11
139
140
487
94
122
U12
J14
141
490
95
123
V12
H12
142
143*
493
124
T11
J10
144
496
125
U11
J11
145
499
96
126
V11
J15
146
502
97
127
V10
H13
147
505
98
128
U10
J9
148
508
99
129
T10
H9
149
100
130
R10
H14
150
-
Boundary
Pin
Description
PQ160 MQ208 PG223 BG225 PQ240 Scan Order
GND
101
131
R9
H15
151
511
I/O (D3)
102
132
T9
H10
152
514
I/O (RS)
103
133
U9
G12
153
517
I/O
104
134
V9
G14
154
520
I/O
105
135
V8
G15
155
523
I/O
136
U8
G9
156
526
I/O
137
T8
G11
157
158*
529
I/O (D2)
106
138
V7
G10
159
532
I/O
107
139
U7
G13
160
VCC
161
535
I/O
108
140
V6
F14
162
538
I/O
109
141
U6
F11
163
541
I/O
R8
F13
164
544
I/O
R7
F10
165
GND
110
142
T7
E15
166
547
I/O
R6
E14
167
550
I/O
R5
F12
168
553
I/O
143
V5
D14
169
556
I/O
144
V4
E12
170
559
I/O
111
145
U5
D15
171
562
I/O
112
146
T6
D13
172
565
I/O (D1)
113
147
V3
E13
173
568
I/O (RCLK-BUSY/RDY) 114
148
V2
C13
174
571
I/O
115
149
U4
C15
175
574
I/O
116
150
T5
C14
176
577
I/O (D0, DIN)
117
151
U3
D10
177
580
SGCK4 (DOUT, I/O)
118
152
T4
C11
178
CCLK
119
153
V1
B15
179
VCC
120
154
R4
F15
180
155*
156*
157*
158*
TD0
121
159
U2
A14
181
GND
122
160
R3
A15
182
2
I/O (A0, WS)
123
161
T3
C12
183
5
PGCK4 (I/O, A1)
124
162
U1
C10
184
8
I/O
125
163
P3
B14
185
11
I/O
126
164
R2
A13
186
14
I/O (CS1, A2)
127
165
T2
B13
187
17
I/O (A3)
128
166
N3
B12
188
20
I/O
P4
D12
189
23
I/O
N4
A12
190
26
I/O
129
167
P2
E11
191
29
I/O
130
168
T1
D9
192
32
I/O
169
R1
B11
193
35
I/O
170
N2
D11
194
195*
GND
131
171
M3
A11
196
38
I/O
132
172
P1
C9
197
41
I/O
133
173
N1
B10
198
44
I/O
M4
E10
199
47
I/O
L4
D8
200
VCC
201
50
I/O (A4)
134
174
M2
B9
202
53
I/O (A5)
135
175
M1
C8
203
204*
56
I/O
176
L3
F9
205
59
I/O
136
177
L2
E9
206
62
I/O
137
178
L1
A9
207
65
I/O
138
179
K1
B8
208
68
I/O (A6)
139
180
K2
H8
209
71
I/O (A7)
140
181
K3
G8
210
GND
141
182
K4
A8
211
-
* Indicates unconnected package pins.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 583 = BSCAN.UPD
2-65
XC4000 Logic Cell Array Family
XC4020 Pinouts
Pin
Bound
Description
HQ208 HQ240 PG233 PG299 Scan
VCC
183
212
J4
K1
I/O (A8)
184
213
J3
K2
86
I/O (A9)
185
214
J2
K3
89
I/O
186
215
J1
K5
92
I/O
187
216
H1
K4
95
I/O
188
217
H2
J1
98
I/O
189
218
H3
J2
101
I/O (A10)
190
220
G1
H1
104
I/O (A11)
191
221
G2
J3
107
I/O
H2
110
I/O
G1
113
VCC
222
E1
I/O
223
H4
H3
116
I/O
224
G4
G2
119
I/O
192
225
F1
H4
122
I/O
193
226
E1
F2
125
GND
194
227
G3
F1
I/O
195
228
F2
D1
128
I/O
196
229
D1
G4
131
I/O
197
230
C1
E2
134
I/O
198
231
E2
F3
137
I/O (A12)
199
232
F3
G5
140
I/O (A13)
200
233
D2
C1
143
I/O
F4
146
I/O
E3
149
I/O
234
F4
D2
152
I/O
235
E4
C2
155
I/O
201
236
B1
F5
158
I/O
202
237
E3
E4
161
I/O (A14)
203
238
C2
D3
164
SGCK1(A15,I/O)
204
239
B2
C3
167
VCC
205
240
D3
A2
GND
2
1
D4
B1
PGCK1 (A16,I/O)
4
2
C3
D4
170
I/O (A17)
5
3
C4
B2
173
I/O
6
4
B3
B3
176
I/O
7
5
C5
E6
179
I/O (TDI)
8
6
A2
D5
182
I/O (TCK)
9
7
B4
C4
185
I/O
A3
188
I/O
D6
191
I/O
10
8
C6
E7
194
I/O
11
9
A3
B4
197
I/O
12
10
B5
C5
200
I/O
13
11
B6
A4
203
I/O
12
D5
D7
206
I/O
13
D6
C6
209
GND
14
14
C7
A5
I/O
15
15
A4
B6
212
I/O
16
16
A5
D8
215
I/O (TMS)
17
17
B7
C7
218
I/O
18
18
A6
B7
221
VCC
19
A6
I/O
20
D7
C8
224
I/O
21
D8
E9
227
I/O
B8
230
I/O
A8
233
I/O
19
23
C8
C9
236
I/O
20
24
A7
B9
239
I/O
21
25
B8
E10
242
I/O
22
26
A8
A9
245
I/O
23
27
B9
D10
248
I/O
24
28
C9
C10
251
GND
25
29
D9
A10
VCC
26
30
D10
A11
I/O
27
31
C10
B10
254
I/O
28
32
B10
B11
257
I/O
29
33
A9
C11
260
I/O
30
34
A10
E11
263
I/O
31
35
A11
D11
266
I/O
32
36
C11
A12
269
I/O
B12
272
I/O
A13
275
I/O
38
D11
E12
278
I/O
39
D12
B13
281
VCC
40
A16
I/O
33
41
B11
A14
284
Pin
Description
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SCGK2 (I/O)
O (M1)
GND
I (M0)
VCC
I (M2)
PGCK2 (I/O)
I/O (HDC)
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (ERR, INIT)
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
Bound
HQ208 HQ240 PG233 PG299 Scan
34
42
A12
C13
287
35
43
B12
B14
290
36
44
A13
D13
293
37
45
C12
A15
46
D13
C14
296
47
D14
A17
299
38
48
B13
D14
302
39
49
A14
B16
305
40
50
A15
C15
308
41
51
C13
E14
311
A18
314
D15
317
42
52
B14
C16
320
43
53
A16
B17
323
44
54
B15
B18
326
45
55
C14
E15
329
46
56
A17
D16
332
47
57
B16
C17
335
48
58
C15
A20
338
49
59
D15
A19
50
60
A18
C18
341
55
61
D16
B20
56
62
C16
D17
342
57
63
B17
B19
343
58
64
E16
C19
346
59
65
C17
F16
349
60
66
D17
E17
352
61
67
B18
D18
355
62
68
E17
C20
358
F17
361
G16
364
63
69
F16
D19
367
64
70
C18
E18
370
65
71
D18
D20
373
66
72
F17
G17
376
73
E15
F18
379
74
F15
H16
382
67
75
G16
E20
68
76
E18
H17
385
69
77
F18
G18
388
70
78
G17
G19
391
71
79
G18
H18
394
80
F20
72
81
H16
J16
397
73
82
H17
G20
400
H20
403
J18
406
84
G15
J19
409
85
H15
K16
412
74
86
H18
J20
415
75
87
J18
K17
418
76
88
J17
K18
421
77
89
J16
K19
424
78
90
J15
L20
79
91
K15
K20
80
92
K16
L19
427
81
93
K17
L18
430
82
94
K18
L16
433
83
95
L18
L17
436
84
96
L17
M20
439
85
97
L16
M19
442
N20
445
M18
448
99
L15
N19
451
100
M15
P20
454
101
T20
86
102
M18
N18
457
87
103
M17
P19
460
88
104
N18
N17
463
89
105
P18
R19
466
90
106
M16
R20
107
N15
U20
469
108
P15
P17
472
91
109
N17
T19
475
92
110
R18
R18
478
93
111
T18
P16
481
94
112
P17
V20
484
† Contributes only one bit (.i) to the boundary scan register.
2-66
Pin
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK3 (I/O)
GND
DONE
VCC
PROG
I/O (D7)
PGCK3 (I/O)
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D6)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O (D5)
I/O (CS0)
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D4)
I/O
VCC
GND
I/O (D3)
I/O (RS)
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D2)
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O (D1)
HQ208 HQ240 PG233
95
113
N16
96
114
T17
97
115
R17
98
116
P16
99
117
U18
100
118
T16
101
119
R16
103
120
U17
106
121
R15
108
122
V18
109
123
T15
110
124
U16
111
125
T14
112
126
U15
127
R14
128
R13
113
129
V17
114
130
V16
115
131
T13
116
132
U14
117
133
V15
118
134
V14
119
135
T12
136
R12
137
R11
120
138
U13
121
139
V13
140
122
141
U12
123
142
V12
124
144
T11
125
145
U11
126
146
V11
127
147
V10
128
148
U10
129
149
T10
130
150
R10
131
151
R9
132
152
T9
133
153
U9
134
154
V9
135
155
V8
136
156
U8
137
157
T8
138
159
V7
139
160
U7
161
140
162
V6
141
163
U6
164
R8
165
R7
142
166
T7
167
R6
168
R5
143
169
V5
144
170
V4
145
171
U5
146
172
T6
147
173
V3
I/O (RCLK-BUSY/RDY) 148
174
V2
I/O
I/O
I/O
149
175
U4
I/O
150
176
T5
I/O (D0, DIN)
151
177
U3
SGCK4 (DOUT, I/O) 152
178
T4
CCLK
153
179
V1
VCC
154
180
R4
TDO
159
181
U2
Bound
PG299 Scan
R17
487
T18
490
U19
493
V19
496
R16
499
T17
502
U18
505
X20
508
W20
V18
X19
U17
W19
511
W18
514
T15
517
U16
520
V17
523
X18
526
U15
529
T14
532
W17
535
V16
538
X17
541
U14
544
V15
547
T13
550
X16
U13
553
V14
556
W14
559
V13
562
X15
T12
565
X14
568
X13
571
V12
574
W12
577
T11
580
X12
583
U11
586
V11
589
W11
592
X10
X11
W10
595
V10
598
T10
601
U10
604
X9
607
W9
610
X8
613
V9
616
W8
619
X7
622
X5
V8
625
W7
628
U8
631
W6
634
X6
X4
637
U7
640
W5
643
V6
646
T7
X3
649
U6
652
V5
655
W4
658
W3
661
T6
664
U5
667
V4
670
X1
673
V3
W1
U4
-
XC4020 Pinouts (continued)
Pin
Bound
Description
HQ208 HQ240 PG233 PG299 Scan
GND
160
182
R3
X2
I/O (A0, WS)
161
183
T3
W2
2
PGCK4 (I/O, A1) 162
184
U1
V2
5
I/O
163
185
P3
R5
8
I/O
164
186
R2
T4
11
I/O (CS1, A2)
165
187
T2
U3
14
I/O (A3)
166
188
N3
V1
17
I/O
R4
20
I/O
P5
23
I/O
189
P4
U2
26
I/O
190
N4
T3
29
Pin
Description
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
Bound
HQ208 HQ240 PG233 PG299 Scan
167
191
P2
U1
32
168
192
T1
P4
35
169
193
R1
R3
38
170
194
N2
N5
41
171
196
M3
T1
172
197
P1
N4
44
173
198
N1
P3
47
199
M4
P2
50
200
L4
N3
53
201
R1
M5
56
Pin
Description
I/O
I/O (A4)
I/O (A5)
I/O
I/O
I/O
I/O
I/O (A6)
I/O (A7)
GND
Bound
HQ208 HQ240 PG233 PG299 Scan
P1
59
174
202
M2
N1
62
175
203
M1
M3
65
176
205
L3
M2
68
177
206
L2
L5
71
178
207
L1
M1
74
179
208
K1
L4
77
180
209
K2
L3
80
181
210
K3
L2
83
182
211
K4
L1
-
XC4025 Pinouts
Pin
Description
VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O
I/O
GND
I/O (A10)
I/O (A11)
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)
I/O
I/O
I/O
I/O
I/O
I/O
I/O (A14)
SGCK1 (A15, I/O)
VCC
GND
PGCK1 (A16, I/O)
VCC
I/O (A17)
I/O
I/O
I/O (TDI)
I/O (TCK)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O (TMS)
I/O
PG
223
J4
J3
J2
J1
H1
H2
H3
G1
G2
H4
G4
F1
E1
G3
F2
D1
C1
E2
F3
D2
F4
E4
B1
E3
C2
B2
D3
D4
C3
C4
B3
C5
A2
B4
C6
A3
B5
B6
D5
D6
C7
A4
A5
B7
A6
MQ
240
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PG
299
K1
K2
K3
K5
K4
J1
J2
H1
J3
J4
J5
H2
G1
E1
H3
G2
H4
F2
F1
H5
G3
D1
G4
E2
F3
G5
C1
F4
E3
D2
C2
F5
E4
D3
C3
A2
B1
D4
E5
B2
B3
E6
D5
C4
A3
D6
E7
B4
C5
A4
D7
C6
E8
B5
A5
B6
D8
C7
B7
HQ
304
38
37
36
35
34
33
32
31
30
29
28
27
26
25
23
22
21
20
19
18
17
16
15
14
13
12
10
9
8
7
6
5
4
3
2
1
304
303
302
301
300
299
298
297
296
295
294
293
292
291
290
289
288
287
286
285
284
283
Bound
Pin
PG MQ
Scan Description 223 240
VCC
19
98
I/O
D7 2 0
101
I/O
D8 2 1
104
GND
22
107
I/O
110
I/O
113
I/O
I/O
116
I/O
C8 2 3
119
I/O
A7 2 4
122
I/O
B8 2 5
125
I/O
A8 2 6
128
I/O
B9 2 7
131
I/O
C9 2 8
GND
D9 2 9
134
VCC
D10 3 0
137
I/O
C10 3 1
140
I/O
B10 3 2
143
I/O
A9 3 3
I/O
A10 3 4
146
I/O
A11 3 5
149
I/O
C11 3 6
152
I/O
155
I/O
158
I/O
161
I/O
164
GND
37
167
I/O
D11 3 8
170
I/O
D12 3 9
173
VCC
40
176
I/O
B11 4 1
179
I/O
A12 4 2
182
I/O
B12 4 3
185
I/O
A13 4 4
188
GND
C12 4 5
191
I/O
I/O
I/O
D13 4 6
194
I/O
D14 4 7
I/O
B13 4 8
197
I/O
A14 4 9
200
I/O
A15 5 0
203
I/O
C13 5 1
206
I/O
209
I/O
212
I/O
B14 5 2
215
I/O
A16 5 3
218
I/O
B15 5 4
221
I/O
C14 5 5
224
I/O
A17 5 6
2 2 7 SCGK2 (I/O) B 1 6 5 7
230
O (M1)
C15 5 8
233
GND
D15 5 9
236
I (M0)
A18 6 0
239
VCC
D16 6 1
I (M2)
C16 6 2
2 4 2 PGCK2 (I/O) B 1 7 6 3
245
I/O (HDC) E16 6 4
248
GND
251
I/O
C17 6 5
PG
299
A6
C8
E9
A7
D9
B8
A8
C9
B9
E10
A9
D10
C10
A10
A11
B10
B11
C11
E11
D11
A12
B12
A13
C12
D12
E12
B13
A16
A14
C13
B14
D13
A15
B15
E13
C14
A17
D14
B16
C15
E14
A18
D15
C16
B17
B18
E15
D16
C17
A20
A19
C18
B20
D17
B19
C19
E16
F16
HQ
304
280
279
278
277
276
275
274
273
272
271
270
269
268
267
266
265
264
263
262
261
260
259
258
257
256
255
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
Bound
Pin
Scan
Description
I/O
254
I/O
257
I/O (LDC)
I/O
260
I/O
263
I/O
266
I/O
269
I/O
272
I/O
275
I/O
278
I/O
281
I/O
284
I/O
287
GND
I/O
I/O
290
I/O
293
I/O
296
VCC
299
I/O
302
I/O
305
GND
308
I/O
311
I/O
314
I/O
317
I/O
I/O
320
I/O
323
I/O
I/O
326
I/O
3 2 9 I/O (ERR, INIT)
332
VCC
335
GND
I/O
338
I/O
341
I/O
344
I/O
347
I/O
350
I/O
353
I/O
356
I/O
359
I/O
362
I/O
365
GND
368
I/O
371
I/O
374
VCC
377
I/O
380
I/O
383
I/O
386
I/O
GND
389†
I/O
I/O
390†
I/O
391
I/O
394
I/O
I/O
397
I/O
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 775 = BSCAN.UPD
2-67
PG MQ PG HQ Bound
Pin
PG MQ PG HQ Bound
223 240 299 304 Scan Description 223 240 299 304 Scan
D17 6 6 E17 2 2 3 4 0 0
I/O
P 1 7 1 1 2 V20 1 6 3 5 5 6
B 1 8 6 7 D18 2 2 2 4 0 3
I/O
- R17 1 6 2 5 5 9
E17 6 8 C20 2 2 1 4 0 6
I/O
T 18 1 6 1 5 6 2
F17 2 2 0 4 0 9
I/O
N16 1 1 3 U19 1 6 0 5 6 5
G16 2 1 9 4 1 2
I/O
T 1 7 1 1 4 V19 1 5 9 5 6 8
F 1 6 6 9 D19 2 1 8 4 1 5
I/O
R17 1 1 5 R16 1 5 8 5 7 1
C18 7 0 E18 2 1 7 4 1 8
I/O
P 1 6 1 1 6 T17 1 5 7 5 7 4
D18 7 1 D20 2 1 6 4 2 1
I/O
U18 1 1 7 U18 1 5 6 5 7 7
F1 7 7 2 G17 2 1 5 4 2 4 SGCK3 (I/O) T 1 6 1 1 8 X20 1 5 5 5 8 0
E15 7 3 F1 8 2 1 4 4 2 7
VCC
R16 T 16 1 5 4
F 1 5 7 4 H16 2 1 3 4 3 0
GND
- 1 1 9 W20 E19 2 1 2 4 3 3
DONE
U17 1 2 0 V18 1 5 3
F19 2 1 1 4 3 6
VCC
R15 1 2 1 X19 1 5 2
G16 7 5 E20 2 1 0
PROG
V18 1 2 2 U17 1 5 1
E18 7 6 H17 2 0 9 4 3 9
I/O (D7)
T15 1 2 3 W19 1 5 0 5 8 3
F1 8 7 7 G18 2 0 8 4 4 2 PGCK3 (I/O) U16 1 2 4 W 1 8 1 4 9 5 8 6
G17 7 8 G19 2 0 7 4 4 5
I/O
T 1 4 1 2 5 T15 1 4 8 5 8 9
G18 7 9 H18 2 0 6 4 4 8
I/O
U15 1 2 6 U16 1 4 7 5 9 2
8 0 F20 2 0 4
I/O
R14 1 2 7 V17 1 4 6 5 9 5
H16 8 1 J 1 6 2 0 3 4 5 1
I/O
R13 1 2 8 X18 1 4 5 5 9 8
H17 8 2 G20 2 0 2 4 5 4
I/O
- U15 1 4 4 6 0 1
83 I/O
T14 1 4 3 6 0 4
J17 201 457
I/O (D6)
V17 1 2 9 W 1 7 1 4 2 6 0 7
- H19 2 0 0 4 6 0
I/O
V16 1 3 0 V16 1 4 1 6 1 0
- H20 1 9 9 4 6 3
I/O
T 1 3 1 3 1 X17 1 4 0 6 1 3
J18 198 466
I/O
U14 1 3 2 U14 1 3 9 6 1 6
G15 8 4 J 1 9 1 9 7 4 6 9
I/O
V15 1 3 3 V15 1 3 8 6 1 9
H15 8 5 K 1 6 1 9 6 4 7 2
I/O
V14 1 3 4 T 13 1 3 7 6 2 2
H18 8 6 J 2 0 1 9 5 4 7 5
I/O
- W16 1 3 6 6 2 5
J18 8 7 K17 1 9 4 4 7 8
I/O
- W15 1 3 5 6 2 8
J17 8 8 K18 1 9 3 4 8 1
GND
T 1 2 1 3 5 X16 1 3 4
J16 8 9 K19 1 9 2 4 8 4
I/O
R12 1 3 6 U13 1 3 3 6 3 1
J15 9 0 L20 1 9 1
I/O
R11 1 3 7 V14 1 3 2 6 3 4
K15 9 1 K20 1 9 0
I/O
U13 1 3 8 W 1 4 1 3 1 6 3 7
K16 9 2 L19 1 8 9 4 8 7
I/O
V13 1 3 9 V13 1 3 0 6 4 0
K17 9 3 L18 1 8 8 4 9 0
VCC
- 1 4 0 X15 K18 9 4 L16 1 8 8 4 9 3
I/O (D5)
U12 1 4 1 T12 1 2 7 6 4 3
L18 9 5 L17 1 8 7 4 9 6
I/O (CS0)
V12 1 4 2 X14 1 2 6 6 4 6
L17 9 6 M20 1 8 5 4 9 9
GND
- 143 L16 9 7 M19 1 8 4 5 0 2
I/O
- U12 1 2 5 6 4 9
- N20 1 8 3 5 0 5
I/O
- W13 1 2 4 6 5 2
- M18 1 8 2 5 0 8
I/O
X13 1 2 3 6 5 5
- M17 1 8 1 5 1 1
I/O
V12 1 2 2 6 5 8
- M16 1 8 0 5 1 4
I/O
T11 1 4 4 W12 1 2 1 6 6 1
L15 9 8 - 1 7 9
I/O
U11 1 4 5 T11 1 2 0 6 6 4
M 1 5 9 9 N19 1 7 8 5 1 7
I/O
V11 1 4 6 X12 1 1 9 6 6 7
- 100 520
I/O
V10 1 4 7 U11 1 1 8 6 7 0
- 1 0 1 T20 1 7 7
I/O (D4)
U10 1 4 8 V11 1 1 7 6 7 3
M 1 8 1 0 2 N18 1 7 5 5 2 3
I/O
T10 1 4 9 W11 1 1 6 6 7 6
M17 1 0 3 P19 1 7 4 5 2 6
VCC
R10 1 5 0 X10 1 1 5
N18 1 0 4 N17 1 7 3 5 2 9
GND
R9 1 5 1 X11 1 1 4
P 1 8 1 0 5 R19 1 7 2 5 3 2
I/O (D3)
T9 1 5 2 W 1 0 1 1 3 6 7 9
M 1 6 1 0 6 R20 1 7 1
I/O (RS)
U9 1 5 3 V10 1 1 2 6 8 2
- N16 1 7 0 5 3 5
I/O
V9 1 5 4 T 10 1 1 1 6 8 5
- P18 1 6 9 5 3 8
I/O
V8 1 5 5 U10 1 1 0 6 8 8
N15 1 0 7 U20 1 6 8 5 4 1
I/O
U8 1 5 6 X9 1 0 9 6 9 1
P15 1 0 8 P17 1 6 7 5 4 4
I/O
T8 1 5 7 W 9 1 0 8 6 9 4
N17 1 0 9 T 1 9 1 6 6 5 4 7
I/O
X8 1 0 7 6 9 7
R18 1 1 0 R18 1 6 5 5 5 0
I/O
V9 1 0 6 7 0 0
T18 1 1 1 P16 1 6 4 5 5 3
I/O
U9 1 0 5 7 0 3
XC4000 Logic Cell Array Family
XC4025 Pinouts (continued)
Pin
Description
I/O
GND
I/O (D2)
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PG
223
V7
U7
V6
U6
R8
R7
T7
R6
R5
V5
V4
U5
MQ
240
158
159
160
161
162
163
164
165
166
167
168
169
170
171
PG
299
T9
W8
X7
X5
V8
W7
U8
W6
X6
T8
V7
X4
U7
W5
V6
T7
HQ Bound
Pin
304 Scan
Description
104 706
I/O
I/O (D1)
1 0 3 7 0 9 I/O (RCLK-BUSY/RDY)
102 712
I/O
I/O
9 9 715
I/O
9 8 718
I/O
9 7 721
I/O (D0, DIN)
9 6 724
SGCK4 (DOUT, I/O)
95
CCLK
9 4 727
GND
9 3 730
VCC
9 2 733
TDO
9 1 736
GND
9 0 739
I/O (A0, WS)
8 9 742
PGCK4 (I/O, A1)
88
I/O
PG
223
T6
V3
V2
U4
T5
U3
T4
V1
R4
U2
R3
T3
U1
P3
MQ
240
172
173
174
175
176
177
178
179
180
181
182
183
184
185
PG
299
X3
U6
V5
W4
W3
T6
U5
V4
X1
V3
T5
W1
U4
X2
W2
V2
R5
HQ Bound
304 Scan
87
745
86
748
85
751
84
754
83
757
82
760
81
763
80
766
79
769
78
77
76
75
74
2
73
5
72
8
Pin
Description
I/O
I/O (CS1, A2)
I/O (A3)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
PG
223
R2
T2
N3
P4
N4
P2
T1
R1
N2
M3
P1
N1
M4
MQ
240
186
187
188
189
190
191
192
193
194
195
196
197
198
199
PG
299
T4
U3
V1
R4
P5
U2
T3
U1
P4
R3
N5
T2
R2
T1
N4
P3
P2
HQ
304
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
Bound
Scan
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
Pin
Description
I/O
VCC
I/O
I/O
I/O
I/O
I/O (A4)
I/O (A5)
GND
I/O
I/O
I/O
I/O
I/O (A6)
I/O (A7)
GND
PG
223
L4
M2
M3
L3
L2
L1
K1
K2
K3
K4
MQ
PG
240
299
2 0 0 N3
2 0 1 R1
M5
P1
M4
N2
2 0 2 N1
203 M3
204
205 M2
206
L5
207 M1
208
L4
209
L3
210
L2
211
L1
HQ Bound
304 Scan
54
59
52
51
62
50
65
49
68
48
71
47
74
46
77
45
80
44
83
43
86
42
89
41
92
40
95
39
-
For a detailed description of the device architecture, see pages 2-9 through 2-31.
For a detailed description of the configuration modes and their timing, see pages 2-32 through 2-55.
For detailed lists of package pinouts, see pages 2-57 through 2-67.
For package physical dimensions and thermal data, see Section 4.
Ordering Information
XC4010-5PG191C
Example:
Device Type
Temperature Range
Speed Grade
Number of Pins
Package Type
Component Availability
PINS
84
TYPE
PLAST.
PLCC
XC4005
XC4006
XC4008
XC4010
XC4010D
XC4013
XC4013D
XC4020
XC4025
120
144
TOP
PLAST. BRAZED CERAM. PLAST.
VQFP
CQFP
PGA
TQFP
156
160
164
191
196
208
TOP
TOP
CERAM PLAST. BRAZED CERAM. BRAZED PLAST.
PGA
PQFP
CQFP
PGA
CQFP
PQFP
223
225
METAL CERAM. PLAST.
PQFP
PGA
BGA
240
PLAST.
PQFP
299
304
METAL CERAM. CERAM.
PQFP
PGA
PGA
PC84 PQ100 VQ100 CB100 PG120 TQ144 PG156 PQ160 CB164 PG191 CB196 PQ208 MQ208 PG223 BG225 PQ240 MQ240 PG299 HQ304
CODE
XC4003
100
PLAST.
PQFP
-6
-5
-4
-10
-6
-5
-4
-6
-5
-4
-6
-5
-4
-10
-6
-5
-4
-6
-5
-4
-6
-5
-4
-6
-5
-4
-6
-5
-4
-6
-5
-4
CI
CI
CI
C
C
C
C
C
C
CI
CI
CIMB
CI
CI
CI
CI
CI
C
C
MB
MB
MB
CI
CI
C
C
C
CI
CI
CI
CI
CI
CI
CI
CI
C
C
C
C
CI
CI
CI
CI
CI
CI
CI
C
CI
CI
C
C
C
C
C
MB
MB
MB
CI
CI
CIMB
CI
CI
CI
C
CI
CI
CI
CI
CI
CI
C
C
C
C
CI
CI
CI
CI
CI
CI
CI
CI
C
C
C
CI
CI
CI
C I (M B)
CI
CI
CI
CI
CI
CI
CI
CI
CI
CI
C
C
C
C
C
C
C
CI
CI
CI
CI
CI
CI
CI
CI
C
C
C
C
(C I)
(C I)
(C I)
(C I)
(C I)
(C I)
(C I)
(C)
(C)
I = Industrial = -40° to +100° C
M = Mil Temp = -55° to +125° C
Parentheses indicates future product plans
2-68
C
(C I)
(C)
C = Commercial = 0° to +85° C
B = MIL-STD-883C Class B
C
(C)
CI
CI
CI
C
CI
CI
CI
C