ZARLINK MT90401AB

MT90401
SONET/SDH System Synchronizer
Data Sheet
Features
January 2005
•
Meets requirements of GR-253-CORE for SONET
Stratum 3 and SONET minimum clock
•
Meets requirements of GR-1244-CORE Stratum 3
•
Meets requirements of G.813 Option 1 and Option
2 for SDH Equipment Clocks (SEC) with external
jitter attenuator
Ordering Information
MT90401AB
80 Pin LQFP
MT90401AB1 80 Pin LQFP*
*Pb Free Matte Tin
Trays
Trays
-40°C to +85°C
•
Provides OC-3/STM-1, DS3, E3, 19.44 MHz,
DS2, E1, T1, 8 kHz and ST-BUS clock outputs
Applications
•
Accepts reference inputs from two independent
sources
•
SONET/SDH Add/Drop multiplexers
•
SONET/SDH uplinks
•
Selectable 1.544 MHz, 2.048 MHz, 19.44 MHz or
8kHz input reference frequencies
•
Integrated access devices
•
Holdover accuracy of 0.02 ppm
•
ATM edge switches
•
Adjustable output clock phase supporting masterslave arrangements
Description
•
Hardware or microprocessor control (8 bit
microprocessor interface)
•
3.3 V supply
•
JTAG boundary scan
The MT90401 is a digital phase locked loop (DPLL)
that is designed to synchronize SDH (Synchronous
Digital Hierarchy) and SONET (Synchronous Optical
Network) networking equipment. The MT90401 is used
to ensure that the timing of outgoing signals remains
within the limits specified by Telcordia, ANSI and the
ITU during normal operation and in the presence of
disturbances on the incoming synchronization signals.
LOCK
TCLR
C20i
TCK
TDI
TMS
TRST
TDO
PRI
SEC
Prioor
Secoor
RSEL
Master Clock
TIE
Corrector
Circuit
IEEE
1149.1a
Reference
Select
MUX
Reference
Monitor
Reference
Select
VSS
Virtual
Reference
DPLL
Output
Interface
Circuit
Selected
Reference
TIE
Corrector
Enable
VDD
State
Select
Input
Impairment
Monitor
State
Select
Feedback
Frequency
Select
MUX
Control State Machine
RST MS1 MS2 HOLDOVER PCCi FLOCK D0/D7 A0/A6 CS,DS,R/W
FS1
FS2
Figure 1 - Functional Block Diagram
1
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Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
C155P/N
C19o
C1.5o
C2o
C4o
C6o
C8o
C16o
C44/C34
F0o
F8o
F16o
MT90401
Data Sheet
The MT90401 can operate in free-run, locked or holdover mode. The loop filter corner frequency can be selected to
suit SONET applications or to suit SDH applications. The MT90401 uses an external 20 MHz oscillator as its
master clock and it does not require external loop filter components.
IC
DS
FLOCK
LOCK
PCCi
HOLDOVER
VDD4
C34/C44
VSS7
C20i
NC
VDD3
TCLR
RSEL
C19o
VSS5
IC
C6o
C1.5o
PRIOOR
In Hardware Mode, the MT90401 can be controlled and monitored via external pins. In Microport Mode, a
microprocessor can be used for more comprehensive control and monitoring.
60
58
56
54
52
50
48
46
44
62
42 40
38
64
36
66
34
68
32
70
MT90401AB
30
72
28
74
26
76
24
78
4
6
8
10
12
14
16
18
20
MS2
F8o
2
MS1
22
80
IC
A1
A2
A3
A4
VSS9
A5
A6
SONET/SDH
VDD1
VSS1
F16o
C16o
C8o
C4o
C2o
F0o
SECOOR
OE
CS
RST
HW
D0
D1
D2
D3
VSS8
IC
IC
VDD5
D4
D5
D6
D7
R/W
A0
IC
FS1
FS2
Tdi
Trst
Tclk
Tms
Tdo
VREF
VSS4
C155P
C155N
VDD
VDD2
VSS3
IC
VSS2
PRI
SEC
E3/DS3
E3DS3/OC3
Figure 2 - Pin Connections 80 Pin LQFP for MT90401
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Zarlink Semiconductor Inc.
MT90401
Data Sheet
Pin Description
Pin #
Name
1
IC
2-5
A1 - A4
6
VSS9
7, 8
A5, A6
9
Description
Internal Connection. Leave unconnected.
Address 1 to 4 (5 V tolerant Inputs). Address inputs for the parallel processor interface.
Digital ground. 0 Volts
Address 5, to 6 (5 V tolerant Input). Address inputs for the parallel processor interface.
SONET/SD SONET/SDH (Input). In hardware mode set this pin high to have a loop filter corner
H
frequency of 70 millihertz and limit the phase slope to 885 ns per second. Set this pin low to
have a corner frequency of approximately 1.1 hertz and limit the phase slope to 53 ns per
1.326 ms. This pin performs no function if the device is not in hardware mode.
10
VDD1
Positive Power Supply. Digital supply.
11
VSS1
Digital ground. 0 Volts
12
F16o
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for STBUS operation at 8.192 Mb/s.
13
C16o
Clock 16.384 MHz (CMOS Output). This output is used for ST-BUS operation with a
16.384 MHz clock.
14
C8o
Clock 8.192 MHz (CMOS Output). This output is used for ST-BUS operation at
8.192 Mb/s.
15
C4o
Clock 4.096 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s
and 4.096 Mb/s.
16
C2o
Clock 2.048 MHz (CMOS Output). This output is used for ST-BUS operation at
2.048 Mb/s.
17
F0o
Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output). This is an 8 kHz 244 ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for STBUS operation at 2.048 Mb/s and 4.096 Mb/s.
18
MS1
Mode/Control Select 1 (Input). This input, together with MS2, determines the state
(Normal, Holdover, or Freerun) of operation. See Table 3 on page 15. The logic level at this
input is gated in by the rising edge of F8o. This pin performs no function if the device is not
in hardware mode.
19
MS2
Mode/Control Select 2 (Input). This input, together with MS1, determines the state
(Normal, Holdover or Freerun) of operation. See Table 3 on page 15. The logic level at this
input is gated in by the rising edge of F8o. This pin performs no function if the device is not
in hardware mode.
20
F8o
Frame Pulse Generic (CMOS Output). This is an 8 kHz 122 ns active high framing pulse,
which marks the beginning of a TDM frame. This is typically used for TDM streams
operating at 8.192 Mb/s.
21
E3DS3/OC3 E3DS3 or OC-3 Selection (Input). In Hardware Mode a low on this pin enables the
differential 155.52 MHz output clock on the C155N/C155P pins; this will also cause the
C34/C44 pin to output its nominal clock frequency divided by 4. In Hardware Mode, a high
on this pin disables the differential 155.52 MHz output clock on the C155N/C155P pins; this
will also cause the C34/C44 pin to output its nominal clock frequency. This pin performs no
function if the device is not in Hardware Mode.
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Zarlink Semiconductor Inc.
MT90401
Data Sheet
Pin Description (continued)
Pin #
Name
Description
22
E3/DS3
E3 or DS3 Selection (Input). In Hardware Mode a low on this pin selects a clock rate of
44.736 MHz for the C34/C44 pin, while a high selects a clock rate of 34.368 MHz. This pin
performs no function if the device is not in hardware mode.
23
SEC
Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources
(falling edge) used for synchronization. One of four possible frequencies ( 8kHz,
1.544 MHz, 2.048 MHz or 19.44 MHz) may be used. In hardware mode the selection of the
input reference is based upon the MS1, MS2 and RSEL control inputs.
24
PRI
Primary Reference (Input). This is one of two (PRI & SEC) input reference sources
(falling edge) used for synchronization. One of four possible frequencies (8 kHz,
1.544 MHz, 2.048 MHz or 19.44 MHz) may be used. In hardware mode the selection of the
input reference is based upon the MS1, MS2 and RSEL control inputs.
25
VSS2
Digital ground. 0 Volts
26
IC
27
VSS3
Analog ground. 0 Volts
28
VDD2
Positive Analog Power Supply. Analog supply.
29
VDD
Positive Power Supply. Digital supply.
30
31
C155N,
C155P
32
VSS4
Digital ground. 0 Volts
33
VREF
LVDS Reference Voltage (Input).
34
Tdo
IEEE 1149.1a Test Data Output (Output). If not used, this pin should be left unconnected.
35
Tms
IEEE 1149.1a Test Mode Selection (Input). If not used, this pin should be pulled high.
36
Tclk
IEEE 1149.1a Test Clock Signal (Input). If not used, this pin should be pulled high.
37
Trst
IEEE 1149.1a Reset Signal (Input). If not used, this pin should be held low.
38
Tdi
IEEE 1149.1a Test Data Input (Input). If not used, this pin should be pulled high.
39
FS2
Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four
possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI
and SEC inputs. For more details see FS2 bit description in Table 6 - Control Register 1
(Address 00H - Read/Write).
40
FS1
Frequency Select 1 (Input). This input, in conjunction with FS2, selects which of four
possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI
and SEC inputs. For more details see FS1 bit description in Table 6 - Control Register 1
(Address 00H - Read/Write).
41
PRIOOR
Primary Reference Out Of Range (CMOS Output). A logic high at this pin indicates that
the primary reference is off the PLL center frequency by more than 12 ppm. The
measurement is done on a 1 second basis using a signal derived from the 20 MHz clock
input on C20i. When the accuracy of the 20 MHz clock is ± 4.6 ppm, the effective out of
range limits of the PRIOOR signal will be +16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm.
42
C1.5o
43
C6
Clock 6.312 MHz (CMOS Output). This output is used for DS2 or J2 applications.
44
IC
Internal Connection. Tie low for normal operation.
Internal Connection. Leave unconnected
LVDS 155.52 MHz (Output)). Differential outputs generating a 155.52 MHz clock
Clock 1.544 MHz (CMOS Output). This output is used in T1 applications.
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Zarlink Semiconductor Inc.
MT90401
Data Sheet
Pin Description (continued)
Pin #
Name
Description
45
VSS5
Digital ground. 0 Volts
46
C19o
Clock 19.44 MHz (CMOS Output). This output is used in OC-N and STM-N applications.
47
RSEL
Reference Source Select (Input). A logic low selects the PRI (primary) reference source
as the input reference signal and a logic high selects the SEC (secondary) input. The logic
level at this input is gated in by the rising edge of F8o. For more details see RSEL bit
description in Table 6 - Control Register 1 (Address 00H - Read/Write).
48
TCLR
TIE Circuit Clear (Input). A logic low at this input clears the Time Interval Error (TIE)
correction circuit resulting in a realignment of output phase with input phase. The TCLR pin
should be held low for a minimum of 300 ns. When this pin is held low, the time interval error
correction circuit is disabled.
49
VDD3
Positive Power Supply. Digital supply.
50
NC
51
C20i
20 MHz Clock Input (5 V tolerant Input). This pin is the input for the master 20 MHz clock.
52
VSS7
Digital ground. 0Volts
53
C34/C44
No Connection.
Controlled Clock 34.368 MHz / Clock 44.736 MHz (CMOS Output). This output clock is
programmable to be either 34.368 MHz (for E3 applications) or 44.736 MHz (for DS3
applications). The output clock is controlled via control pins in Hardware Mode or control
bits when the device is in Microport Mode.
If the E3DS3/OC3 control pin or control bit is high, the C34/C44 pin will output its nominal
frequency. If the E3DS3/OC3 control pin or bit is low, the C34/C44 pin will output its nominal
frequency divided by 4. (C8.5o/C11o)
54
55
VDD4
Positive Power Supply. Digital supply.
HOLDOVER Holdover (CMOS Output). This output goes high when the device is in holdover mode.
56
PCCi
Phase Continuity Control Input (3 V Input). The signal at this pin affects the state
changes between Primary Holdover Mode and Primary Normal Mode and Primary Holdover
Mode and Secondary Normal Mode. The logic level at this input is gated by the rising edge
of F8o. See Figure 12, “Control State Diagram” on page 21 for details.
57
LOCK
Lock Indicator (CMOS Output). This output goes high when the PLL is in frequency lock
to the input reference.
58
FLOCK
Fast Lock Mode (Input). In hardware mode, hold this pin high to lock faster than normal to
the input reference. This pin performs no function if the device is not in hardware mode. In
Fast Lock Mode, the wander generation of the PLL is, of necessity, compromised.
59
DS
Data Strobe (5 V tolerant Input). This input is the active low data strobe of the Motorola
processor interface.
60
IC
Internal Connection. Tie low for normal operation.
61
SECOOR
Secondary Reference Out Of Capture Range (CMOS Output). A logic high at this pin
indicates that the secondary reference is off the PLL center frequency by more than 12
ppm. The measurement is done on a 1 second basis using a signal derived from the
20 MHz clock input on the C20i pin. When the accuracy of the 20 MHz clock is ± 4.6 ppm
the effective out of range limits of the SECOOR signal will be +16.6 ppm to -7.4 ppm or
+7.4 ppm to -16.6 ppm.
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Zarlink Semiconductor Inc.
MT90401
Data Sheet
Pin Description (continued)
Pin #
Name
Description
62
OE
Output Enable (Input). Tie high for normal operation. Tie low to force output clocks pins
F16, F8, C16, C8, C4, C2 to a high impedance state.
63
CS
Chip Select (5 V tolerant Input). This active low input enables the non-multiplexed
Motorola parallel microprocessor interface of the MT90401. When CS is set to high, the
microprocessor interface is idle and all bus I/O pins will be in a high impedance state.
64
RST
RESET (5 V tolerant Input). This active low input puts the MT90401 in a reset condition.
RST should be set to high for normal operation. The MT90401 should be reset after powerup and after the selected reference frequency is changed. The RST pin must be held low for
a minimum of 1msec. to reset the device properly.
65
HW
Hardware Mode (Input). If this pin is tied low, the device is in microport mode and is
controlled via the microport. If it is tied high, the device is in hardware mode and is
controlled via the control pins MS1, MS2, FS1, FS2, FLOCK and SONET/SDH.
66-69
D0 - D3
Data 0 to Data 3 (5 V tolerant Three-state I/O). These signals combined with D4-D7 form
the bidirectional data bus of the parallel processor interface (D0 is the least significant bit).
70
VSS8
71
IC
Internal Connection. Tie low for normal operation.
72
IC
Internal Connection. Tie low for normal operation.
73
VDD5
74-77
D4 - D7
Data 4 to Data 7 (5 V tolerant Three-state I/O). These signals combined with D0-D3 form
the bidirectional data bus of the parallel processor interface (D7 is the most significant bit).
78
R/W
Read/Write Select (5 V tolerant Input). This input controls the direction of the data bus
D[0:7] during a microprocessor access. When R/W is high, the parallel processor is reading
data from the MT90401. When low, the parallel processor is writing data to the MT90401.
79
A0
Address 0 (5 V tolerant Input). Address input for the parallel processor interface. A0 is the
least significant input.
80
IC
Internal Connection. Tie low for normal operation.
Digital ground. 0 Volts.
Positive Power Supply. Digital supply.
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Zarlink Semiconductor Inc.
MT90401
Data Sheet
Table of Contents
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 Reference Select MUX Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Frequency Select MUX Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Time Interval Error (TIE) Corrector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Digital Phase Lock Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5 Output Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 Input Impairment Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.7 State Machine Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.8 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.0 Control and Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 Freerun Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 Fast Lock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 Transitions from Freerun Mode or Holdover Mode to Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.0 MT90401 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Jitter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Frequency Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Holdover Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6 Capture Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7 Lock Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.8 Phase Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9 Frequency Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10 Time Interval Error (TIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.13 Phase Lock Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.0 MT90401 and Network Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 TIE Correction (using PCCi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 C155 clock generation and LVDS output drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4 Microport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.5 Output Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Zarlink Semiconductor Inc.
MT90401
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections 80 Pin LQFP for MT90401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3 - TIE Corrector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4 - DPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5 - Output Interface Circuit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6 - Control State Machine Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7 - Jitter Tolerance GR-1244 1.544 MHz Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8 - Jitter Tolerance ITU-T G.813 Option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9 - Jitter Tolerance SONET Category II (OC1) 19.44 MHz Input Reference. . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10 - Jitter and Wander Transfer with SONET filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11 - Jitter and Wander Transfer with SDH Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12 - Control State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13 - LVDS Voltage Offset Vos Generation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 15 - Microport Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16 - Input to Output Timing for T1/E1 signals (Normal Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17 - Input to Output Timing for 19.44 MHz Signal (Normal Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18 - Output Timing 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19 - Output Timing 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20 - Input Controls Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 21 - Output Timing 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Zarlink Semiconductor Inc.
MT90401
Data Sheet
List of Tables
Table 1 - Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2 - Input Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3 - Operating Modes and States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4 - Control State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6 - Control Register 1 (Address 00H - Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7 - Status Register 1 (Address 01H - Read Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8 - Control Register 2 (Address 04H - Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9 - Set Delay Word 2 (Address 06H - Read/Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10 - Set Delay Word 1 (Address 07H - Read/Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11 - Identification Word (Address 0FH - Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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Zarlink Semiconductor Inc.
MT90401
1.0
Data Sheet
Functional Description
The MT90401 is a SONET/SDH System Synchronizer, providing timing (clock) and synchronization (frame) signals
to interface circuits for Digital Telecommunications Transmission links. Figure 1 is a functional block diagram which
is described in the following sections.
1.1
Reference Select MUX Circuit
The MT90401 accepts two simultaneous reference input signals and operates on their falling edges. Either the
primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE
Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1
and Table 4.
1.2
Frequency Select MUX Circuit
The MT90401 operates with one of four possible input reference frequencies (8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz). The frequency select inputs, FS1 and FS2, which come from pins in hardware mode and control bits in
microport mode determine which of the four frequencies may be used at the reference inputs (PRI and SEC). Both
inputs must have the same frequency applied to them. A reset (RST) must be performed after every frequency
select input change. See Table 1 - Input Frequency Selection.
FS2
FS1
0
0
Input Frequency
19.44 MHz
See FS2 and FS1 bit description
in Table 6 - Control Register 1
(Address 00H - Read/Write)
0
1
8 kHz
1
0
1.544 MHz
1
1
2.048 MHz
Table 1 - Frequency Selection
1.3
Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or
SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.
During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary
reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL
would lead to unacceptable phase changes in the output signal.
As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the
signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is
input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference. During a switch
from one reference to the other, the State Machine first changes the mode of the device from Normal to Holdover. In
Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an accurate clock signal using
storage techniques. The Compare Circuit then measures the phase delay between the current phase (feedback
signal) and the phase of the new reference signal. This delay value is passed to the Programmable Delay Circuit
(See Figure 3). The new virtual reference signal is now at the same phase position as the previous reference signal
would have been if the reference switch had not taken place. The State Machine then returns the device to Normal
Mode.
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Zarlink Semiconductor Inc.
MT90401
Data Sheet
TCLR
Resets Delay
Control Signal
Control
Circuit
Delay Value
PRI or SEC
from Reference
Select Mux
Virtual
Reference to
DPLL
Programmable
Delay Circuit
Compare
Circuit
TIE Corrector
Enable
from
State Machine
Feedback
Signal from
Frequency
Select MUX
Figure 3 - TIE Corrector Circuit
The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL,
no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change
at the input of the DPLL, or at the output of the DPLL.
Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual
reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL.
This phase error is a function of the difference in phase between the two input reference signals during reference
rearrangements. Each time a reference switch is made, the delay between input signal and output signal will
change. The value of this delay is the accumulation of the error measured during each reference switch.
The programmable delay circuit can be reset to zero by applying a logic low pulse to the TIE Circuit Clear (TCLR)
pin. A minimum reset pulse width is 300 ns. This results in a phase realignment between the input reference signal
and the output signal as shown in Figure 16. The speed of the phase alignment correction is limited to 885 ns/s in
SONET mode and 53 ns per 1.326 ms in SDH mode, convergence is in the direction of least phase travel.
The state diagram of Figure 12 indicates the state changes for which the TIE Corrector Circuit is activated.
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Zarlink Semiconductor Inc.
MT90401
1.4
Data Sheet
Digital Phase Lock Loop (DPLL)
As shown in Figure 4, the DPLL of the MT90401 consists of a Phase Detector, Phase Slope Limiter, Loop Filter,
Digitally Controlled Oscillator, and a Control Circuit.
Virtual Reference
from
TIE Corrector
Phase
Detector
Feedback Signal
from
Frequency Select MUX
Phase Slope
Limiter
Loop Filter
Digitally
Controlled
Oscillator
State Select
from
Input Impairment Monitor
DPLL Reference
to
Output Interface Circuit
Control
Circuit
State Select
from
State Machine
Figure 4 - DPLL Block Diagram
Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the
feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase
difference between the two. This error signal is passed to the Phase Slope Limiter circuit. The Frequency Select
MUX allows the proper feedback signal to be externally selected (e.g., 8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz).
Phase Slope Limiter - the Phase Slope Limiter receives the error signal from the Phase Detector and ensures that
the DPLL responds to all input transient conditions with a limited output phase slope. In SONET Mode the
maximum output phase slope is limited to 885 ns/s as per Telcordia GR-253-CORE. In SDH Mode the maximum
output phase slope is 53 ns per 1.326 ms.
Loop Filter - the Loop Filter is a low pass filter, that defines the network jitter and wander transfer requirements for
all input reference frequencies (8 kHz, 1.544 MHz, 2.048 MHz, or 19.44 MHz). In SONET mode the loop filter has a
cut-off frequency of 70 mHz to comply with Telcordia GR-253-CORE and GR-1244-CORE. In SDH mode the loop
filter has a cut-off frequency of 1.1Hz to comply with ITU-T G.813 Option 1 and GR-1244-CORE.
Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input
Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the MT90401.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover Mode, the DCO is free running at a frequency equal to the last locked frequency the DCO was
generating while in Normal Mode. In order to improve accuracy of the Holdover Mode the actual frequency sample
is taken 30 to 60 ms before switching into holdover.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the C20i 20 MHz source.
Telcordia GR-253-CORE requires that, during recovery from holdover, SONET clocks not change their output
frequency at a rate faster than 2.9 ppm per second. In SONET Mode the MT90401 limits the rate of change of its
output frequency (frequency slope) to less than 1.9ppm per second; this limit remains in place when the PLL is in
Fast Lock Mode.
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Zarlink Semiconductor Inc.
MT90401
Data Sheet
Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical
to the line frequency), and the input phase offset is small enough such that no phase slope limiting is exhibited, then
the lock signal will be set high.
1.5
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure
5. The Output Interface Circuit uses five Tapped Delay Lines in MT90401 followed by a T1 Divider Circuit, an E1
Divider Circuit, a DS2 Divider Circuit, and a x4/x8 PLL, to generate the required output signals.
Five tapped delay lines are used to generate 8.592 MHz, 11.184 MHz, 16.384 MHz, 12.352 MHz, 12.624 MHz and
19.44 MHz signals.
The E1 Divider Circuit uses the 16.384 MHz signal to generate four clock outputs and three frame pulse outputs.
The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.
These outputs have a nominal 50% duty cycle. The frame pulse outputs (F0o, F8o, and F16o) are generated
directly from the C16 clock.
The T1 Divider Circuit uses the 12.352 MHz signal to generate C1.5o. This output has a nominal 50% duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal
50% duty cycle.
The 19.44 MHz signal is output on the C19o pin and it is multiplied by an internal PLL to generate the 155.52 MHz
clock output on the C155P/N pins. The C155P/N clock has a nominal 50% duty cycle.
The 8.592 MHz and 11.184 MHz signals are multiplied by an internal PLL to generate the 34.368 MHz or
44.736 MHz clock output on the C34/C44 pin. If the internal PLL is dedicated to the C155P/N clock then the
C34/C44 pin will output the 8.592 MHz or 11.184 MHz clocks. The 34.368 Mhz and 44.736 MHz clocks have a
nominal 50% duty cycle. The duty cycles of the 8.592 MHz and 11.184 MHz signals are dependent on the duty
cycle of the 20 MHz clock input to the C20i pin.
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Zarlink Semiconductor Inc.
MT90401
12MHz
T1 Divider
Data Sheet
C1.5o
Tapped
Delay
Line
From
DPLL
Tapped
Delay
Line
16MHz
Tapped
Delay
Line
12MHz
Tapped
Delay
Line
E1 Divider
DS2 Divider
19MHz
C6o
C19o
x4 / x8 PLL
Tapped
Delay
Line
C2o
C4o
C8o
C16o
F0o
F8o
F16o
8.5/11.2MHz
C155P/N
C34/C44
Figure 5 - Output Interface Circuit Block Diagram
The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulses and clock
outputs are locked to one another for all operating states, and are also locked to the selected input reference in
Normal Mode. See Figure 18.
All frame pulses and clock outputs have limited driving capability, and should be buffered when driving capacitive
loads exceeding 30 pF.
1.6
Input Impairment Monitor
This circuit monitors the input signal to the DPLL and automatically enables the Auto-Holdover when the frequency
of the incoming signal is outside the Auto-Holdover capture range. (See Performance Characteristics - Mode
Switching). This includes a complete loss of incoming signal, or a large frequency shift in the incoming signal. When
the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output signal locked to the
input signal. The holdover output signal in the MT90401 is based on the incoming signal 30 ms (minimum) to 60 ms
prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible because the Holdover
Mode is very accurate (i.e., 0.02 ppm). Consequently, the phase delay between the input and output after switching
back to Normal Mode is preserved.
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Zarlink Semiconductor Inc.
MT90401
1.7
Data Sheet
State Machine Control
An internal state machine can be enabled to control the TIE Corrector Circuit as shown in Figure 1. In hardware
mode, control is based on the logic levels at the control inputs RSEL, MS1, MS2 and PCCi (See Figure 6). In
Microport mode, control is based on the state of control bits RSEL, MS1 and MS2 and the PCCi pin. When
switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when PCCi = 1, and
disabled when PCCi = 0.
All state machine changes occur synchronously on the rising edge of F8o. See the Control and Mode of Operation
section for full details.
To
Reference
Select MUX
To DPLL
State
Select
To TIE
Corrector
Enable
Control
State Machine
RSEL
PCCi
MS2
MS1
Figure 6 - Control State Machine Block Diagram
1.8
Master Clock
The MT90401 uses an external oscillator as the master timing source. For recommended master timing circuits,
see the Applications - Master Clock section.
2.0
Control and Mode of Operation
The MT90401 has three possible modes of operation, Normal, Holdover and Freerun.
In hardware mode the Mode/Control Select pins MS2 and MS1 select the mode and method of control as shown in
Table 3.
RSEL
Input Reference
0
PRI
1
SEC
Table 2 - Input Reference Selection
MS2
MS1
Mode
0
0
NORMAL
0
1
HOLDOVER
1
0
FREERUN
1
1
Reserved
Table 3 - Operating Modes and States
The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2. Refer to Table 4 and
Figure 12 for details of the state change sequences.
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Zarlink Semiconductor Inc.
MT90401
2.1
Data Sheet
Normal Mode
Normal Mode is typically used when a slave clock source, synchronized to the network is required.
In Normal Mode, the MT90401 provides timing and frame synchronization signals, which are synchronized to one
of two reference inputs (PRI or SEC). The input reference signal may have a nominal frequency of 8 kHz,
1.544 MHz, 2.048 MHz or 19.44 MHz.
The selection of input references is control dependent as shown in state table 4. The reference frequencies are
selected by the frequency control pins/bits FS2 and FS1 as shown in Table 1.
2.2
Holdover Mode
Holdover Mode is typically used when network synchronization is temporarily disrupted.
In Holdover Mode, the MT90401 provides timing and synchronization signals, which are not locked to an external
reference signal, but are based on storage techniques. The storage value is determined while the device is in
Normal Mode and locked to an external reference signal
When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the MT90401
output reference frequency is stored alternately in two memory locations every 30 ms. When the device is switched
into Holdover Mode, the value in memory from between 30 ms and 60 ms is used to set the output frequency of the
device.
The frequency accuracy of Holdover Mode is ±0.02 ppm, which translates to a worst case 14 frame (125 us) slips
in 24 hours. This is better than the Telcordia GR-1244-CORE Stratum 3 requirement of ±0.37 ppm (255 frame slips
per 24 hours).
Two factors affect the accuracy of Holdover Mode. One is drift on the Master Clock and the other is jitter on the
reference signal. The drift on the Master Clock oscillator propagates unattenuated and causes the same drift on the
output clocks. This drift can only be reduced by selecting more stable Master Clock oscillator. For example, a
±4.6 ppm temperature compensated clock oscillator may have a temperature coefficient of 0.03 ppm per degree C.
The 10 degC change while in Holdover Mode, will result in an additional offset in frequency accuracy equal to
0.3ppm which is much greater than the internal holdover accuracy of the MT90401 (0.02 ppm).
The other factor affecting accuracy is large jitter on the reference input prior (30 ms to 60 ms) to the mode switch.
For instance, jitter of 7.5 UI at 700 Hz may reduce the Holdover Mode accuracy from 0.02 ppm to 0.10 ppm.
2.3
Freerun Mode
Freerun Mode is typically used when a master clock source is required, or immediately following system power-up
before network synchronization is achieved. In Freerun Mode, the MT90401 provides timing and synchronization
signals which are based on the master clock frequency (C20i) only, and are not synchronized to the reference
signals (PRI and SEC).
The accuracy of the output clock is equal to the accuracy of the master clock (C20i). So if a ±20 ppm output clock is
required, the master clock must also be ±20 ppm. See Applications - Master Clock section.
2.4
Fast Lock Mode
Fast Lock Mode is a submode of Normal Mode, it is used to allow the MT90401 to lock to a reference eight times
more quickly than normal. Fast Lock Mode necessarily compromises the wander generation characteristics of the
MT90401. When the MT90401 is in Fast Lock Mode and SONET Mode at the same time, the PLL frequency slope
is limited to less than 1.9 ppm per second.
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Zarlink Semiconductor Inc.
MT90401
2.5
Data Sheet
Transitions from Freerun Mode or Holdover Mode to Normal Mode
Telcordia GR-253-CORE requires SONET Internal Clocks to settle within 100 s after transitioning from Freerun
Mode or Holdover Mode to Normal Mode. During such a transition, the wander filtering requirements for a SONET
Internal Clock are relaxed to make a 100 s settling time possible.
To meet the GR-253-CORE 100 s settling time requirement at power-up and during a transition from Freerun Mode
to Normal Mode the MT90401 should be placed in its SDH Mode until lock is achieved. When the PLL indicates
lock the MT90401 should be placed in SONET Mode.
During a transition from Holdover Mode to Normal Mode, GR-253-CORE requires a SONET Internal Clock to limit
the frequency slope to less than 2.9 ppm per second. To meet the 100 s settling time during such a transition it is
necessary to keep the MT90401 in SONET Mode and Fast Lock Mode until lock is achieved. When the PLL
indicates lock the MT90401 can be taken out of its Fast Lock Mode.
A transition from Holdover Mode to Normal Mode can result in a large initial frequency offset, for example 4.6 ppm,
between the clock’s reference and its output. The 2.9 ppm per second frequency slope limit required by
GR-253-CORE places a lower limit on the time it takes for a SONET Internal Clock to acquire a new frequency.
While the clock is acquiring the new frequency a phase error will accumulate which could cause the clock’s settling
time to be longer than 100 s. GR-1244-CORE and GR-253-CORE allow a clock to ignore some of the phase error
accumulated during the transition from Holdover Mode to Normal Mode.
During a transition from Holdover Mode to Normal Mode, if the MT90401 has not achieved lock within 16 seconds,
it is recommended that the PLL be put briefly into its Holdover Mode and then returned to Normal Mode by toggling
the MS1 pin or the MS1 control bit. Toggling the PLL into and out of Holdover will clear any accumulated phase
error and reduce the settling time.
3.0
MT90401 Measures of Performance
The following are some synchronizer performance indicators and their corresponding definitions.
3.1
Jitter Generation
Jitter generation is the amount of jitter produced by a PLL and is measured at its output. It is measured by applying
a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter generation may also
be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the
output jitter of the device. Jitter generation is usually measured with various band-limiting filters depending on the
applicable standards.
3.2
Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the
presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied
jitter magnitude and jitter frequency depends on the applicable standards (see Figures 7, 8 and 9).
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Zarlink Semiconductor Inc.
MT90401
Data Sheet
Figure 7 - Jitter Tolerance GR-1244 1.544 MHz Reference
Figure 8 - Jitter Tolerance ITU-T G.813 Option 1
Figure 9 - Jitter Tolerance SONET Category II (OC1) 19.44 MHz Input Reference
3.3
Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
For the MT90401, two internal elements determine the jitter attenuation. This includes the low pass loop filter and
the phase slope limiter. Both of these parameters have different settings depending on whether the device is in
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Zarlink Semiconductor Inc.
MT90401
Data Sheet
SONET or SDH mode. For SONET mode the loop filter has a corner frequency of 70 millihertz and the output
phase slope is limited to 885 ns per second. For SDH mode the loop filter has a corner frequency of 1.1 Hertz and
a maximum phase slope of 53 ns per 1.326 milliseconds. If the input signal exceeds this rate, such as for very large
amplitude low frequency input jitter, the maximum output phase slope will be limited.
The MT90401 has ten outputs that can be locked to four possible input frequencies for a total of 40 possible jitter
transfer functions. Since all outputs are derived from the same internal signal, the jitter transfer values for the four
cases, 8 kHz to 8 kHz, 1.544 MHz to 1.544 MHz, 2.048 MHz to 2.048 MHz 19.44 MHz to 19.44 MHz can be applied
to all outputs.
Figure 10 - Jitter and Wander Transfer with SONET filter
Figure 11 - Jitter and Wander Transfer with SDH Filter
It should be noted that 1 UI at 1.544 MHz is 648 ns, which is not equal to 1 UI at 2.048 MHz, which is 488 ns.
Consequently, a transfer value using different input and output frequencies must be calculated in common units
(e.g., seconds) as shown in the following example.
Example: What is the T1 and E1 output jitter when the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter
attenuation is 18 dB?
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Zarlink Semiconductor Inc.
MT90401
OutputT1 = InputT1 ×10
OutputT1 = 20 ×10
18-
 –------- 20 
Data Sheet
A
 –----- 20 
= 2.5UI ( T1 )
( 1UIT1 )
OutputE1 = OutputT1 × ---------------------( 1UIE1 )
( 644ns )
OutputE1 = OutputT1 × ------------------- = 3.3UI ( T1 )
( 488ns )
Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on
the four jitter transfer functions provided.
Since intrinsic jitter generation is always present, jitter attenuation will appear to be lower for small input jitter
signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with
large input jitter signals (e.g., 75% of the specified maximum jitter tolerance).
Description
State
Input Controls
Freerun
Normal
(PRI)
Normal
(SEC)
Holdover
(PRI)
Holdover
(SEC)
MS2
MS1
RSEL
PCCi
S0
S1
S2
S1H
S2H
0
0
0
0
S1
-
S1 MTIE
S1
S1 MTIE
0
0
0
1
S1
-
S1 MTIE
S1 MTIE
S1 MTIE
0
0
1
X
S2
S2 MTIE
-
S2 MTIE
S2 MTIE
0
1
0
X
/
S1H
/
0
1
1
X
/
S2H
S2H
/
-
1
0
X
X
-
S0
S0
S0
S0
Legend:
No Change
/
Not Valid
MTIE
State change occurs with TIE Corrector Circuit
Refer to Control State Diagram for state changes to and from Auto-Holdover State
Table 4 - Control State Table
20
Zarlink Semiconductor Inc.
/
MT90401
Data Sheet
S0
Freerun
(10X)
PCCi-0
PCCi-1
S1
Normal
Primary
(000)
{A
(PCCi=0)
(PCCi=1)
S1A
Auto-Holdover
Primary
S2A
Auto-Holdover
Secondary
S1H
Holdover
Primary
(010)
S2H
Holdover
Secondary
(011)
NOTES:
(XXX)
MS2 MS1 RSEL
{A}
Invalid Reference Signal
Movement to Normal State from any state requires a valid input signal
Phase Re-Alignment
{A}
S2
Normal
Secondary
(001)
In the case where 19.44 MHz input reference clocks are
selected (FS2,FS1 = 00) the MT90401 may latch
inaccurate phase reading during transition between
states: S1A>>S1 and S2A>>S2 which may cause
frequency step exceeding ±4.6 ppm and longer than 100
sec lock time.
Phase Continuity Maintained (without TIE Corrector Circuit)
Phase Continuity Maintained (with TIE Corrector Circuit)
Figure 12 - Control State Diagram
3.4
Frequency Accuracy
Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an
external reference, but is operating in a free running mode. For the MT90401, the Freerun accuracy is equal to the
Master Clock (C20i) accuracy.
3.5
Holdover Accuracy
Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external
reference signal, but is operating using storage techniques. For the MT90401, the storage value is determined
while the device is in Normal Mode and locked to an external reference signal. The initial frequency offset of the
MT90401 in Holdover Mode is +20 x 10-9. This is more accurate than Telcordia’s GR-1244-CORE stratum 3
requirements of +50 x 10-9. Once the MT90401 has transitioned into Holdover Mode, holdover stability is
determined by the stability of the 20 MHz Master Clock Oscillator.
The absolute Master Clock (C20i) accuracy of the MT90401 does not affect Holdover accuracy, but the change in
C20i accuracy while in Holdover Mode does.
21
Zarlink Semiconductor Inc.
MT90401
3.6
Data Sheet
Capture Range
Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull
into synchronization. The MT90401 capture range is equal to ±52 ppm minus the accuracy of the master clock
(C20i). For example, a ±32 ppm master clock results in a capture range of ±20 ppm.
MT90401 provides two pins and two bits, PRIOOR and SECOOR, to indicate whether the primary and secondary
reference are within the 12 ppm of the nominal frequency. When the accuracy of the 20 MHz oscillator is 4.6 ppm
the effective out of range limits of the PRIOOR and SECOOR pins will be +16.6 ppm to -7.4 ppm or +7.4 ppm to
-16.6 ppm. Both references are monitored at the same time. PRIOOR and SECOOR are updated every 1.0 to 1.5
seconds.
3.7
Lock Range
This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock
range is equal to the capture range for the MT90401.
3.8
Phase Slope
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect
to an ideal signal. The given signal is typically the output signal. An ideal signal is one that is at exactly the nominal
frequency and is completely free of jitter and wander.
3.9
Frequency Slope
Frequency slope is measured in ppm per second and is the rate at which the fractional frequency offset of a given
signal changes. The fractional frequency offset is calculated with respect to an ideal signal. The given signal is
typically the output signal. An ideal signal is one that is at exactly the nominal frequency and is completely free of
jitter and wander.
3.10
Time Interval Error (TIE)
TIE is the time delay between a given timing signal and an ideal timing signal.
3.11
Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
MTIE ( S ) = TIEmax ( t ) – TIEmin ( t )
3.12
Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a
mode change.
22
Zarlink Semiconductor Inc.
MT90401
3.13
Data Sheet
Phase Lock Time
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal
and output signal are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
1. initial input to output phase difference
2. initial input to output frequency difference
3. synchronizer loop filter
4. synchronizer limiter
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT90401 loop filter
and limiter were optimized to meet the GR-253-CORE, GR-1244-CORE, and G-813 jitter transfer and phase slope
requirements.
4.0
MT90401 and Network Specifications
The MT90401 meets all applicable PLL requirements for the following specifications.
1. Telcordia GR-1244-CORE December 2000 for Stratum 3, SONET Minimum Clock (SMC), Stratum 4 Enhanced
and Stratum 4
2. Telcordia GR-253-CORE September 2000 for SONET Internal Clocks
3. ANSI T1.101 (DS1) February 1994 for Stratum 3, Stratum 4 Enhanced and Stratum 4
4. ANSI T1.105.09-1996 for SONET Minimum Clocks (SMCs)
5. ITU-T G.813 August 1996 for Option1 and Option 2 clocks (with external jitter attenuator)
5.0
Applications
This section contains MT90401 application specific details for Master clock operation, LVDS output drivers setup,
microport functionality and output clock phase adjustment.
5.1
Master Clock
In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source
at the C20i input pin.
Another consideration in determining the accuracy of the master timing source is the desired capture range. The
sum of the accuracy of the master timing source and the capture range of the MT90401 will always equal 52 ppm.
For example, if the master timing source is ±20 ppm, then the capture range will be ±32 ppm.
5.2
TIE Correction (using PCCi)
When Primary Holdover Mode is entered for short time periods, TIE correction should not be enabled. This will
prevent unwanted accumulated phase change between the input and output.
For example, we can estimate phase accumulation for a case when ten Normal to Holdover to Normal sequential
mode changes occur, with each Holdover entered for 2 s with TIE enabled. Each mode change could account for a
phase shift as large as 250 ns. Thus, the accumulated phase could be as large as 2.9 us, and, the overall MTIE
could be as large as 2.9 us.
23
Zarlink Semiconductor Inc.
MT90401
Data Sheet
Phase hold = 0.02ppm × 2s = 40ns
Phase state = 50ns + 200ns = 250ns
Phase 10 = 10 × ( 250ns + 40ns ) = 2.9us
•
0.02 ppm is the accuracy of Holdover Mode
•
50 ns is the maximum phase continuity of the MT90401 from Normal Mode to Holdover Mode
•
200 ns is the maximum phase continuity of the MT90401 from Holdover Mode to Normal Mode (with or
without TIE Corrector Circuit)
When the same ten Normal to Holdover to Normal mode changes occur with TIE disabled, the overall MTIE will
only be 250 ns. There would be no accumulated phase change, since the input to output phase is re-aligned after
every Holdover to Normal state change.
5.3
C155 clock generation and LVDS output drivers
The MT90401 provides a 155.52 MHz clock that is frequency locked to the internally generated 19.44 MHz clock.
The locking of both clocks is achieved by the internal analog PLL that multiplies the 19.44 MHz clock eight times.
This C155 clock is output on pins C155P and C155N in LVDS format. The LVDS offset voltage Vos is set by
applying an external 1.25 V reference voltage to the Vref input (pin 33). This pin can be connected to a common
1.25 V voltage reference that may exist on the customer board or alternatively can be generated by a simple
voltage divider as it is shown in Figure 13 - LVDS Voltage Offset Vos Generation Circuit. To ensure proper operation
of LVDS drivers, the decoupling capacitor must be placed very close to the MT90401 package.
Figure 13 - LVDS Voltage Offset Vos Generation Circuit
5.4
Microport
If the HW pin is tied low, an 8 bit Motorola microprocessor may be used to control the PLL and report on the device
status. In this case the control pins SONET/SDH, RSEL, MS1, MS2, FS1, FS2, and FLOCK are unused and they
are replaced by the control bits SONET/SDH, RSEL, MS1, MS2, FS1, FS2, FLOCK. The input pin PCCi remains in
use. The output pins LOCK, HOLDOVER, SECOOR, PRIOOR function whether the device is in microprocessor
mode or hardware mode, but these signals are also available in Status Register 1. The microport provides
additional functionality not available in hardware.
24
Zarlink Semiconductor Inc.
MT90401
5.5
Data Sheet
Output Phase Adjustment
Two control registers are available to program the output phase offset of the generated clocks. All 16.384 MHz
derived outputs clocks, F16o, F80, F0o, C16o, C8o, C4o and C2o can be collectively shifted up to 125
microseconds with a step size of 60 nS with respect to the input reference by programming the Set Delay Word 1
and Set Delay Word 2 registers.
Control and Status Registers
Address
(A6A5A4A3A2A1A0)
Register
Read/
Write
Function
00H (Table 6)
Control Register 1
Read/ RSEL, FS2, FS1, MS2, MS1, SONET/SDH
Write FLOCK, TCLR
01H (Table 7)
Status Register 1
Read PRIOOR, SECOOR,
Only RSV, FLim, RSV, RSV
02H
Reserved
Read
Only
03H
Reserved
Read
Only
04H (Table 8)
Control Register 2
Read/ E3/DS3/OC3, E3/DS3, RSV=0,
Write RSV=0, RSV=0, RSV=0, RSV=0.
05H
Reserved
Read Set all bits to zero.
/Write
06H (Table 9)
Set Delay Word 2
Read/ RSV=0, RSV=0, RSV=0, RSV=0,
Write C16OCNT10,C16OCNT9, C16OCNT8
07H (Table 10)
Set Delay Word 1
Read/ C16OCNT7-0
Write
08H
Reserved
Read/ Set all bits to zero.
Write
09H
Reserved
Read
Only
0AH
Reserved
Read
Only
0BH
Reserved
Read
Only
0CH
Reserved
Read
Only
0DH
Reserved
Read
Only
Table 5 - Register Map
25
Zarlink Semiconductor Inc.
LOCK,
HOLDOVER,
RSV=0,
OffEn,
MT90401
Data Sheet
Control and Status Registers (continued)
Address
(A6A5A4A3A2A1A0)
Register
Read/
Write
0EH
Reserved
Read
Only
0FH (Table 11)
Identification Word
Read ID7-0
Only
10H
Reserved
Read/ Set all bits to zero.
Write
Function
Table 5 - Register Map (continued)
Bit
Name
Functional Description
7
RSEL
Reference Select. A zero selects the PRI (primary) reference source as the input
reference signal and a one selects the SEC (secondary) reference. Switching between
reference clocks operating at 8 kHz, 1.544 MHz and 2.048 MHz can be done at any time
and without any special setup procedures. However it is recommended that the switching
of the 19.44 MHz references will be performed by forcing PLL temporary into Holdover
mode (MS2,MS1=01) to prevent excessive phase accumulation in the internal controller.
The PLL can be switched back to Normal mode (MS2,MS1= 00) 250 us after the new
input reference has been selected.
6-5
FS2-1
Frequency Select 2 - 1. These bits select which of four possible frequencies (8 kHz,
1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI and SEC inputs.
FS2 - 0, FS1 - 0 = 19.44 MHz
FS2 - 0, FS1 - 1 = 8 kHz.
FS2 - 1, FS1 - 0 = 1.544 MHz.
FS2 - 1, FS1 - 1 = 2.048 MHz.
When “19.44 MHz” reference clock option is selected, a loss of 19.44 MHz clock or a
larger than 30000 ppm frequency deviation may create a frequency step exceeding ±4.6
ppm upon return from Auto-Holdover mode. This may result in a lock time that is longer
than normally guaranteed.
4-3
MS2-1
Mode Select 2 - 1: These bits select the PLL state of operation.
MS2 - 0, MS1 - 0 = Normal.
MS2 - 0, MS1 - 1 = Holdover.
MS2 - 1, MS1 - 0 = Freerun.
MS2 - 1, MS1 - 1 = Reserved.
2
SONET/SDH
SONET / SDH. Set to one to move the loop filter corner frequency to 70 millihertz and
limit the phase slope to 885 ns per second as per SONET requirements. Set to zero to
move the corner frequency to 1.1 Hz and limit the phase slope to 53 ns per 1.326 ms.
1
FLOCK
Fast Lock. Set to one to allow the PLL to lock faster than normal to the input reference.
During the time that FLOCK is one, the wander generation of the PLL is, of necessity,
compromised. Set to zero for normal operation.
Table 6 - Control Register 1 (Address 00H - Read/Write)
26
Zarlink Semiconductor Inc.
MT90401
Data Sheet
Bit
Name
Functional Description
0
TCLR
TIE Clear. Set to zero to clear the Time Interval Error correction circuit resulting in a
realignment of output phase with input phase. When this bit is zero, the Time Interval
Error correction circuit is disabled. When this bit is one, the Time Interval Error correction
circuit will function normally.
Table 6 - Control Register 1 (Address 00H - Read/Write) (continued)
Bit
Name
Functional Description
7
PRIOOR
Primary Out Of Range. A one indicates that the primary reference is off the PLL
center frequency by more than 12 ppm. The measurement is done on a 1 second
basis using a signal derived from the 20 MHz clock input on C20i. When the
accuracy of the 20 MHz clock is ± 4.6ppm, the effective out of range limits of the
PRIOOR signal will be +16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm.
6
SECOOR
Secondary Out of Range. A one indicates that the secondary reference is off the
PLL center frequency by more than 12 ppm. The measurement is done on a 1
second basis using a signal derived from the 20 MHz clock input on C20i. When the
accuracy of the 20 MHz clock is ± 4.6 ppm, the effective out of range limits of the
PRIOOR signal will be +16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm.
5
LOCK
4
HOLDOVER
3
RSV
Reserved.
2
FLim
Frequency Limit. This bit goes high whenever the reference frequency hits the
input frequency offset tolerance of the PLL. This bit can flicker high in the event of
large excursions of still tolerable input jitter.
1-0
RSV
Reserved.
Lock. This bit goes high when the PLL is in frequency lock to the input reference.
Holdover. This bit goes high whenever the device is in Holdover mode.
Table 7 - Status Register 1 (Address 01H - Read Only)
Bit
Name
Functional Description
7
E3DS3/OC3
E3DS3/OC3 Selection. Set this bit to zero to enable the differential 155.52 MHz
output clock on the C155N/C155P pins and cause the C34/C44 pin to output its
nominal clock frequency divided by 4. Set this bit to one to disable the differential
155.52 MHz output clock on the C155N/C155P pins and cause the C34/C44 pin to
output its nominal clock frequency.
6
E3/DS3
E3/DS3. Set this bit low to select a clock rate of 44.736 MHz for the C34/C44 pin.
Set high to select a clock rate of 34.368 MHz for the C34/C44 pins.
5-0
RSV
Reserved. Set to zero for normal operation.
Table 8 - Control Register 2 (Address 04H - Read/Write)
27
Zarlink Semiconductor Inc.
MT90401
Data Sheet
Bit
Name
7-4
RSV
Reserved. Set to zero.
3
OffEn
Offset Enable. Set high to enable a programmed phase shift between the input
reference and the generated clocks.
2-0
Functional Description
C16OCNT10-8 C16 Offset Count. The three most significant bits of the offset delay word. These
bits program the offset all clocks derived from 16.384 MHz with respect to the input
reference in step sizes of 60 nS.
Table 9 - Set Delay Word 2 (Address 06H - Read/Write)
Bit
Name
Functional Description
7-0
C16OCNT 7-0
C16 Offset Count. The eight least significant bits of the offset delay word. These
bits program the offset of all clocks derived from 16.384 MHz with respect to the
input reference in step sizes of 60 nS.
Table 10 - Set Delay Word 1 (Address 07H - Read/Write)
Bit
Name
7- 0
ID7-0
Functional Description
Identification Word 7-0. These bits contain the revision number of the part.
Table 11 - Identification Word (Address 0FH - Read Only)
28
Zarlink Semiconductor Inc.
MT90401
Data Sheet
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
1
Supply voltage
VDDR
-0.3
7.0
V
2
Voltage on any pin
VPIN
-0.3
VDD+0.3
V
3
Current on any pin
IPIN
30
mA
4
Storage temperature
TST
125
°C
5
80 LQFP package power dissipation
PPD
1000
mW
-55
* Voltages are with respect to ground (V SS) unless otherwise stated.
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions*
Characteristics
1 Supply voltage
2 Operating temperature
Sym.
Min.
Typ.
Max.
VDD
3.0
3.3
3.6
V
+85
°0 C
-40
TA
25
Units
* Voltages are with respect to ground (V SS) unless otherwise stated.
DC Electrical Characteristics*
Characteristics
Sym.
Min.
Max.
Units
Conditions/Notes
1
Supply current with C20i = 0V
IDDS
2
mA
Outputs unloaded
2
Supply
MHz
IDD
150
mA
Outputs unloaded
3
CMOS high-level input voltage
VCIH
4
CMOS low-level input voltage
VCIL
0.3VDD
V
5
Input leakage current
IIL
15
µA
VI=VDD or 0 V
6
High-level output voltage
VOH
V
IOH= 10 mA
7
Low-level output voltage
VOL
0.4
V
IOL= 10 mA
8
LVDS Differential Output Voltage
VOD
460
mV
ZT = 100 W
9
LVDS Change in VOD between
complementary output states
dVOD
40
mV
10
LVDS Offset Voltage
VOS
1.35
V
11
LVDS Change in VOS between
complementary output states
dVOS
40
mV
12
LVDS Output short circuit current
IOS
20
mA
VCI55P = 0 or
VC155N = 0
13
LVDS Output Rise/Fall Times
TRF
600
ps
Measured at 20%
and 80%
current
with C20i = 20
0.7VDD
V
2.4
250
1.15
300
* Voltages are with respect to ground (V SS) unless otherwise stated.
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
29
Zarlink Semiconductor Inc.
MT90401
Data Sheet
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels*
Characteristics
Sym.
CMOS
Units
VT
0.5VDD
V
1
Threshold Voltage
2
Rise and Fall Threshold Voltage High
VHM
0.7VDD
V
3
Rise and Fall Threshold Voltage Low
VLM
0.3VDD
V
* Voltages are with respect to ground (V SS) unless otherwise stated.
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
* Timing for input and output signals is based on the worst case
Timing Reference Points
V HM
VT
V LM
ALL SIGNALS
tIF, tOF
tIR, tOR
Figure 14 - Timing Parameter Measurement Voltage Levels
AC Electrical Characteristics - Microprocessor Timing*
Characteristics
Sym.
Min.
Max.
Units
1
DS low
tDSL
30
ns
2
DS High
tDSH
30
ns
3
CS Setup
tCSS
0
ns
4
R/W Setup
tRWS
18
ns
5
Address Setup
tADS
0
ns
6
CS Hold
tCSH
0
ns
7
R/W Hold
tRWH
4
ns
8
Address Hold
tADH
10
ns
9
Data Delay Read
tDDR
50
ns
10
Data Hold Read
tDHR
30
ns
11
Data Setup Write
tDSW
0
ns
12
Data Hold Write
tDHW
10
ns
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
30
Zarlink Semiconductor Inc.
Test Conditions
CL=150 pF
MT90401
Data Sheet
tDSL
tDSH
VTT
DS
tCSS
tCSH
CS
VTT
tRWH
tRWS
VTT
R/W
tADS
tADH
VTT
A0-A4
tDDR
VTT,VCT
VALID DATA
D0-D7
READ
D0-D7
WRITE
tDHR
tDHW
tDSW
VALID DATA
VTT
Note: DS and CS may be connected together.
Figure 15 - Microport Timing
tR8D
PRI/SEC
8kHz
tRW
tR15D
PRI/SEC
1.544MHz
PRI/SEC
2.048MHz
tR2D
tRW
tRW
F8o
NOTES:
1. Input to output delay values are valid after a
TCLR or RST with no further state changes
Figure 16 - Input to Output Timing for T1/E1 signals (Normal Mode)
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Zarlink Semiconductor Inc.
MT90401
Data Sheet
tR19D
tR19W
tR19W
PRI/SEC
19.44MHz
VT
C19o
VT
Figure 17 - Input to Output Timing for 19.44 MHz Signal (Normal Mode)
AC Electrical Characteristics - Output Timing*
Characteristics
Sym.
Min.
Max.
Units
1
Reference input pulse width high or low
(8 KHz, 1.544 MHz, 2.048 MHz)
tRW
100
ns
2
Reference input pulse width high or low
(19.4 MHz)
tR19W
10
ns
3
Reference input rise or fall time
tIR,tIF
4
8 kHz reference input to F8o delay
tR8D
5
1.544 MHz reference input to F8o delay
6
10
ns
-85
-65
ns
tR15D
400
425
ns
2.048 MHz reference input to F8o delay
tR2D
220
230
ns
7
19.44 MHz reference input to C19o delay
tR19D
38
42
ns
8
F8o to F0o delay
tF0D
115
125
ns
9
F8o to F16o delay
tF16D
23
35
ns
10
F8o to C1.5o delay
tC15D
-100
-85
ns
11
F8o to C6o delay
tC6D
58
70
ns
12
F8o to C2o delay
tC2D
-6
5
ns
13
F8o to C4o delay
tC4D
-6
5
ns
14
F8o to C8o delay
tC8D
-6
5
ns
15
F8o to C16o delay
tC16D
-6
5
ns
16
C1.5o pulse width high or low
tC15W
315
ns
17
C6o pulse width high or low
tC6W
70
ns
18
C2o pulse width high or low
tC2W
235
ns
19
C4o pulse width high or low
tC4W
115
ns
20
C8o pulse width high or low
tC8W
53
ns
21
C16o pulse width high or low
tC16W
24
ns
22
C19o pulse width high or low
tC19W
9
ns
23
C19o to c155 delay
tC155D
0
6
ns
24
F0o pulse width low
tF0WL
235
250
ns
25
F8o pulse width high
tF8WH
115
130
ns
32
Zarlink Semiconductor Inc.
Conditions/Notes†
MT90401
Data Sheet
AC Electrical Characteristics - Output Timing* (continued)
Characteristics
Sym.
Min.
Max.
Units
55
63
ns
9
ns
26
F16o pulse width low
tF16WL
27
Output clock and frame pulse rise or fall time
tOR,tOF
28
Input Controls Setup Time
tS
100
ns
29
Input Controls Hold Time
tH
100
ns
30
C34o Pulse width low or high
tC34W
9
ns
31
C44o Pulse width low or high
tC44W
6
ns
32
C8.5o Pulse width low
tC8.5WL
106
ns
33
C11o Pulse width low
tC11WL
81
ns
Conditions/Notes†
* Supply voltage and operating temperature are as per Recommended Operating Conditions
tF8WH
VT
F8o
tF0WL
tF0D
VT
F0o
tF16WL
tF16D
VT
F16o
tC16D
tC16WL
VT
C16o
tC8W
tC8W
tC8D
VT
C8o
tC4W
tC4W
tC4D
VT
C4o
tC2W
tC2D
VT
C2o
tC6W
tC6D
tC6W
VT
C6o
tC15W
tC15D
VT
C1.5o
Figure 18 - Output Timing 1
33
Zarlink Semiconductor Inc.
MT90401
Data Sheet
tC19W
tC19W
C19o
VT
tC155D
tC155D
C155p
VLVH
C155n
VLVL
Figure 19 - Output Timing 2
VT
F8o
tS
MS1,2,
RSEL,
PCCi
tH
VT
Figure 20 - Input Controls Setup and Hold Timing
VT
C34o
tC44W
VT
C44o
tC 8.5
VT
C8.5o
tC11
VT
C11o
Figure 21 - Output Timing 3
34
Zarlink Semiconductor Inc.
MT90401
Data Sheet
AC Electrical Characteristics - C20i Master Clock Input*
Characteristics
Sym.
Min.
Max.
Units
40
60
%
1
Duty cycle
2
Rise time
10
ns
3
Fall time
10
ns
Max.
Units
Conditions/Notes†
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Performance Characteristics: Mode Switching*
Characteristics
1
Min.
Holdover Mode accuracy with C20i at:
2
3
Capture range with C20i at:
4
5
Phase lock time
6
Typ.
0ppm
-0.02
+0.02
ppm
20ppm
-0.02
+0.02
ppm
0ppm
-52
+52
ppm
20ppm
-32
+32
ppm
100
s
Output phase continuity with: reference switch
200
ns
7
mode switch to Normal
200
ns
8
mode switch to Freerun
200
ns
9
mode switch to Holdover
50
ns
10
Output phase slope - SDH mode
- SONET mode
11
Reference input for Auto-Holdover with:
40
885
us/s
ns/s
8kHz
-30k
+30k
ppm
12
1.544MHz
-30k
+30k
ppm
13
2.048MHz
-30k
+30k
ppm
14
19.44MHz
-30k
+30k
ppm
Conditions/Notes†
4.6 ppm frequency
offset
53 ns per 1.326 ms
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Performance Characteristics: Output Jitter Generation - Filtered
Characteristics
MAX UIpp
MAX ns-pp
Notes
1
Intrinsic jitter at C1.5o (1.544 MHz)
0.004
2.76
Filter: 10 Hz - 40 kHz
2
Intrinsic jitter at C2o (2.048 MHz)
0.004
1.83
Filter: 20 Hz - 100 kHz
3
Intrinsic jitter at C19o (19.44 MHz)
0.100
5.20
Filter: 500 Hz - 1.3 MHz OC-3
4
Intrinsic jitter at C19o (19.44 MHz)
0.100
5.16
Filter: 65 kHz - 1.3 MHz OC-3
5
Intrinsic jitter at C34o (34.368 MHz)
0.044
1.30
Filter: 100 Hz - 800 kHz
6
Intrinsic jitter at C34o (34.368 MHz)
0.039
1.15
Filter: 10 kHz - 800 kHz
7
Intrinsic jitter at C44o (44.736 MHz)
0.044
0.99
Filter: 10 Hz - 400 kHz
8
Intrinsic jitter at C44o (44.736 MHz)
0.037
0.82
Filter: 30 kHz - 400 kHz
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
35
Zarlink Semiconductor Inc.
MT90401
Data Sheet
Performance Characteristics: Output Jitter Generation - Filtered (VDD = 3.3V +/- 10%, TA = -5°C to +85°C)
Characteristics
MAX UIpp
MAX ns-pp
Notes
1
Intrinsic jitter at C155o (155.52 MHz)
0.12
0.76
Filter: 100 Hz - 400 kHz OC-1
2
Intrinsic jitter at C155o (155.52 MHz)
0.11
0.69
Filter: 20 kHz - 400 kHz OC-1
3
Intrinsic jitter at C155o (155.52 MHz)
0.18
1.13
Filter: 500 Hz - 1.3 MHz OC-3
4
Intrinsic jitter at C155o (155.52 MHz)
0.13
0.83
Filter: 65 kHz - 1.3 MHz OC-3
Performance Characteristics: Output Jitter Generation - Unfiltered*
Characteristics
Sym.
MAX UIpp
MAX ns-pp
1
Intrinsic jitter at C1.5o (1.544 MHz)
0.010
6.5
2
Intrinsic jitter at C2o (2.048 MHz)
0.012
5.8
3
Intrinsic jitter at C4o (4.096 MHz)
0.027
6.5
4
Intrinsic jitter at C6o (6.312 MHz)
0.037
5.8
5
Intrinsic jitter at C8o (8.192 MHz)
0.048
5.9
6
Intrinsic jitter at C8.5o (8.592 MHz)
0.032
3.8
7
Intrinsic jitter at C11o (11.184 MHz)
0.036
3.2
8
Intrinsic jitter at C16o (16.384 MHz)
0.096
5.8
9
Intrinsic jitter at C19o (19.44 MHz)
0.11
5.6
10
Intrinsic jitter at C34o (34.368 MHz)
0.12
3.5
11
Intrinsic jitter at C44o (44.736 MHz)
0.12
2.6
12
Intrinsic jitter at C155o (155.52 MHz)
0.21
1.3
13
Intrinsic jitter at F0o (8 kHz)
NA
4.7
14
Intrinsic jitter at F8o (8 kHz)
NA
4.0
15
Intrinsic jitter at F16o (8 kHz)
NA
3.1
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
36
Zarlink Semiconductor Inc.
Notes
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