Obsolescence Notice
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
P R E L I M I N A R Y
Distinctive Characteristics
t Highly integrated central switch controller
I N F O R M A T I O N
SC220 – XpressFlow Engine
XpressFlow 2020 Ethernet Routing Switch Chipset
t State of the art 0.35 micron 3.3 Volt CMOS
process
t 256-PIN PQFP package
t Operating frequency
◊
-40
40 MHz maximum
◊
-50
50 MHz maximum
◊
-66
66 MHz maximum
CAM
(Optional)
ADDRESS
MAPPING
TABLE
SC220
16
t 16-bit external CAM interface
◊
Supports ½k to 16k MAC addresses
t 32-bit Control Buffer Memory interface
◊
Supports 128k to 1M bytes
◊
Utilize high performance 32-bit Synchronous Burst SRAM
XpressFlow
CONTROL
BUFFER
32
MEMORY
t Hardware assisted Buffer and Queue Management to minimize CPU overhead
32
t 32-bit Management Bus I/O interface
◊
Allows host to access CAM and Control
Buffer Memory
◊
Supports Big and Little Endian CPUs
◊
Direct interface with various different
standard microprocessors including
386, 486 families and Motorola MPC series embedded processors
Switching bandwidth
32
XpressFlow BUS
XpressFlow BUS
SC220 - XpressFlow Engine
t 32-bit XpressFlow Bus Interface
◊
ENGINE
General Description
−1.28 Gbps @ 40 MHz system clock
−1.60 Gbps @ 50 MHz system clock
−2.10 Gbps @ 66.67 MHz system clock
◊
Supports up to 8 Multi-port Network Access Controllers
◊
XpressFlow Bus access arbitration
◊
XpressFlow Bus data transfer load
regulation
t Full IP Switching
◊
Addresses resolved by SC220
The XpressFlow Engine contains the switching data base interface and buffer management logic in order to do the switching
decision making for unicast, multicast, and broadcast frames.
Hardware assisted queue manager is incorporated to facilitate
buffer management. It also provides a generic Management Bus
interface to allow external processor to do initialization, learning,
VLAN, and RMON support, etc. In addition, a XpressFlow Bus
interface block is responsible for communicating with the Network
Access Controllers through the XpressFlow message passing
protocol.
t MAC Address Mapping Table
◊
Supports either CAM based or SRAM
based Switching data base
Related Components:
t EA218E – 8-port 10Mbps Ethernet Access Controller
t EA218 – 6-port 10 + 2-port 10/100 Ethernet Access Controller
t EA234 – 4-port 10/100 Fast Ethernet
© 1998 Vertex Networks, Inc.
1999
1
Rev. 4.5 – February
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
Characteristics Continue
SC220
XpressFlow
Engine
◊
Embedded 32-bit HISC™ (High density
Instruction Set Core) Processor
◊
Optimized architecture for switch applications
◊
Loadable firmware for easy upgrade
t Supports unicast, multicast, and broadcast
frames
t Address Filtering
◊
Destination & Source MAC address
matching & filtering
CAM
ADDRESS
MAPPING
TABLE
CAM
Interface
16
Up to 62 groups
◊
Level 1 and 2 mapping
◊
VLAN ID tagging & stripping
◊
Auto padding if necessary after stripping
16
16
SRAM
CONTROL
BUFFER
MEMORY
32
32
Control
Buffer
Memory
Interface
32
Mngmt
Bus
Interface
HISC
I/O
Registers
32
32
32
32
32
t VLAN classification & verification
◊
HISC Core
MANAGEMENT-BUS
t Built-in address to port resolution
32
32
32
Automatic
Buffer
Manager
XpressFlow Bus
Interafce
32
XpressFlow BUS
t Supports Store-&-Forward Frame Forwarding Mode
Block Diagram –
SC220 XpressFlow Engine
t Collects statistics for RMON
Typical Application:
◊ A 16-port Ethernet Switch with 4-Fast Ethernet
Address
Mapping
Table
Buffer
RAM
RS232 Local
Control Console
SC220
XpressFlow
Engine
Switch
Manager
CPU
Flash
ROM
DRAM
Management Bus
XpressFlow Bus
Buffer
RAM
EA208E
8-Port
Ethernet
Access
Controller
8 Ethernet ports
Buffer
RAM
EA208E
8-Port
Ethernet
Access
Controller
8 Ethernet ports
Buffer
RAM
EA234
4-Port
Ethernet
Access
Controller
Four 100M
Fast Ethernet ports
System Block Diagram -16-Port Ethernet Switch with 4 Fast Ethernet Up-Links
© 1998 Vertex Networks, Inc.
1999
2
Rev. 4.5 – February
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
1. PIN ASSIGNMENT
1.1
Logic Symbol
L_WE[3:0]#
L_OE[3:0]#
L_ADSC#
L_CLK
4
P_D[31:0]
P_A[11:1]
P_CS#
P_ADS#
P_RWC
P_RDY#
P_BS16#
P_INT
P_RSTIN#
P_RSTOUT
P_CLK
Note:
4
T_MODE
CAM Interface
L_BWE[3:0]#
4
Test Pin
C_D[15:0]
XpressFlow Bus Interface
L_A[18:2]
Management Bus Interface
L_D[31:0]
Control Buffer
Memory Interface
SC220
S_D[31:0]
C_CE#
C_WE#
C_CM#
C_EC#
C_MF#
C_FF#
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_OVLD#
8
8
S_HPREQ#
S_REQ[8:1]#
S_GNT[8:1]#
S_CLK
The SC220 is pin compatible to the SC201 with only one exception:
The RSTOUT pin of SC201 is defined as a synchronous RESET output pin which follows the RSTIN input and re-synchronous with
P_CLK for meeting the 80386 timing requirement.
The RSTOUT pin for SC220 has a totally different function. It is no longer related with the RSTIN input. The RSTOUT is a watchdog output from SC220 to keep track of the active state of the host processor. Host processor needs to access the Keep
Alive register periodically to prevent the setting of the RSTOUT output. The RSTOUT output can be use as Reset input to
the host processor.
© 1998 Vertex Networks, Inc.
1999
3
Rev. 4.5 – February
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
Pin Assignment (Preliminary)
Note:
#
Input
I-ST
Output
Out-OD
I/O-TS
I/O-OD
5VT
Active low signal
Input signal
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Output signal with Open-Drain driver
Input & Output signal with Tri-State driver
Input & Output signal with Open-Drain driver
Input with 5V Tolerance
Pin No(s).
Symbol
XpressFlow Bus Interface
122,121,119,118, 116 S_D[31:27] /
P_C[0:4]
114,113,111,109,108,
106,105,104,103,101,
100,98,97,96,95,93,92,
90,89,88,87,85,84,82,
80,79,77
71
69
72
70
123
140,138,135,133,131,
129,126,124
141,139,137,134,132,
130,128,125
73
75
© 1998 Vertex Networks, Inc.
1999
Type
Name & Functions
S_D[26:0]
CMOS I/O-TS XpressFlow Bus – Data Bit [31:28] or
Processor Interface Configuration Bit
[0:4]
CMOS I/O-TS XpressFlow Bus – Data Bit [27:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_HPREQ#
S_REQ[8:1]#
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-OD
CMOS I/O-OD
CMOS Input **
S_GNT[8:1]#
CMOS Output XpressFlow Bus – Bus Grant [8:1]
S_OVLD#
S_CLK
CMOS Output XpressFlow Bus – Bus Overload
CMOS Input XpressFlow Bus – Clock
4
XpressFlow Bus – Message Envelope
XpressFlow Bus – End of Frame
XpressFlow Bus – Initiator Ready
XpressFlow Bus – Target Abort
XpressFlow Bus – High Priority Request
XpressFlow Bus – Bus Request [8:1]
Rev. 4.5 – February
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Pin No(s).
Symbol
XpressFlow Bus Interface
185,184,183,182,180,
P_D[31:0]
179,177,176,175,174,
172,171,169,168,167,
166,164,163,160,159,
157,156,154,153,151,
150,149,148,146,145,
143,142
211,210,208,207,205,
P_A[11:1]
204,203,202,201,199,
198
196
P_ADS#
191
P_RWC
183
P_RDY#
184
P_BS16#
185
P_CS#
189
P_RSTIN#
190
192
187
P_RSTOUT
P_INT
P_CLK
Control Buffer Memory Interface
60,59,58,57,56,54,53,51, L_D[31:0]
50,49,48,47,46,45,43,42,
40,39,38,37,36,34,33,30,
29,27,26,25,24,23,22,21,
8,6,5,3,2,1,256,255,254, L_A[18:2]
253,251,250,248,247,
246,245,244
9
L_A[19] /
L_OE[3]#
63, 11, 19
L_OE[2:0]#
242, 62, 10, 18
12,13,14,15
16
66
© 1998 Vertex Networks, Inc.
1999
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
Type
TTL I/O-TS
(5VT)
TTL Input
(5VT)
TTL Input
(5VT)
TTL Input
(5VT)
CMOS OutOD
CMOS OutOD
TTL Input
(5VT)
TTL In-ST
(5VT)
CMOS Output
CMOS Output
TTL Input
(5VT)
TTL I/O-TS
Name & Functions
Management Bus – Data Bit [31:0]
Management Bus – Address Bit [11:1]
Management Bus – Address Strobe
Management Bus – Read/Write Control
Management Bus – Data Ready
Management Bus – 16 bit Data Bus
Management Bus – Chip Select
System RESET Input
CPU RESET Output
Management Bus – Interrupt Request
CPU Clock
Local Memory Bus – Data Bit [31:0]
CMOS Output Local Memory Bus – Address Bit [17:2]
CMOS Output Local Memory Bus – Address Bit [19:18]
or Memory Read Chip Select [3]
CMOS Output Local Memory Bus- Read Chip Select
[2:0]
L_WE[3:0]#, CMOS Output Local Memory Bus – Write Chip Select
[3:0]
L_BWE[3:0]# CMOS Output Local Memory Bus – Byte Write Enable
[3:0]
L_ADSC#
CMOS Output Local Memory Bus – Controller Address
Status
L_CLK
CMOS Output Local Memory Bus – Synchronous Clock
5
Rev. 4.5 – February
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Pin No(s).
CAM Interface
214,215,217,218,219,
220,221,222,223,225,
226,228,229,220.221,
239
241
233
234
236
237
Symbol
C_D[15:0]
C_WE#
C_CE#
C_EC#
C_CM#
C_FF#
C_MF#
Test & Reserved Pins
65
TEST
62,63,64,67,242
n/c
Power Pins
32,78,115,161,206,243 VDD (Core)
7,20,31,44,55,68,76,86, VDD
94,102,110,120,144,
152,162,170,178,186,
197,216,227,238,252
35,81,112,158,209,240 VSS (Core)
4,17,28,41,52,61,66,74, VSS
83,91,99,197,117,127,
136,147,155,165,173,
181,188,200,213,224,
235,249
© 1998 Vertex Networks, Inc.
1999
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
Type
TTL I/O-TS
(5VT)
CMOS Output
CMOS Output
CMOS Output
CMOS Output
TTL Input
(5VT)
TTL Input
(5VT)
Name & Functions
CAM Interface – Data Bus bit [15:0]
CAM Interface – Write Enable
CAM Interface – Chip Enable
CAM Interface – Enable Comparison
CAM Interface – Data/Command Select
CAM Interface – Full Flag
CAM Interface – Match Flag
CMOS I/O-TS Test Pin – Set Test Mode upon Reset,
and provides test status output during
test mode
--Reserved Pins (5 pins)
Input
Input
Input
Input
6
+3.3 Volt DC Supply for Core Logic (6
pins)
+3.3 Volt DC Supply for I/O Pads (23
pins)
Ground for Core Logic (6 pins)
Ground for I/O Pads (26 pins)
Rev. 4.5 – February
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
1.1
1.2
P_A[11]
P_A[10]
VSS (Core)
P_A[9]
P_A[8]
VDD (Core)
P_A[7]
P_A[6]
P_A[5]
P_A[4]
P_A[3]
VSS
P_A[2]
P_A[1]
VDD
P_ADS#
P_CS#
P_BS16#
P_RDY#
Connection Diagram – 256-PQFP Package (Top View)
L_A[12]
L_A[11]
L_A[10]
L_A[9]
VDD
L_A[8]
L_A[7]
L_A[6]
VSS
L_A[5]
L_A[4]
L_A[3]
L_A[2]
VDD (Core)
L_WE[3]#
C_CE#
VSS (Core)
C_WE#
VDD
C_MF#
C_FF#
VSS
C_CM#
C_EC#
C_D[0]
C_D[1]
C_D[2]
C_D[3]
C_D[4]
VDD
C_D[5]
C_D[6]
VSS
C_D[7]
C_D[8]
C_D[9]
C_D[10]
C_D[11]
C_D[12]
C_D[13]
VDD
C_D[14]
C_D[15]
VSS
1.3
256
193
1
192
Control Buffer Memory Interface
Pin 1 I.D.
Test
P_INT
P_RWC
P_RSTOUT
P_RSTIN#
VSS
P_CLK
VDD
P_D[31]
P_D[30]
P_D[29]
P_D[28]
VSS
P_D[27]
P_D[26]
VDD
P_D[24]
P_D[25]
P_D[23]
P_D[22]
VSS
P_D[21]
P_D[20]
VDD
P_D[19]
P_D[18]
P_D[17]
P_D[16]
VSS
P_D[15]
P_D[14]
VDD
VDD (Core)
P_D[13]
P_D[12]
VSS (Core)
P_D[11]
P_D[10]
VSS
P_D[9]
P_D[8]
VDD
P_D[7]
P_D[6]
P_D[5]
P_D[4]
VSS
P_D[3]
P_D[2]
VDD
P_D[1]
P_D[0]
S_GNT[8]#
S_REQ[8]#
S_GNT[7]#
S_REQ[7]#
S_GNT[6]#
VSS
S_REQ[6]#
S_GNT[5]#
S_REQ[5]#
S_GNT[4]#
S_REQ[4]#
S_GNT[3]#
S_REQ[3]#
CAM Interface
Management Bus Interface
L_A[13]
L_A[14]
L_A[15]
VSS
L_A[16]
L_A[17]
VDD
L_A[18]
L_A[19] / L_OE[3]#
L_WE[1]#
L_OE[1]#
L_BWE[3]#
L_BWE[2]#
L_BWE[1]#
L_BWE[0]#
L_ADSC#
VSS
L_WE[0]#
L_OE[0]#
VDD
L_D[0]
L_D[1]
L_D[2]
L_D[3]
L_D[4]
L_D[5]
L_D[6]
VSS
L_D[7]
L_D[8]
VDD
VDD (Core)
L_D[9]
L_D[10]
VSS (Core)
L_D[11]
L_D[12]
L_D[13]
L_D[14]
L_D[15]
VSS
L_D[16]
L_D[17]
VDD
L_D[18]
L_D[19]
L_D[20]
L_D[21]
L_D[22]
L_D[23]
L_D[24]
VSS
L_D[25]
L_D[26]
VDD
L_D[27]
L_D[28]
L_D[29]
L_D[30]
L_D[31]
VSS
L_WE[2]#
L_OE[2]#
XpressFlow Bus Interface
64
129
128
T_MODE
VSS
L_CLK
VDD
S_EOF#
S_TABT#
S_MSGEN#
S_IRDY
S_OVLD#
VSS
S_CLK
VDD
S_D[0]
VDD (Core)
S_D[1]
S_D[2]
VSS (Core)
S_D[3]
VSS
S_D[4]
S_D[5]
VDD
S_D[6]
S_D[7]
S_D[8]
S_D[9]
VSS
S_D[10]
S_D[11]
VDD
S_D[12]
S_D[13]
S_D[14]
S_D[15]
VSS
S_D[16]
S_D[17]
VDD
S_D[18]
S_D[19]
S_D[20]
S_D[21]
VSS
S_D[22]
S_D[23]
VDD
S_D[24]
VSS (Core)
S_D[25]
S_D[26]
VDD (Core)
S_D[27]
VSS
S_D[28] / P_C[3]
S_D[29] / P_C[2]
VDD
S_D[30] / P_C[1]
S_D[31] / P_C[0]
S_HPREQ#
S_REQ[1]#
S_GNT[1]#
S_REQ[2]#
VSS
S_GNT[2]#
65
© 1998 Vertex Networks, Inc.
1999
7
Rev. 4.5 – February
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1.4
O
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Connection Diagram – 256-BGA Package (Top View)
1
2
3
A
L_A
[13]
L_A
[12]
L_A
[10]
B
L_A
[14]
C
L_A
[18]
L_A
[16]
D L_OE L_OE
[1]#
[3]#
4
5
6
7
L_A[5] / L_A[2] /
P_C[3] P_C[0]
11
12
13
14
15
16
17
18
C_ C_ EC# C_D
MF#
[2]
8
9
10
C_D
[3]
C_D
[6]
C_D
[10]
C_D
[13]
P_A
[11]
P_A
[8]
P_A
[6]
P_A
[3]
C_
CM#
C_D
[1]
C_D
[4]
C_D
[7]
C_D
[11]
C_D
[14]
P_A
[10]
P_A
[7]
P_A
[4]
P_
ADS#
L_A L_A[3] / C_ CE#
[6] P_C[1]
L_A
[15]
L_A
[9]
L_A L_A[4] / L_WE
[7] P_C[2] [3]
C_
WE#
C_
FF#
C_D
[0]
C_D
[5]
C_D
[9]
C_D
[12]
C_D
[15]
P_A
[9]
P_A
[5]
P_A P_ CS# P_ P_RST
[1]
RWC OUT
L_A
[17]
VDD
(Core)
VSS
VDD
VSS
VSS
C_D
[8]
VDD
VSS
VDD
VDD
(Core)
VSS
VDD P_RST
IN#
VDD
VSS
P_
CLK
P_D
[29]
P_D
[28]
P_D
[27]
VDD
(Core)
P_D
[26]
P_D
[25]
P_D
[24]
VDD
VSS
G L_D
P_
INT
P_D
[30]
L_ L_BWE L_BWE VDD
ADSC# [0]#
[1]#
[1]#
P_A
[2]
P_D
[31]
VSS
[3]#
20
P_
P_
BS16# RDY#
L_A
[8]
VSS
[2]#
19
L_A
[11]
E L_BWE L_BWE L_WE
F
I
SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
[0]
L_OE
[0]#
H
L_D
[3]
L_D
[2]
L_D
[1]
L_WE
[0]#
VSS
P_D
[23]
P_D
[22]
P_D
[21]
J
L_D
[7]
L_D
[6]
L_D
[4]
L_D
[5]
VDD
P_D
[20]
P_D
[19]
P_D
[18]
K
L_D
[9]
L_D
[8]
VDD
VSS
P_D
[17]
P_D
[16]
P_D
[15]
L
L_D
[10]
L_D
[11]
L_D
[12]
VSS
P_D
[12]
P_D
[13]
M L_D
[13]
L_D
[14]
L_D
[15]
VDD
(Core)
VSS
P_D
[9]
P_D
[10]
P_D
[11]
N
L_D
[16]
L_D
[17]
L_D
[18]
VSS
P_D
[3]
P_D
[6]
P_D
[7]
P_D
[8]
P
L_D
[19]
L_D
[20]
L_D
[21]
VDD
VDD
(Core)
P_D
[2]
P_D
[4]
P_D
[5]
R
L_D
[22]
L_D
[23]
L_D
[24]
L_D
[26]
VDD
P_D
[0]
P_D
[1]
T
L_D
[25]
L_D
[27]
L_D
[28]
VSS
VSS S_REQ S_REQ S_GNT
[7]#
[8]#
[8]#
U
L_D
[29]
L_D
[30]
L_D
[31]
VDD
VSS
S_D
[4]
VSS
VDD
VDD
(Core)
VSS
VDD
VSS
S_D
[25]
S_D S_REQ S_GNT S_GNT S_GNT S_GNT
[29]
[1]#
[4]#
[5]#
[6]#
[7]#
L_WE
[2]#
L_
S_
CLK TABT#
S_D
[0]
S_D
[3]
S_D
[7]
S_D
[10]
S_D
[13]
VDD
S_D
[20]
S_D
[23]
S_D
[26]
VDD
W L_OE S_MSG
S_
S_
EOF# OVLD#
S_D
[1]
S_D
[5]
S_D
[8]
S_D
[11]
S_D
[14]
S_D
[17]
S_D
[19]
S_D
[22]
VSS
S_D
[27]
S_
IRDY
S_D
[2]
S_D
[6]
S_D
[9]
S_D
[12]
S_D
[15]
S_D
[16]
S_D
[18]
S_D
[21]
S_D
[24]
V
[2]#
Y
T_
MODE
EN#
S_
CLK
© 1998 Vertex Networks, Inc.
1999
P_D
[14]
8
S_D
[30]
VDD S_REQ S_REQ
[4]#
[5]#
S_HP S_GNT S_REQ S_GNT
REQ# [1]#
[6]#
[3]#
S_D
[28]
S_D S_REQ S_GNT S_REQ
[31]
[2]#
[2]#
[3]#
Rev. 4.5 – February
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
Pin Reference Table: (256 Pin PQFP& 256-BGA)
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
L_A[13]
L_A[14]
L_A[15]
VSS
L_A[16]
L_A[17]
VDD
L_A[18]
L_A[19] / L_OE[3]#
L_WE[1]#
L_OE[1]#
L_BWE[3]#
L_BWE[2]#
L_BWE[1]#
L_BWE[0]#
L_ADSC#
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
TEST
VSS
L_CLK
VDD
S_EOF#
S_TABT#
S_MSGEN#
S_IRDY
S_OVLD#
VSS
S_CLK
VDD
S_D[0]
VDD (Core)
S_D[1]
S_D[2]
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
S_REQ[3]#
S_GNT[3]#
S_REQ[4]#
S_GNT[4]#
S_REQ[5]#
S_GNT[5]#
S_REQ[6]#
VSS
S_GNT[6]#
S_REQ[7]#
S_GNT[7]#
S_REQ[8]#
S_GNT[8]#
P_D[0]
P_D[1]
VDD
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
P_RDY#
P_BS16#
P_CS#
P_ADS#
VDD
P_A[1]
P_A[2]
VSS
P_A[3]
P_A[4]
P_A[5]
P_A[6]
P_A[7]
VDD (Core)
P_A[8]
P_A[9]
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
L_WE[0]#
L_OE[0]#
VDD
L_D[0]
L_D[1]
L_D[2]
L_D[3]
L_D[4]
L_D[5]
L_D[6]
VSS
L_D[7]
L_D[8]
VDD
VDD (Core)
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
VSS (Core)
S_D[3]
VSS
S_D[4]
S_D[5]
VDD
S_D[6]
S_D[7]
S_D[8]
S_D[9]
VSS
S_D[10]
S_D[11]
VDD
S_D[12]
S_D[13]
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
P_D[2]
P_D[3]
VSS
P_D[4]
P_D[5]
P_D[6]
P_D[7]
VDD
P_D[8]
P_D[9]
VSS
P _D[10]
P_D[11]
VSS (Core)
P_D[12]
P_D[13]
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
VSS (Core)
P_A[10]
P_A[11]
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
L_D[9]
L_D[10]
VSS (Core)
L_D[11]
L_D[12]
L_D[13]
L_D[14]
L_D[15]
VSS
L_D[16]
L_D[17]
VDD
L_D[18]
L_D[19]
L_D[20]
L_D[21]
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
S_D[14]
S_D[15]
VSS
S_D[16]
S_D[17]
VDD
S_D[18]
S_D[19]
S_D[20]
S_D[21]
VSS
S_D[22]
S_D[23]
VDD
S_D[24]
VSS (Core)
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
VDD (Core)
VDD
P_D[14]
P_D[15]
VSS
P_D[16]
P_D[17]
P_D[18]
P_D[19]
VDD
P_D[20]
P_D[21]
VSS
P_D[22]
P_D[23]
P_D[24]
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
C_D[6]
C_D[5]
VDD
C_D[4]
C_D[3]
C_D[2]
C_D[1]
C_D[0]
C_EC#
C_CM#
VSS
C_FF#
C_MF#
VDD
C_WE#
VSS (Core)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
L_D[22]
L_D[23]
L_D[24]
VSS
L_D[25]
L_D[26]
VDD
L_D[27]
L_D[28]
L_D[29]
L_D[30]
L_D[31]
VSS
L_WE[2]#
L_OE[2]#
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
S_D[25]
S_D[26]
VDD (Core)
S_D[27]
VSS
S_D[28]
S_D[29]
VDD
S_D[30]
S_D[31]
S_HPREQ#
S_REQ[1]#
S_GNT[1]#
S_REQ[2]#
VSS
S_GNT[2]#
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
P_D[25]
VDD
P_D[26]
P_D[27]
VSS
P_D[28]
P_D[29]
P_D[30]
P_D[31]
VDD
P_CLK
VSS
P_RSTIN#
P_RSTOUT
P_RWC
P_INT
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
C_CE#
L_WE[3]
VDD (Core)
L_A[2] / P_C[0]
L_A[3] / P_C[1]
L_A[4] / P_C[2]
L_A[5] / P_C[3]
L_A[6]
VSS
L_A[7]
L_A[8]
VDD
L_A[9]
L_A[10]
L_A[11]
L_A[12]
© 1998 Vertex Networks, Inc.
1999
9
VSS
C_D[15]
C_D[14]
VDD
C_D[13]
C_D[12]
C_D[11]
C_D[10]
C_D[9]
C_D[8]
C_D[7]
VSS
Rev. 4.5 – February
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
•
For 256-BGA package: F4, K4, P4, U5, U9, U12, V11, V15, V17, R17, J17, F17, D17, D14, D12, D8 and D6 are VDD.
‚
For 256-BGA package: D4, M4, U10, P17, G17 and D15 are VDD(Core).
ƒ
For 256-BGA package: E4, G4, L4, N4, T4, U6, U8, U11, U13, W14, T17, M17, K17, H17, E17, D16, D13, D10, D9, D7, and
D5 are VSS.
© 1998 Vertex Networks, Inc.
1999
10
Rev. 4.5 – February
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
2 FUNCTIONAL DESCRIPTION
2.1 CAM Interface
t Direct interface with MUSIC MU9C1480 1k x
64 bit Content Addressable Memory (CAM)
◊ Expandable to support 8k MAC Addresses
t Two access masters: HISC in XpressFlow
CAM
Engine, and Switch Manager CPU
CAM
Interface
Logic
Command
Block
From HISC
Response
Data Block
To HISC
Command
Block
From CPU
Response
Data Block
To CPU
t Master interface with CAM Interface logic via
two dedicated CAM Command Blocks
◊ One for HISC
◊ One for Switch Manager CPU
Block Diagram – CAM Interface
t Both HISC and Switch Manager CPU can ac-
cess the CAM by setting up their corresponding CAM Command Blocks, and read the return information from their own Response Data Block
2.1.1
Pin Description
Symbol
C_D[15:0]
C_CE#
C_WE#
C_CM#
C_EC#
C_MF#
C_FF#
© 1998 Vertex Networks, Inc.
1999
Type
Name & Functions
TTL
I/O-TS
CMOS
Output
CAM Data Bus bit [15:0] – a 16-bit data bus for Data/Command input/output.
CAM Chip Enable – Enables the CAM by registers the control signals
on its falling edge and release them on its rising edge. Also used for
locking and unlocking the cascaded daisy chain.
CMOS CAM Write Enable – allows to write data or command to CAM
Output
CMOS CAM Data/Command Select – defines data or command operations
Output
CMOS CAM Enable Comparison – latches and enables the MF and FF outputs
Output during a comparison cycle.
TTL CAM Match Flag – indicates a valid match during a comparison cycle.
Input
TTL CAM Full Flag – indicates there is no empty location in the CAM.
Input
11
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
Bus Cycle Waveforms
S_CLK
C_CE#
C_CM#
C_EC#
C_WE#
C_MF#
C_D[15:0]
Write
MAC Address
Byte 0, & 1
Write
MAC Address
Byte 2, & 3
Write
MAC Address
Byte 4, & 5
Read
MAC Control
Buffer Pointer
Typical MAC Address Compare Operation
Note:
Refer to MUSIC MU9C1480 CAM data sheet for detailed timing parameters.
© 1998 Vertex Networks, Inc.
1999
12
Rev. 4.5 – February
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2.2
O
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
Local Memory (Control Buffer Memory) Interface
t Uses industry standard Synchronous Burst SRAM (Pipe-lined Mode)
◊ Supports 64k x 32, 128k x 32, or 256k x 32 chips up to maximum 2M bytes
t Provides 4 individual Byte Write Enable controls
t Supports back to back Read or Write operations
2.2.1
Pin Description
Symbol
Type
Name & Functions
L_D[31:0]
TTL Local Memory Data Bus Bit [31:0] – a 32-bit synchronous data bus.
I/O-TS
L_A[18:2]
CMOS Local Memory Address Bus Bit [18:2] – Bit [17:2] of a synchronous adOutput dress bus. The memory address is sampled when L_CS# is enabled
and L_ADSC# is asserted.
L_A[19] /
CMOS Local Memory Address Bus Bit [19] or Local Memory Write Chip Select
L_WE[3]#
Output [3] – Depends on memory configuration, this pin can be used as the
Local Memory Address Bit [19] or as the Local Memory Write Chip
Select [3].
L_WE[2:0]#
CMOS Local Memory Write Chip Select [2:0] – allows up to write one of the 4
Output banks of memory.
L_OE[3:0]#
CMOS Local Memory Read Chip Select [3:0] – allows up to read one of the 4
Output banks of memory.
L_BWE[3:0]# CMOS Local Memory Byte Write Enable [3:0] – use to write individual bytes.
Output
L_ADSC#
CMOS Local Memory Controller Address Status – to load a new address.
Output
L_CLK
CMOS Local Memory Clock – a synchronous clock to memory devices.
Output
© 1998 Vertex Networks, Inc.
1999
13
Rev. 4.5 – February
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
Supported Memory Configurations
Read/Write Chip Select and High Address Bits
Chip #3
Chip #2
RAM
Chip Size
# of
RAM
Chips
64k x 32
1
256k bytes
----
----
----
----
2
512k bytes
----
----
----
----
256k x32
2.2.2
Chip #0
Total Buffer L_A[19] / L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
Memory L_WE[3]#
Size
4
128k x 32
Chip #1
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
1M bytes L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
1
256k bytes
----
----
----
----
----
----
L_WE[0]# L_OE[0]#
2
1M bytes
----
----
----
----
4
2M bytes L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
1
1M bytes
L_A[19]
----
----
----
2
2M bytes
L_A[19]
----
----
----
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
Bus Cycle Waveforms
L_CLK
L_ADSC#
L_CS#
L_A[19:2]
A1
A2
A3
A3+1
A3+2
A3+3
A4
A4+1
A4+2
A4+3
A5
A6
L_WE[3:0]#
L_BWE[3:0]#
L_OE[3:0]#
L_D[31:0] (Wr)
D1
L_D[31:0] (Rd)
D3
D3+1
D3+2
D3+3
D2
D6
D4
D4+1
D4+2
D4+3
D5
Typical Local Memory Access Operations
Note:
Refer to manufacturer’s data sheet for detailed timing parameters.
© 1998 Vertex Networks, Inc.
1999
14
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2.3
I
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N
Management Bus Interface
t Supports various industry standard micro-
processors including:
t Provides separate Address and Data bus
t Supports Big & Little Endian byte ordering
◊ Intel 186/486 family or equivalent
◊ Motorola MPC series embedded processors
t Supports 16- or 32-bit Data Bus
t Provides a single interrupt signal to Switch
t Easily adapts to other industry standard CPUs
2.3.1
T
SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
Manager CPU
Pin Description
Symbol
Type
P_C[4:0]
Name & Functions
CMOS Input Processor Configuration bit [4:0]: – During the Reset Cycle, the P_C[4:0] pins provides the processor configuration. By using external weak pull-up or -down resistors, they define the External
Management Bus Interface Configuration. These inputs are sampled at the trailing edge of the
Reset cycle.
C[0] – Defines the CPU Clock input is 1X or 2X clock
C[1] – Selects either Big or Little Endian byte ordering
C[2] – Defines the polarity of the P_RWC (Rd/Wr Control) input
C[3] – Defines the CPU Data Bus width – 16-bit or 32-bit
C[4] – Defines the timing relationship between P_RDY and P_D[15:0] valid. If C[4] is High,
the P_D[15:0] are valid along in the same clock period as P_RDY is asserted. If C[4]
is Low, the P_RDY is asserted one clock period early ahead of the P_D[15:0] are
valid.
Lo
Hi
P_A[11:1]
TTL In
(5VT)
TTL I/O-TS
(5VT)
TTL In
(5VT)
TTL
Input (5VT)
P_D[15:0]
P_ADS#
P_RWC
P_RDY#
P_BS16#
P_CS#
P_INT
•
P_RSTIN#
P_RSTOUT
P_CLK
Note:
TTL OutOD
TTL Out-OD
TTL In
(5VT)
TTL Output
TTL In-ST
(5VT)
CMOS
Output
TTL In
(5VT)
•
© 1998 Vertex Networks, Inc.
1999
C[0]
CPU Clock
C[1]
Byte Order
C[2]
RWC
C[3]
Bus Width
C[4]
RDY Timing
1X Clock
2x Clock
Little Endian
Big Endian
P_R/W#
P_W/R#
16-bit
32-bit
Normal
Early
After RESET, these pins are used as XpressFlow Bus Data bit [31:27].
Address Bus Bit [11:1] – I/O port address
Data Bus Bit [15:0] – a 16-bit synchronous data bus.
Address Strobe – indicates valid address is on the bus
Read/Write Control – indicates the current bus cycle is a read or write cycle. C[1] defines the
polarity of this signal during the Reset cycle.
C[1]=Low
P_R/W# is used for PowerPC or other similar processors.
C[1]=High
P_W/R# is used for 386, 486 or other similar processors
Data Ready – timing indicates for bus data valid
Bus Size 16 – response to bus master that the SC-201 only supports 16-bit data bus width.
Chip Select – indicates the XpressFlow Engine is the target for the current bus operation.
Interrupt Request to Switch Manager CPU The polarity of this signal output is programmable via
chip configuration register.
Power Up Reset Input – Asynchronous Reset Input from either Power-Up Reset circuit or from
Switch Manager CPU (except 386)
Synchronous Reset Output – Synchronous Reset Output for i386 family as the Switch Manager
CPU
CPU Clock – 1X Clock for the others
Output signal with programmable polarity.
15
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
Motorola MPC801 Processor Interface
P_CLK
{CLKOUT}
P_ADS#
{TS#}
P_A[11:1]
{A[20:30]}
P_CS#
P_RWC
{RD/WR#}
P_RDY#
{TA#}
P_D[31:0]
{D[0:31]} (in)
P_D[31:0]
{D[0:31]} (out)
Note:
Mnemonics within {} are the equivalent signals defined by MPC801
Typical Motorola MPC801 CPU I/O Access Operations
2.3.3 Intel 486 Processor Interface
P_CLK
P_ADS#
P_A[11:1]
P_CS#
P_W/R#
P_RDY#
P_D[31:0] (in)
P_D[31:0] (out)
Typical 486 CPU I/O Access Operations
© 1998 Vertex Networks, Inc.
1999
16
Rev. 4.5 – February
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
2.3.4 Intel 386 Processor Interface
P_CLK
PH2 (internal)
PH2
P_ADS#
P_A[11:1]
P_CS#
P_W/R#
P_RDY#
P_D[15:0] (in)
P_D15:0] (out)
Typical 386 CPU I/O Access Operations
P_CLK
PH2 (internal)
PH2
PH1
PH2
PH2 or PH1
P_RSTIN#
P_RSTOUT#
Internal PH2 Clock Synchronization
Note:
© 1998 Vertex Networks, Inc.
1999
See Intel 386 Processor Data Book for more details
17
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
2.3.5 Register Map
Note:
All 32-bit registers are D-word aligned.
All 16-bit registers are also D-word aligned and right justified.
For the Little Endian CPUs, register offset bit [1,0] are always set to be 00.
For the Big Endian CPUs, register offset bit [1,0] are always set to be 10.
This is a Global Register. CPU is allowed to write the Global Register of all devices by a
single operation.
These registers are reserved for system diagnostic usage only.
I/O Offset
Little
Big
Reg.
Endian Endian Size
Register Description
W/R
Device Configuration Registers (DCR)
GCR
Global Control Register
DCR0
Device Status Register
DCR1
Signature & Revision Register
DCR2
ID Register
DCR3
Local Control Register
DCR4
Interface Status Register
DCR5
Bus Credit Register
hF00
hF00
hF10
hF20
hF30
hF40
hF50
hF02
hF02
hF12
hF22
hF32
hF42
hF52
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
W/---/R
--/R
W/R
W/R
--/R
W/R
Interrupt Controls
ISR
Interrupt Status Register – Unmasked
ISRM
Interrupt Status Register – Masked
IMSK
Interrupt Mask Register
IAR
Interrupt Acknowledgment Register
hF80
hF90
hFA0
hFB0
hF82
hF92
hFA2
hFB2
16-bit
16-bit
16-bit
16-bit
--/R
--/R
W/R
W/--
hE08
hE18
hE28
hE40
hE50
hE68
hE6C
hE68
hE6C
hE08
hE18
hE28
hE42
hE52
hE68
hE6C
hE68
hE6C
32-bit
32-bit
32-bit
16-bit
16-bit
32-bit
32-bit
32-bit
32-bit
W/R
W/R
W/R
W/R
W/R
W/-W/---/R
--/R
hD00
hD20
hD20
hD30
hD80
hD90
hDA0
hDB0
hD02
hD22
hD22
hD32
hD82
hD92
hDA2
hDB2
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
W/R
--/R
W/---/R
W/R
W/R
W/R
--/R
Buffer Memory Interface
MWAR Memory Write Address Register – Single Cycle
MRAR Memory Read Address Register – Single Cycle
MBAR Memory Address Register – Burst Mode
MWBS Memory Write Burst Size (in D-words)
MRBS Memory Read Burst Size (in D-words)
MWDR Memory Write Data Register
MWDX Memory Write Data Register – Byte Swapping
MRDR Memory Read Data Register
MRDX Memory Read Data Register – Byte Swapping
Buffers & Stacks Management
Frame Control Buffers
FCBBA Frame Control Buffer – Base Address
FCBA
Frame Control Buffer – Buffer Allocation
FCBR
Frame Control Buffer – Buffer Release
FCBAG Frame Control Buffer – Buffer Aging Status
FCBSA Frame Ctrl Buffer Stack – Base Address
FCBSL Frame Ctrl Buffer Stack – Size Limit
FCBST Frame Ctrl Buffer Stack – Buffer Low Threshold
FCBSS Frame Ctrl Buffer Stack – Allocation Status
© 1998 Vertex Networks, Inc.
1999
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
I/O Offset
Little
Big
Reg.
Endian Endian Size
Register Description
Buffers & Stacks Management (Continue)
Switch Control Buffers
SCBBA Switch Control Buffer – Base Address
SCBA
Switch Control Buffer – Buffer Allocation
SCBAG Switch Control Buffer – Buffer Aging Status
SCBSA Switch Ctrl Buffer Stack – Base Address
SCBSL Switch Ctrl Buffer Stack – Size Limit
SCBST Switch Ctrl Buffer Stack – Buffer Low Threshold
SCBSS Switch Ctrl Buffer Stack – Allocation Status
MAC Control Tables
MCTA
MAC Control Table – Table Allocation
MCTR MAC Control Table – Table Release
MCTSA MAC Ctrl Table Stack – Base Address
MCTSS MAC Ctrl Table Stack – Allocation Status
W/R
hC00
hC20
hC30
hC80
hC90
hCA0
hCB0
hC02
hC22
hC32
hC82
hC92
hCA2
hCB2
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
W/R
--/R
--/R
W/R
W/R
W/R
--/R
hB20
hB20
hB80
hBB0
hB22
hB22
hB82
hBB2
16-bit
16-bit
16-bit
16-bit
--/R
W/W/R
--/R
Queue Management
QSBA
Queue Structure – Base Address
MFTA
Multicast Frame Table – Base Address
CINQ
CPU Input Queue
COTQ CPU Output Queue
CSQ0
CPU Status Queue – 1st D-word
CSQ1
CPU Status Queue – 2nd D-word
CSQ2
CPU Status Queue – 3rd D-word
hA00
hA10
hA88
hA88
hA98
hAA8
hAB8
hA02
hA12
hA88
hA88
hA98
hAA8
hAB8
16-bit
16-bit
32-bit
32-bit
32-bit
32-bit
32-bit
W/R
W/R
W/---/R
--/R
--/R
--/R
CAM Interface
CCWR CAM Command/Data Write Register
CSRL
CAM Status/Data Read Register Low
CSRH
CAM Status/Data Read Register High
h908
h928
h938
h908
h928
h938
32-bit
32-bit
32-bit
W/---/R
--/R
HISC Control
HPCR
HISC Processor Control Register
HMCL
HISC Micro-Code Loading Port
HPRC
HISC Priority Control Register
h980
h998
h9B0
h982
h998
h9B2
16-bit
32-bit
16-bit
W/R
W/R
W/R
© 1998 Vertex Networks, Inc.
1999
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
XpressFlow Bus Interface
◊ Data Messages for forwarding an Ethernet
frame from receiving port to transmission
port
t Vertex Networks’ optimized XpressFlow Bus
architecture
t Provides 1G bps switching bandwidth
t Full multi bus master structure
t Allows XpressFlow Engine to communicate
with Access Controllers via a message passing protocol
t Built-in intelligent bus load regulator for data
traffic balancing
t Provides centralized bus arbitration with two
level request priorities
◊ High priority for Data Messages
◊ Command Messages for passing control
information between devices
◊ Low priority for Command Messages
2.4.1 Pin Description
Symbol
Type
Name & Functions
S_D[31:0]
CMOS Data Bus Bit [31:0] – a 32-bit synchronous data bus.
I/O-TS Note: During the system RESET period, Data Bit [31:28] are used as
Processor Interface Configuration bit [0:3]
S_MSGEN# CMOS Message Envelope – encompasses the entire period of a message
I/O-TS transfer. Targets use the leading edge of this signal to detect the beginning of a message transfer, and to decode the message header for
the intended target(s).
S_EOF#
CMOS End of Frame – only used by frame data transfer messages to identify
I/O-TS the end of frame condition. This signal is synchronous with the Rx
Frame Status word appended to the end of the message.
S_IRDY
CMOS Initiator Ready – a normal true signal. When negated, it indicates the
I/O-TS initiator had asserted wait state(s) in between command words. Target
should use this signal as enable signal for latching the data from the
bus.
S_TABT#
CMOS Target Abort – when asserted, the target had aborted the reception of
I/O-OD current message on the bus.
S_HPREQ#
CMOS High Priority Request – indicates one or more Bus Requester is reI/O-OD questing for high priority message transfer.
S_REQ[8:1]# CMOS Bus Request [8:1] – Bus Request signals from Access Controllers to
Input Bus Access Arbitrator in XpressFlow Engine
S_GNT[8:1]# CMOS Bus Grant [8:1] – Bus Grant signals from Bus Arbitrator to Bus ReOutput questers
S_OVLD#
CMOS Bus Overload – when asserted all data forwarding bus bandwidth has
Output been allocated. Cannot support additional load for data forwarding traffic
S_CLK
CMOS XpressFlow Bus Clock – 33MHz system clock
Input
© 1998 Vertex Networks, Inc.
1999
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XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
2.4.2
A
Bus Cycle Waveforms
S_CLK
S_MSGEN#
S_D[31:0]
C0
C1
D0
D1
D2
D3
D4
D5
EoF
S_EOF#
S_IRDY
XpressFlow Bus Data Transfer Cycle
S_CLK
S_MSGEN#
S_D[31:0]
C0
C1
C0
C1
EOF
C0
C1
S_EOF#
S_TABT#
Command Cycle
Data Xfer w/o Data
Aborted Command
Other XpressFlow Bus Cycles
S_CLK
S_REQ[k]#
S_REQ[j]#
S_HPREQ#
High Priority Request pre-empts the low priority request
© 1998 Vertex Networks, Inc.
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
S_CLK
S_MSGEN#
S_REQ[j]#
S_GNT[j]#
S_HPREQ#
S_REQ[I]#
S_GNT[I]#
XpressFlow Bus arbitration
S_CLK
S_REQ[k]#
S_OVLD#
Bus Overload pre-empts the data transfer request
2.5
Test Pins
Symbol
TEST
© 1998 Vertex Networks, Inc.
1999
Type
Name & Functions
CMOS Test Mode Selection & Test Output – Set Test Mode upon Reset,
I/O
and provides test status output during test mode
22
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
3 DC SPECIFICATION
3.1 ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Operating Temperature
-65C to +150C
0C to +70C
Supply Voltage VDD with Respect to VSS
Voltage on 5V Tolerant Input Pins
Voltage on Other Pins
+3.0 V to +3.6 V
-0.5 V to (VDD + 2.5 V)
-0.5 V to (VDD + 0.3 V)
Stresses above those listed may cause permanent device failure. Functionality at or above these
limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device
reliability.
3.2
DC CHARACTERISTICS
VDD = 3.0 V to 3.6 V;
T AMBIENT = 0C to +70C
Preliminary
Symbol
f osc
IDD
VOH-CMOS
VOL-CMOS
VOH-TTL
VOL-TTL
VIH-CMOS
VIL-CMOS
VIH-TTL
VIL-TTL
VIH-5VT
VIL-5VT
ILI
ILO
IIH
IIL
CIN
COUT
CI/O
Parameter Description
Min
Frequency of Operation ( -40)
Frequency of Operation ( -50)
Frequency of Operation (-66)
Supply Power – @ 33.3333 MHz (VDD =3.3
V)
Supply Power – @ 40 MHz (VDD =3.3 V)
Supply Power – @ 50 MHz (VDD =3.3 V)
Output High Voltage (CMOS) IOH = -1.0 mA
Output Low Voltage (CMOS) IOL = 1.0 mA
Output High Voltage (TTL) IOH = -1.0 mA
Output Low Voltage (TTL) IOL = 1.0 mA
Input High Voltage (CMOS)
Input Low Voltage (CMOS)
Input High Voltage (TTL)
Input Low Voltage (TTL)
Input High Voltage (TTL 5V tolerant)
Input Low Voltage (TTL 5V tolerant)
Input Leakage Current (0.1 V V IN V DD)
(all pins except those with internal pullup/pull-down resistors)
Output Leakage Current (0.1 V V OUT
VDD)
Input Leakage Current VIH = VDD - 0.1 V
(pins with internal pull-down resistors)
Input Leakage Current VIL = 0.1 V
(pins with internal pull-up resistors)
Input Capacitance
Output Capacitance
I/O Capacitance
© 1998 Vertex Networks, Inc.
1999
23
Typ
Max
Unit
300
40.0000
50.0000
66.6666
500
MHz
MHz
MHz
mA
300
300
500
500
mA
mA
V
V
V
V
V
V
V
V
V
V
A
20
20
20
VDD - 0.5
0.45
2.4
VDD x 70%
-0.5
2.0
-0.3
2.0
-0.3
0.45
VDD + 0.3
VDD x 30%
VDD + 0.3
+0.8
VDD + 2.5
+0.8
10
15
A
60
A
-60
A
8
8
10
pF
pF
pF
Rev. 4.5 – February
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
4
A
AC SPECIFICATION
4.1
XpressFlow Bus Interface:
S_CLK
S_CLK
S12
S1-min
S1-max
S1-min
S_D[31:0]
S_D[31:0]
S13
S2-min
S2-max
S2-min
S_MSGEN#
S_MSGEN#
S14
S3-min
S3-max
S3-min
S_EOF#
S_EOF#
S15
S4-min
S4-max
S4-min
S_IRDY
S_IRDY
XpressFlow Bus Interface –
Output float delay timing
S6-max
S6-min
S_TABT#
S7-max
S7-min
S_CLK
S_HPREQ#
S17
S8-max
S8-min
S18
S_D[31:0]
S_GNT[7:0]#
S19
S9-max
S9-min
S20
S_MSGEN#
S_OVLD#
S21
S22
XpressFlow Bus Interface –
Output valid delay timing
S_EOF#
S23
S24
S_IRDY
S27
S28
S_TABT#
S29
S30
S_HPREQ#
S31
S32
S_REQ[7:0]#
XpressFlow Bus Interface –
Input setup and hold timing
© 1998 Vertex Networks, Inc.
1999
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SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
-40
Symbol
O
Parameter
-50
-66
Min (ns)
Max
(ns)
Min (ns)
Max
(ns)
Min (ns)
Max
(ns)
Note:
S1
S_D[31:0] output valid delay
6
14
5
11
4
8.5
CL = 50pf
S2
S_MSGEN# output valid delay
6
14
5
11
4
8.5
CL = 50pf
S3
S_EOF# output valid delay
6
14
5
11
4
8.5
CL = 50pf
S4
S_IRDY output valid delay
6
14
5
11
4
8.5
CL = 50pf
S6
S_TABT# output valid delay
6
14
5
11
4
8.5
CL = 50pf
S7
S_HPREQ# output valid delay
6
14
5
11
4
8.5
CL = 50pf
S8
S_GNT[7:0]# output valid delay
6
14
5
11
4
8.5
CL = 20pf
S9
S_OVLD# output valid delay
6
14
5
11
4
8.5
CL = 50pf
S12
S_D[31:0] output float delay
18
15
12
S13
S_MSGEN# output float delay
18
15
12
S14
S_EOF# output float delay
18
15
12
S15
S_IRDY output float delay
18
15
12
S17
S_D[31:0] input set-up time
S18
S_D[31:0] input hold time
S19
S_MSGEN# input set-up time
S20
S_MSGEN# input hold time
S21
S22
2
1.5
1
5.5
4.5
3.5
2
1.5
1
5.5
4.5
3.5
S_EOF# input set-up time
2
1.5
1
S_EOF# input hold time
5.5
4.5
3.5
S23
S_IRDY input set-up time
2
1.5
1
S24
S_IRDY input hold time
5.5
4.5
3.5
S27
S_TABT# input set-up time
5.5
4.5
3.5
S28
S_TABT# input hold time
5.5
4.5
3.5
S29
S_HPREQ# input set-up time
4.5
3.5
2.5
S30
S_HPREQ# input hold time
5.5
4.5
3.5
S31
S_REQ[7:0]# input set-up time
6
5
4
S32
S_REQ[7:0]# input hold time
5.5
4.5
3.5
AC Characteristics -- XpressFlow Bus Interface
© 1998 Vertex Networks, Inc.
1999
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P_CLK
CPU Bus Interface:
P1
P_CLK
P_D[31:0]
O
SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
4.2
I
P2
P_RST#
P15
P16-min
P3
P4
P_ADS#
P5
CPU Bus Interface –
Output float delay timing
P6
P_W/R#
P7
P8
P_CLK
P_CS#
P16-max
P16-min
P9
P_D[31:0]
P10
P_A[11:1]
P17-max
P17-min
P11
P_RDY#
P12
P_D[31:0]
P18-max
P18-min
P_INT
CPU Bus Interface –
Input setup and hold timing
CPU Bus Interface –
Output valid delay timing
-40
Symbol
Parameter
Min
(ns)
-50
Max
(ns)
Min
(ns)
-66
Max
(ns)
Min
(ns)
Max
(ns)
Note:
P1
P_RST# input setup time
13
10
8
P2
P_RST# input hold time
3.5
2.5
2
P3
P_ADS# input set-up time
13
10
8
P4
P_ADS# input hold time
3.5
2.5
2
P5
P_W/R# input set-up time
13
10
8
P6
P_W/R# input hold time
3.5
2.5
2
P7
P_CS# input set-up time
13
10
8
P8
P_CS# input hold time
3.5
2.5
2
P9
P_A[11:1] input set-up time
13
10
8
P10
P_A[11:1] input hold time
3.5
2.5
2
P11
P_D[31:0]# input set-up time
13
10
8
P12
P_D[31:0]# input hold time
3.5
P15
P_D[31:0]# output float delay
17
13
10
P16
P_D[31:0]# # output valid delay
17
13
10
CL = 60pf
P17
P_RDY# output valid delay
13
10
8
CL = 60pf
P18
P_INT# output valid delay
8.5
6.5
5
CL = 20pf
2.5
2
AC Characteristics -- CPU Bus Interface
© 1998 Vertex Networks, Inc.
1999
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XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
4.3
O
Local Memory Interface:
Local Memory Interface:
L_CLK
L_CLK
L3-max
L3-min
L1
L2
L_D[31:0]
L_D[31:0]
L4-max
L4-min
Local Memory Interface –
Input setup and hold timing
L_A[19:2]
L5-max
L5-min
L_CS[3:0]#
L_CLK
L6-max
L6-min
L10
L3-min
L_ADSC#
L_D[31:0]
L7-max
L7-min
L_BWE[3:0]#
Local Memory Interface –
Output float delay timing
L8-max
L8-min
L_WE#]
L9-max
L9-min
L_OE#
Local Memory Interface –
Output valid delay timing
-40
Symbol
-50
Max
(ns)
Parameter
Min
(ns)
L1
L_D[31:0]# input set-up time
6.5
5.5
4
L2
L_D[31:0]# input hold time
3
2.5
2
L3
L_D[31:0]# output valid delay
5
17
4
13
3
10
CL = 30pf
L4
L_A[19:2] output valid delay
5
17
4
13
3
10
CL = 30pf
L6
L_ADSC# output valid delay
5
17
4
13
3
10
CL = 30pf
L7
L_BWE[3:0]# output valid delay
5
17
4
13
3
10
CL = 30pf
L8
L_WE# output valid delay
5
17
4
13
3
10
CL = 10pf
L9
L_OE# output valid delay
5
17
4
13
3
10
CL = 10pf
L10
L_D[31:0]# output float delay
22
Min
(ns)
-66
Max
(ns)
Min
(ns)
18
Max
(ns)
Note:
14
AC Characteristics – Local Memory Interface
© 1998 Vertex Networks, Inc.
1999
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XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
4.4
O
CAM Memory Interface:
S_CLK
C1
S_CLK
C2
C_D[15:0]
C7-max
C7-min
C3
C4
C5
C6
C_D[15:0]
C_MF#
C8-max
C8-min
C_CE#
C_FF#
C9-max
C9-min
CAM Memory Interface –
Input setup and hold timing
C_WE#
C10-max
C10--min
C_CM#
S_CLK
C11-max
C11-min
C_EC#
C12
C7-min
C_D[15:0]
CAM Memory Interface –
Output valid delay timing
CAM Memory Interface –
Output float delay timing
-40
Symbol
Parameter
-50
-66
Min Max Min Max Min Max
(ns) (ns) (ns) (ns) (ns) (ns)
C1
C_D[15:0]# input set-up time
4.5
4
5
C2
C_D[15:0]# input hold time
1.5
1.5
2
C3
C_MF# input set-up time
4.5
4
5
C4
C_MF# input hold time
1.5
1.5
2
C5
C_FF# input set-up time
4.5
4
5
C6
C_FF# input hold time
1.5
1.5
2
C7
C_D[15:0]# output valid delay
5
18
4
15
6
20
C8
C_CE# output valid delay
5
18
4
15
6
20
C9
C_WE# output valid delay
5
18
4
15
6
20
C10
C_CM# output valid delay
5
18
4
15
6
20
C11
C_CE# output valid delay
5
18
4
15
6
20
C12
C_D[16:0]# output float delay
13
10
Note:
15
AC Characteristics – CAM Memory Interface
© 1998 Vertex Networks, Inc.
1999
28
Rev. 4.5 – February
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
5.1
O
N
SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
5
I
PACKAGING INFORMATION
256-PIN PQFP
30.6 ± 0.20
25.2 REF
256
193
192
1
Pin 1 I.D.
A
B
64
25.2
REF
28.0 30.6
± 0.20 ± 0.20
129
65
0.40
TYP
128
D
0.14/0.22
28.0 ± 0.20
4.10
MAX.
3.40
± 0.20
C
0.25
MIN.
1.30 REF.
0.50/0.75
© 1998 Vertex Networks, Inc.
1999
29
Rev. 4.5 – February
P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
N
SC220
XpressFlow Engine
XpressFlow-2020 Series –
Ethernet Switch Chipset
5.2
O
256- Pin BGA
B
Pin 1 I.D.
20
18
19
16
17
14
15
12
13
10
11
8
9
6
7
4
5
2
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
A
1.27
27.00
C
2.50
max
24.13
0.50 / 0.70
Ordering Information
Part Number
SC220
Description
XpressFlow Switch Engine
Environmental –
C = Commercial
I = Industrial
Speed grade -
0 = 40 MHz
5 = 50 MHz
6 = 66 MHz
Package -
Identification
Vertex Networks Use
Revision
C 0 B
TAV
rrr
Revision 001 = Rev.1
For latest revision, leave blank
B = BGA
P= PQFP
This document contains preliminary information on our product. Vertex reserves the right to make any changes without notice.
16842 Von Karman Ave, Suite 250
Irvine, CA 92606-4950
Tel. 1-714-252-8880, FAX: 1-714-252-8868
Web Site: www.vertex-networks.com
Rev. 4.5- February, 1999
1998 VERTEX NETWORKS
E1
DIMENSION
A
A1
A2
D
D1
E
E1
b
e
MIN
MAX
2.20
2.46
0.50
0.70
1.17 REF
27.20
26.80
24.00 REF
27.20
26.80
24.00 REF
0.60
0.90
1.27
256
Conforms to JEDEC MS - 034
E
e
D1
D
A2
A1 A
1. CONTROLLING DIMENSIONS ARE IN MM
2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER
3. PRIMARY DATUM -C- AND SEATING PLANE
ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
4. N IS THE NUMBER OF SOLDER BALLS
5. NOT TO SCALE.
6. SUBSTRATE THICKNESS IS 0.56 MM
Package Code
c Zarlink Semiconductor 2003 All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes:
INDEX CORNER
PIN 1
D
D1
E1
E
= 0°-7°
A
A2
A1
L
Previous package codes:
Notes:
1. Pin 1 indicator may be a corner chamfer, dot or both.
2. Controlling dimensions are in millimeters.
3. The top package body size may be smaller than the bottom package body size by a max. of 0.15 mm.
4. Dimension D1 and E1 do not include mould protusion.
c Zarlink Semiconductor 2003 All rights reserved.
ISSUE
ACN
DATE
APPRD.
Package Code
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