ST78C34 GENERAL PURPOSE PARALLEL PRINTER PORT WITH 83 BYTE FIFO DESCRIPTION · 83 bytes of printer output FIFO · Bi-directional software parallel port · Bi-directional I/O ports · Register compatible to IBM XT, AT, compatible 386, 486 · Selectable interrupt polarity · Selectable FIFO interrupts ORDERING INFORMATION Part number Pin Package ST78C34CJ44 ST78C34CP40 ST78C34IJ44 ST78C34IP40 44 40 44 40 PLCC PDip PLCC PDip Operating temperature 0° C 0° C -40° C -40° C to + 70° C to + 70° C to + 85° C to + 85° C Rev. 3.00 6-3 N.C. PE -ACK BUSY SLCT -ERROR VCC -IOR -IOW A1 A0 5 4 3 2 1 44 43 42 41 40 N.C. 7 39 N.C. INTSEL 8 38 PD7 D7 9 37 PD6 D6 10 36 PD5 D5 11 35 PD4 D4 12 34 PD3 D3 13 33 PD2 D2 14 32 PD1 D1 15 31 PD0 D0 16 30 GND N.C. 17 29 N.C. 18 19 20 21 22 23 24 25 26 27 28 INT XTAL1 XTAL2 -CS GND RESET -STROBE -AUTOFDX INIT -SLCTIN ST78C34CJ44 N.C. FEATURES 6 PLCC Package The ST78C34 is a monolithic Bidirectional Parallel port designed to operate as a general purpose I/O port. It contains all the necessary input/output signals to be configured as a CENTRONICS printer port. The ST78C34 is a general purpose input/output controller with 83 byte internal FIFO. FIFO operation can be enabled or disabled. For CENTRONICS printer operation, all registers are mapped to IBM printer port registers. The ST78C34 is designed to operate as normal printer interface without any additional settings. Contents of the FIFO will be cleared after reset or setting the INIT pin to a low state. The auto FIFO operation starts after the first -ACK is received from the printer. Contents of the FIFO transfer to the printer at the printer loading speed. ST78C34 Figure 1, PACKAGE DESCRIPTION, ST78C34 Plastic-DIP Package 1 40 VCC SLCT 2 39 -IOR BUSY 3 38 -IOW -ACK 4 37 A1 PE 5 36 A0 INTSEL 6 35 N.C. D7 7 34 PD7 D6 8 33 PD6 D5 9 32 PD5 D4 10 31 PD4 D3 11 30 PD3 D2 12 29 PD2 D1 13 28 PD1 D0 14 27 PD0 N.C. 15 26 GND INT 16 25 -SLCTIN XTAL1 17 24 INIT XTAL2 18 23 -AUTOFDX -CS 19 22 -STROBE GND 20 21 RESET ST78C34CP40 -ERROR Rev. 3.00 6-4 ST78C34 INT INTSEL Inter Connect Bus Lines & Control signals Register Select Logic A0-A1 -CS Printer FIFO Registers Printer Data Ports Printer Control Logic Clock & Timing Generator Interrupt Control Logic D0-D7 -IOR -IOW RESET Data bus & Control Logic Figure 2, BLOCK DIAGRAM Rev. 3.00 6-5 PD0-PD7 -STROBE INIT -AUTOFDX -SELCTIN PE, SELECT BUSY, -ACK -ERROR XTAL2 XTAL1 ST78C34 SYMBOL DESCRIPTION Symbol 40 44 Signal type -ERROR 1 1 I General purpose input or line printer error (active low, with internal pull-up). This is an output from the printer to indicate an error by holding it low during error condition. SLCT 2 2 I General purpose input or line printer selected (active high, with internal pull-up). This is an output from the printer to indicate that the line printer has been selected. BUSY 3 3 I General purpose input or line printer busy (active high, with internal pull-up). An output from the printer to indicate printer is not ready to accept data. -ACK 4 4 I General purpose input or line printer acknowledge (active low, with internal pull-up). An output from the printer to indicate that data has been accepted successfully. PE 5 5 I General purpose input or line printer paper empty (active high, with internal pull-up). An output from the printer to indicate out of paper. INTSEL 6 8 I Interrupt select mode. The external -ACK can be selected as an interrupt source by connecting this pin to the VCC or left open. Connecting this pin to GND will set the interrupt to latched mode, reading the status register resets the INT output. 14-7 16-9 I/O Bi-directional data bus. Eight bit, three state data bus to transfer information to or from the CPU. D0 is the least significant bit of the data bus. INT 16 19 O Interrupt output (selectable active low or high). To signal the state of the printer port. This pin tracks the -ACK input pin, When -ACK is low INT is low and when -ACK is high INT is high if selected as active low interrupt. XTAL1 17 20 I Crystal input 1 or external clock input. A crystal can be connected to this pin and XTAL2 pin to utilize the internal oscillator circuit. An external clock can be used to clock oscillator circuit. XTAL2 18 21 O Crystal input 2 or buffered clock output. See XTAL1. -CS 19 22 I Chip select (active low). A low at this pin enables the ST78C34 / CPU data transfer operation. D0-D7 Pin Pin Description Rev. 3.00 6-6 ST78C34 SYMBOL DESCRIPTION Symbol 40 Pin 44 Signal type Pin Description GND 20 23 O Signal and power ground. RESET 21 24 I Master reset (active high). A high on this pin will reset all the outputs and internal registers. -STROBE 22 25 I/O General purpose I/O or strobe output (open drain active low, with internal pull-up). To transfer latched data to the external peripheral or printer. -AUTOFDXT 23 26 I/O General purpose I/O or line printer auto feed (open drain active low, with internal pull-up). To signal the printer for continuous form feed. INIT 24 27 I/O General purpose I/O or line printer initialize (open drain active high, with internal pull-up). To signal the line printer to enter internal initialization routine. -SLCTIN 25 28 I/O General purpose I/O or line printer select (open drain active low, with internal pull-up). To select the line printer. GND 26 30 O Power and signal ground. PD0-PD7 27-34 31-38 I/O Bi-directional parallel ports (three state). To transfer data in or out of the ST78C34 parallel port. PD7-PD0 are latched during output mode. A0-A1 36-37 40-41 I Address lines. To select internal registers. -IOW 38 42 I Write strobe (active low). A low on this pin will transfer the contents of the CPU data bus to the addressed register. -IOR 39 43 I Read strobe (active low). A low level on this pin transfers the contents of the ST78C34 data bus to the CPU. VCC 40 44 I Power supply input. Rev. 3.00 6-7 ST78C34 PRINTER PORT PROGRAMMING TABLE: A1 A0 0 0 1 1 0 1 0 1 WRITE MODE READ MODE PORT REGISTER PORT REGISTER STATUS REGISTER * COMMAND REGISTER FIFO BYTE COUNT REGISTER CONTROL REGISTER ALTERNATE FUNCTION REGISTER * Reading the status register will reset the INT output. PRINTER FUNCTIONAL DESCRIPTION Following an INIT, the parallel port will not be in the FIFO mode. Control Register bit-0 is used as the STROBE, Status Register bit-7 is the inverse of the BUSY signal, and INT is derived from -ACK. The transition into FIFO mode will occur after the first STROBE is generated and the printer responds with either an -ACK or BUSY. In FIFO mode, -STROBE is generated automatically and writing to Control Register bit-0 has no effect on -STROBE. Alternate Function Register bit 0-2 are used to control the delay and width of -STROBE. Handshaking between the printer and the ST78C34 may be controlled by bit-3 of the Alternate Function Register. Setting this bit to a “1” will result in the use of BUSY instead of -ACK for FIFO reading and interrupt control. INT will transition low when a “1” is written to Control Register bit-0 and will transition high when a write to parallel port is performed. In FIFO mode, data transfer to the printer will be controlled by the printer and will occur at the printer’s maximum data rate. The ST78C34 parallel port is designed to operate as a normal CENTRONICS printer interface. The port contains 83 byte FIFO that may be enabled via bit-7 of the Alternate Function Register (AFR). After reset, the FIFO is disabled and the part will function identical to the ST16C552. Once the FIFO is enabled via AFR bit-7, the port will enter FIFO mode after the first byte of data is strobed to the printer and the printer responds with either an -ACK or BUSY signal. The ST78C34 will remain in FIFO mode until the part is reset or INIT is brought low. While in FIFO mode, data transfer to the printer will be controlled by the printer without any user intervention. The printer port also contains a FIFO byte counter that maintains a count of the number of bytes remaining in the FIFO. The FIFO and the FIFO byte counter are cleared by a reset or by a change of state of the INIT pin. All FIFO related timing is derived from the clock input to pin 17 of the part. The FIFO byte counter is incremented one count for each parallel port write and decremented one count for each FIFO read (data taken by printer). A FIFO read will be generated at the falling edge of either ACK or BUSY. The byte counter will require two to three clock cycles to update. Hence, a read of FIFO Byte Count Register (FBCR) should only be performed a minimum of three clock after the falling edge of either -ACK or BUSY. The counter is reset whenever the FIFO is reset. If write to parallel port operation is attempted when the FIFO is full, the data will not be A special parallel port write / read mode is activated when INIT is held low, either by writing a “0” to Control Register bit-2 or by forcing the INIT pin low. In this mode the FIFO read pointer is advanced by reading the parallel port instead of the -ACK or BUSY signals. The -STROBE output is forced high. This allows the user to perform parallel port write and read from operations without strobing data to the printer. Rev. 3.00 6-8 ST78C34 written into the FIFO and the counter will not increment. 1= no interrupt is pending Reading the STATUS REGISTER will set this bit to “1”. Two interrupt modes are available and are selected with the INTSEL pin. If this pin is tied low, a latched interrupt will result. In this mode, INT will transition low when a “1” is written to Control Register bit-0. A reset or reading the Status Register will clear the interrupt. If INTSEL pin is tied high, INT will transition low when a “1” is written to Control Register bit-0 and will transition high when a write to the parallel port is issued. This (non-latched) interrupt signal is always available in Status Register bit-6 regardless of the state of the INTSEL pin. Status Register bit-2 will always contain the latched interrupt state. The polarity of the INT pin may be inverted by setting Alternate Function Register bit-6 high. STR BIT-3: ERROR input state. 0= ERROR input is in low state 1= ERROR input is in high state STR BIT-4: SLCT input state. 0= SLCT input is in low state 1= SLCT input is in high state STR BIT-5: PE input state. 0= PE input is in low state 1= PE input is in high state The ST78C34 provides additional programmable interrupt output options by programming the Alternate Function Register bit 4-5. INT output can be selected as FIFO full or FIFO empty interrupt. STR BIT-6: -ACK input state. 0= -ACK input is in low state 1= -ACK input is in high state REGISTER DESCRIPTIONS STR BIT-7: BUSY or FIFO full signal. PORT REGISTER Bi-directional printer port. Writing to this register during output mode will transfer the contents of the data bus to the PD7-PD0 ports . Reading this register during input mode will transfer the states of the PD7-PD0 to the data bus. This register will be set to the output mode after reset. 0= BUSY input is in high state 1= BUSY input is in low state FIFO is enabled. 0= FIFO is full 1= One or more empty locations in FIFO PR BIT 7-0: PD7-PD0 bi-directional I/O ports. COMMAND REGISTER STATUS REGISTER This register provides the state of the printer outputs and the interrupt condition. The state of the -STROBE, -AUTOFDXT, INIT, SLCTIN pins, and interrupt enable bit can be read by this register regardless of the I/O direction. STR BIT 1-0: This bits are set to “1” normally except when AFR bit 5-4 are both set to “1”. COM BIT-0: -STROBE input pin. 0= -STROBE pin is in high state 1= -STROBE pin is in low state STR BIT-2: Interrupt condition. 0= an interrupt is pending This bit will be set to “0” at the falling edge of the -ACK input. COM BIT-1: -AUTOFDXT input pin. 0= -AUTOFDXT pin is in high state 1= -AUTOFDXT pin is in low state Rev. 3.00 6-9 ST78C34 COM BIT-2: INIT input pin. 0= INIT pin is in low state 1= INIT pin is in high state CON BIT-5: I/O select. Direction of the PD7-PD0 can be selected by setting or clearing this bit. 0= PD7-PD0 are set for output mode 1= PD7-PD0 are set for input mode COM BIT-3: -SLCTIN input pin. 0= -SLCTIN pin is in high state 1= -SLCTIN pin is in low state CON BIT 7-6: Not used. ALTERNATE FUNCTION REGISTER (AFR) COM BIT-4: Interrupt mask. 0= Interrupt (INT output) is disabled 1= Interrupt (INT output) is enabled This register En/Disables FIFO operation and provides additional capabilities to control -STROBE. INT and change interrupt functions. AFR BIT 0-2: Timing select. The -STROBE delay and width can be controlled by these bits. COM BIT 7-5: Not used. Are set to “1” permanently. CONTROL REGISTER. Writing to this register will set the state of the STROBE, -AUTOFDXT, INIT, SLCTIN pins, and interrupt mask register. CON BIT-0: -STROBE output control bit. 0= -STROBE output is set to high state 1= -STROBE output is set to low state CON BIT-1: -AUTOFDXT output control bit. 0= -AUTOFDXT output is set to high state 1= -AUTOFDXT output is set to low state CON BIT-2: INIT output control bit. 0= INIT output is set to low state 1= INIT output is set to high state AFR Bit-2 AFR Bit-1 AFR Bit-0 TSD (clocks) TSW (clocks) 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3 5 5 9 6 10 10 18 2 4 4 8 4 8 8 16 AFR BIT-3: Interrupt source. 0= -ACK input pin is selected as printer handshaking source 1= BUSY input pin is selected as printer handshaking source CON BIT-3: -SLCTIN output control bit. 0= -SLCTIN output is set to high state 1= -SLCTIN output is set to low state AFR BIT 4-5: Interrupt type. State of the INT output pin can be selected for one of the following options. CON BIT-4: Interrupt output control bit. 0= INT output is disabled (three state mode) 1= INT output is enabled Rev. 3.00 6-10 ST78C34 ST78C34 EXTERNAL RESET CONDITION Bit-5 0 0 1 1 Bit-4 0 1 0 1 INT output Normal mode FIFO empty FIFO full FIFO empty STR bit-0 1 1 1 0 STR bit-6 -ACK FIFO empty FIFO full FIFO empty AFR BIT-6: INT output polarity. 0= Normal. INT output follows the -ACK input 1= Inverted INT output AFR BIT-7: FIFO enable / disable function. 0= FIFO is disabled( default mode). 1= FIFO is enabled. Internal 83 byte of FIFO is enabled. FIFO BYTE COUNT REGISTER (FBCR) State and content of the printer FIFO can be monitored by reading this register. FCBR BIT 0-6: FIFO byte count. Number of characters left in FIFO. FCRB bit-0 is the LSB bit of the counter and FCRB bit6 is the MSB bit of the counter. FBCR BIT-7: FIFO state. 0= FIFO is enabled 1= FIFO is disabled Rev. 3.00 6-11 SIGNALS RESET STATE PD0-PD7 -STROBE -AUTOFDXT INIT -SLCTIN Unknown, output mode High High Low High ST78C34 ST78C34 REGISTER CONFIGURATIONS A1 A0 REGISTER D7 D6 D5 D4 D3 D2 D1 D0 0 0 PR PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0 1 STR BUSY/ -FIFO full None Latched INT PE SLCT ERROR Latched INT 1 1 1 0 COM 1 1 1 INT enable -SLCTIN INIT -AUTO- -STROBE FDXT 1 0 CON X X I/O select INT mask -SLCTIN INIT -AUTO- -STROBE FDXT 1 1 AFR FIFO enable INT polarity INT type bit-1 INT type bit-0 INT source TIMING select bit-2 TIMING select bit-1 TIMING select bit-0 1 1 FBCR -FIFO status FBC-6 FBC-5 FBC-4 FBC-3 FBC-2 FBC-1 FBC-0 Rev. 3.00 6-12 ST78C34 AC ELECTRICAL CHARACTERISTICS TA=0° - 70° C, Vcc=5.0 V ± 10% unless otherwise specified. Symbol Parameter Min T1 T2 T3 T8 T9 T12 T13 T14 T15 T16 T17 Tw T19 T21 T23 T24 T25 Tr T26 T39 T40 T41 T42 T43 Clock high pulse duration Clock low pulse duration Clock rise/fall time Chip select setup time Chip select hold time Data setup time Data hold time -IOW delay from chip select -IOW strobe width Chip select hold time from -IOW Write cycle delay Write cycle=T15+T17 Data hold time -IOR delay from chip select -IOR strobe width Chip select hold time from -IOR Read cycle delay Read cycle=T23+T25 Delay from -IOR to data -ACK pulse width PD7 - PD0 setup time PD7 - PD0 hold time Delay from -ACK low to interrupt low Delay from -IOR to reset interrupt Limits Typ Units 50 50 10 5 0 10 10 10 50 0 55 105 10 10 65 0 55 115 35 75 10 25 5 5 Rev. 3.00 6-13 Conditions Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns External clock 100 pF load ST78C34 ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation 7 Volts GND-0.3 V to VCC+0.3 V 0° C to +70° C -40° C to +150° C 500 mW DC ELECTRICAL CHARACTERISTICS TA=0° - 70° C, Vcc=5.0 V ± 10% unless otherwise specified. Symbol Parameter Min VILCK VIHCK VIL VIH VOL Clock input low level Clock input high level Input low level Input high level Output low level -0.5 3.0 -0.5 2.2 VOH Output high level 2.4 I CC IIL IIL RIN ICL Avg. power supply current Input leakage Input leakage Input pullup resistance Clock leakage Limits Typ 0.6 VCC 0.8 VCC 0.4 Rev. 3.00 6-14 V V V V V V 4 12 Units Conditions Max 7 ±10 -450 40 ±10 mA mA mA kW mA IOL= 6.0 mA D7-D0 IOL= 15mA PD7PD0 IOL= 5.0 mA on all other outputs IOH= -6.0 mA D7D0 IOH= -12.0 mA PD7-PD0 IOH= -150 mA SLCTIN, INIT*,-STROBE, -AUTOFDXT IOH= -6.0 mA on all other outputs Except Pins 1-6 Pins 1-6 @ Vin=0V Pins 1-6 ST78C34 Valid Address A0-A2 T8 T9 Active -CS T21 T23 T24 T25 Active -IOR Active T26 T19 D0-D7 Data Data 7834-RD-1 General read timing Valid Address A0-A2 T8 Active -CS T14 -IOW T9 T15 T16 Active Active T12 D0-D7 T17 T13 Data Data 7834-WD-1 General write timing Rev. 3.00 6-15 ST78C34 T39 Active -ACK Active T40 T42 Active -INT Active T43 Active -IOR Active T40 NORMAL MODE INTERRUPT LATCHED MODE SELECT INTSEL T41 VALID DATA PD0-PD7 7834-PR-1 Interrupt timing T1 T2 EXTERNAL CLOCK 7834-CK-1 T3 External clock timing Rev. 3.00 6-16 ST78C34 RESET INIT INIT LOW FORCES -STROBE HIGH -STROBE 0-2 CLOCK 1-2 CLOCK 0-2 CLOCK FIFO RESET DO-D7 Data Data Active Data Active -IOW Active -IOR PDO-PD7 Data 16553-PW-1 Printer special mode Rev. 3.00 6-17 ST78C34 RESET D0-D7 Active Active Active DATA-1 PD0-PD7 Active DATA-2 Active Active DATA-3 Active Active DATA-4 Active Active -IOW Active Active Active -STROBE Active Active -ACK ` FIFO EMPTY FIFO EMPTY FIFO EMPTY FIFO mode entered after first -STROBE and -ACK -STROBE generated internally -INTP generated internally 16553-PW-2 Printer auto FIFO mode Rev. 3.00 6-18 ST78C34 Active -ACK 0-2 CLOCK 0-2 CLOCK FIFO READ (INTERNAL) Active 3-6 CLOCKS PD OUTPUT PORTS DATA DATA+1 TSD Active -STROBE BUSY SELECTED FOR FIFO OPERATION TSW BUSY 2-4 CLOCK FIFO READ (INTERNAL) Active 5-10 CLOCKS PD OUTPUT PORTS DATA DATA+1 TSD Active -STROBE TSW 16553-PW-3 Printer FIFO timing with more than one byte in the FIFO Rev. 3.00 6-19 ST78C34 RESET PD PORT -IOW Active Active Active Active PD OUTPUT PORT Active Active -STROBE TSD TSW Printer FIFO, with one byte in the FIFO Rev. 3.00 6-20 16553-PW-4 Package Dimensions 40 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) Rev. 1.00 40 21 E1 1 20 E D A2 Seating Plane A L A1 C α B B1 e INCHES SYMBOL eA eB MILLIMETERS MIN MAX MIN MAX A 0.160 0.250 4.06 6.35 A1 0.015 0.070 0.38 1.78 A2 0.125 0.195 3.18 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 1.980 2.095 50.29 53.21 E 0.600 0.625 15.24 15.88 E1 0.485 0.580 12.32 14.73 e 0.100 BSC 2.54 BSC eA 0.600 BSC 15.24 BSC eB 0.600 0.700 15.24 17.78 L 0.115 0.200 2.92 5.08 α 0° 15° 0° 15° Note: The control dimension is the inch column Package Dimensions 44 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) Rev. 1.00 C D D1 Seating Plane 45° x H1 45° x H2 A2 2 1 44 B1 D D1 B D 2 D3 e R D3 A1 A INCHES SYMBOL MIN MAX MILLIMETERS MIN MAX A 0.165 0.180 4.19 4.57 A1 0.090 0.120 2.29 3.05 A2 0.020 –––. 0.51 ––– B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.685 0.695 17.40 17.65 D1 0.650 0.656 16.51 16.66 D2 0.590 0.630 14.99 16.00 D3 0.500 typ. 12.70 typ. e 0.050 BSC 1.27 BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 Note: The control dimension is the inch column NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1991 EXAR Corporation Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.