ZILOG Z89135

PRELIMINARY PRODUCT SPECIFICATION
1
Z89135/Z89136
1
LOW-COST DTAD CONTROLLER
FEATURES
Device
ROM
(KB)
RAM*
(Bytes)
I/O
Lines
Speed
(MHz)
Z89135
Z89136
24
24
256
256
47
47
20
20
■
Clock Speed of 20.48 MHz
■
16-Bit Digital Signal Processor (DSP)
■
6K Word DSP Program ROM
■
24 KB of Z8 Program ROM (Z89135)
■
512 Words On-Chip DSP RAM
■
Watch-Dog Timer and Power-On Reset
■
8-Bit A/D Converter with up to 128 kHz Sample Rate
■
Low Power STOP Mode
■
10-Bit PWM D/A Converter (4 kHz to 64 kHz)
■
On-Chip Oscillator which Accepts a Crystal or External
Clock Drive
■
Three Vectored, Prioritized DSP Interrupts
■
Two DSP Timers to Support Different A/D and
■
D/A Sampling Rates
■
Z8 and DSP Operation in Parallel
■
IBM® PC-Based Development Tools
■
Developer’s Toolbox for T.A.M. Applications
■
Two 8-Bit Z8 Counter Timers with 6-Bit Prescaler
■
Global Power-Down Mode
■
Low Power Consumption - 200 mW (typical)
■
Two Comparators with Programmable Interrupt Priority
■
Six Vectored, Priority Z8 Interrupts
■
RAM and ROM Protect
IBM is a registered trademark of International Business
Machines Corp.
GENERAL DESCRIPTION
The Z89135/136 is a fully integrated, dual processor controller designed for low-cost digital telephone answering
machines. The I/O control processor is a Z8® MCU with 24
KB of program memory, two 8-bit counter/timers, and up to
47 I/O pins. The DSP is a 16-bit processor with a 24-bit
ALU and accumulator, 512 x 16 bits of RAM, single cycle
instructions, and 6K word program ROM plus constants
memory. The chip also contains a half-flash 8-bit A/D converter with up to 128 kHz sample rate and 10-bit PWM D/A
converter. The sampling rates for the converters are programmable. The precision of the 8-bit A/D may be extended by resampling the data at a lower rate in software.
DS97TAD0300
The Z8 and DSP processors are coupled by mailbox registers and an interrupt system, which allows DSP or Z8 programs to be directed by events in each other’s domain.
The Z89136 is the ROMless version of the Z89135. The
DSP is not ROMless. The DSP's program memory is always the internal ROM.
PRELIMINARY
1-1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
GENERAL DESCRIPTION (Continued)
Address
or I/O
(Nibble
Programmable)
Address/Data
or I/O
(Byte
Programmable)
I/O
(Bit
Programmable)
P00
P01
P02
P03
Timer 0
Capture Reg.
Register File
256 x 8 Bit
Timer 1
Port 0
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
Port 3
Register Bus
Internal Address Bus
24 Kbytes
Program
ROM
(Z89165)
Port 1
P31
P32
P33
Z8 Core
Input
P34
P35 Output
P36
P37
Internal Data Bus
Port 4
P40
P41
P42
I/O
P43
(Bit
P44 Programmable)
P45
P46
P47
Port 5
P50
P51
P52
P53
P54
P55
P56
P57
Expanded
Register Bus
Expanded Register
File
(Z8)
Extended Bus of the DSP
Peripheral
Register
(DSP)
256 Word
RAM 0
mailbox
256 Word
RAM 1
Port 2
Internal Address Bus
6K Words
Program
ROM
DSP Core
I/O
(Bit
Programmable)
Internal Data Bus
INT 1
RMLS
/AS
/DS
R/W
XTAL1
XTAL2
VDD
GND
/RESET
INT 2
Ext.
Memory
Control
DSP Port
DSP0
DSP1
PWM
(10-Bit)
PWM
Extended Bus of the DSP
Timer 2
Timer 3
OSC
ADC
(8-Bit)
Power
AN IN
AN VDD
AN GND
VREF+
VREF-
Figure 1. Functional Block Diagram
1-2
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Z8 Core Processor
DSP Coprocessor
The Z8 is Zilog’s 8-bit MCU core with an Expanded Register File to allow access to register-mapped peripheral and
I/O circuits. The Z8® MCU offers a flexible I/O scheme, an
efficient register and address space structure, and a number of ancillary features.
The DSP coprocessor is a second generation, 16-bit two’s
complement CMOS Digital Signal Processor (DSP). Most
instructions, including multiply and accumulate, are accomplished in a single clock cycle. The processor contains
two on-chip data RAM blocks of 256 words, a 6K word program ROM, 24-bit ALU, 16 x 16 multiplier, 24-bit Accumulator, shifter, six-level stack, three vectored interrupts, and
two inputs for conditional program jumps. Each RAM block
contains a set of four pointers which may be incremented
or decremented automatically to affect hardware looping
without software overhead. The data RAMs can be simultaneously addressed and loaded to the multiplier for a true
single cycle scalar multiply.
For applications demanding powerful I/O capabilities, the
Z89135/136 offers 47 pins dedicated to input and output.
These lines are grouped into six ports. Each port is configurable under software control to provide timing, status signals and parallel I/O with or without handshake.
There are four basic memory resources for the Z8 that are
available to support a wide range of configurations: Program Memory, Register File, Data Memory, and Expanded
Register File. The Z8 core processor is characterized by
an efficient register file that allows any of 256 on-board
data and control registers to be the source and/or the destination of almost any instruction. Traditional microprocessor accumulator bottlenecks are eliminated.
The Register File is composed of 236 bytes of general-purpose registers, four I/O port register,s and 15 control and
status registers. The Expanded Register File consists of
mailbox registers, WDT mode register, DSP Control register, Stop-Mode Recovery register, Port Configuration register, and the control and data registers for Port 4 and Port
5.
To unburden the software from supporting the real-time
problems, such as counting/timing and data communication, the Z8 offers two on-chip counter/timers with a large
number of user selectable modes.
Watch-Dog Timer and Stop-Mode Recovery features are
software driven by setting specific bits in control registers.
STOP and HALT instructions support reduced power operation. The low power STOP Mode allows parameter information to be stored in the register file if power fails. An
external capacitor or battery retains power to the device.
Four external DSP registers are mapped into the expanded register file of the Z8. Communication between the Z8
and the DSP occurs through those common registers
which form the mailbox registers.
The analog signal is generated by a 10-bit resolution Pulse
Width Modulator. The PWM output is a digital signal with
CMOS output levels. The output signal has a resolution of
1 in 1024 with a sampling rate of 16 kHz (XTAL = 20.48
MHz). The sampling rate can be changed under software
control and can be set at 4, 10, 16, and 64 kHz. The dynamic range of the PWM is from 0 to 4V.
An 8-bit resolution half-flash A/D converter is provided.
The conversion is conducted with a sampling frequency of
8, 16, 32, 64, or 128 kHz. (XTAL = 20.48 MHz) in order to
provide oversampling. The input signal is 4V peak to peak.
Scaling is normally ±1.25V for the 2.5V peak to peak offset.
Two additional timers (Timer2 and Timer3) have been
added to support different sampling rates for the A/D and
D/A converters. These timers are free running counters
that divide the crystal frequency to the appropriate sampling of frequency.
Notes: All signals with a preceding front slash, "/", are active Low. For example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only).
Power connections follow conventional descriptions below:
DS97TAD0300
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
PRELIMINARY
1-3
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
RMLS
2
1
ANVDD
VDD
3
GND
P04
4
P07
P50
5
P20
P57
6
P21
P03
7
P52
P02
8
P51
P01
9
/DS
P00
Zilog
XTAL2
10
68 67 66 65 64 63 62 61
60
XTAL1
11
59
ANIN
P22
12
58
VREF-
P56
13
57
ANGND
P23
14
56
/AS
P55
15
55
/RESET
P54
16
54
R//W
GND
17
53
PWM
P17
18
52
P10
P05
19
51
P47
P24
20
50
P11
P16
21
49
P46
P25
22
48
P53
P15
23
47
P45
P26
24
46
P44
P27
25
45
P43
N/C
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
N/C
P42
P41
P06
P12
P40
P37
P13
P36
DSP0
DSP1
P14
P35
VDD
P34
P33
P32
P31
Z89135
VREF+
Figure 2. Z89135 68-Pin PLCC Pin Assignments
1-4
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Table 1. Z89135 68-Pin Plastic Leaded Chip Carrier,
Pin Identification
Table 1. Z89135 68-Pin Plastic Leaded Chip Carrier,
Pin Identification
Pin # Symbol Function
Direction
Pin # Symbol Function
Direction
1
2
RMLS
VDD
ROMless
Power Supply
Control Input
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
P04
P50
P57
P03
P02
P01
P00
XTAL2
XTAL1
P22
P56
P23
P55
P54
GND
P17
P05
P24
P16
P25
P15
P26
P27
N/C
P31
P32
P33
P34
VDD
Port 0, Bit 4
Port 5, Bit 0
Port 5, Bit 7
Port 0, Bit 3
Port 0, Bit 2
Port 0, Bit 1
Port 0, Bit 0
Crystal Oscillator Clock
Crystal Oscillator Clock
Port 2, Bit 2
Port 5, Bit 6
Port 2, Bit 3
Port 5, Bit 5
Port 5, Bit 4
Ground
Port 1, Bit 7
Port 0, Bit 5
Port 2, Bit 4
Port 1, Bit 6
Port 2, Bit 5
Port 1, Bit 5
Port 2, Bit 6
Port 2, Bit 7
Not Connected
Port 3, Bit 1
Port 3, Bit 2
Port 3, Bit 3
Port 3, Bit 4
Power Supply
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
DSP0
P36
P13
P37
P40
P12
P06
P41
P42
N/C
P43
P44
P45
P53
P46
P11
P47
P10
PWM
R//W
/RESET
/AS
ANGND
VREF-
DSP User Output 0
Port 3, Bit 7
Port 1, Bit 3
Port 3, Bit 7
Port 4, Bit 0
Port 1, Bit 2
Port 0, Bit 6
Port 4, Bit 1
Port 4, Bit 2
Not Connected
Port 4, Bit 3
Port 4, Bit 4
Port 4, Bit 5
Port 5, Bit 3
Port 4, Bit 6
Port 1, Bit 1
Port 4, Bit 7
Port 1, Bit 0
Pulse Width Modulator
Read/Write
Reset
Address Strobe
Analog Ground
Analog Voltage Ref.
Output
Output
Input/Output
Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
59
ANIN
Analog Input
Input
60
VREF+
Analog Voltage Ref.
Input
61
ANVDD
Analog Power Supply
32
33
34
P35
P14
DSP1
Port 3, Bit 5
Port 1, Bit 4
DSP User Output 1
Output
Input/Output
Output
62
63
64
65
66
67
68
GND
P07
P20
P21
P52
P51
/DS
Ground
Port 0, Bit 7
Port 2, Bit 0
Port 2, Bit 1
Port 5, Bit 2
Port 5, Bit 1
Data Strobe
DS97TAD0300
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input
Input
Output
PRELIMINARY
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
Output
Input/Output
Output
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
1-5
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
P04
VDD
VDD
/DS
ANVDD
P50
5
4
3
2
1
68 67 66 65 64 63 62 61
60
P07
P57
6
P20
P03
7
P21
P02
8
P52
P01
9
P51
P00
GND
Zilog
XTAL2
10
XTAL1
11
59
ANIN
P22
12
58
VREF-
P56
13
57
ANGND
P23
14
56
/AS
P55
15
55
/RESET
P54
16
54
R//W
GND
17
53
PWM
P17
18
52
P10
P05
19
51
P47
P24
20
50
P11
P16
21
49
P46
P25
22
48
P53
P15
23
47
P45
P26
24
46
P44
P27
25
45
P43
SCLK
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
/SYNC
P42
P41
P06
P12
P40
P37
P13
P36
DSP0
DSP1
P14
P35
VDD
P34
P33
P32
P31
Z89136
VREF+
Figure 3. Z89136 68-Pin PLCC Pin Assignments
1-6
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Table 2. Z89136 68-Pin Plastic Leaded Chip Carrier,
Pin Identification
Pin # Symbol Function
Direction
1
VDD
Power Supply
2
VDD
Power Supply
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
P04
P50
P57
P03
P02
P01
P00
XTAL2
XTAL1
P22
P56
P23
P55
P54
GND
P17
P05
P24
P16
P25
P15
P26
P27
SCLK
P31
P32
P33
P34
VDD
Port 0, Bit 4
Port 5, Bit 0
Port 5, Bit 7
Port 0, Bit 3
Port 0, Bit 2
Port 0, Bit 1
Port 0, Bit 0
Crystal Oscillator Clock
Crystal Oscillator Clock
Port 2, Bit 2
Port 5, Bit 6
Port 2, Bit 3
Port 5, Bit 5
Port 5, Bit 4
Ground
Port 1, Bit 7
Port 0, Bit 5
Port 2, Bit 4
Port 1, Bit 6
Port 2, Bit 5
Port 1, Bit 5
Port 2, Bit 6
Port 2, Bit 7
System Clock
Port 3, Bit 1
Port 3, Bit 2
Port 3, Bit 3
Port 3, Bit 4
Power Supply
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
32
33
34
P35
P14
DSP1
Port 3, Bit 5
Port 1, Bit 4
DSP User Output 1
Output
Input/Output
Output
DS97TAD0300
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
Input
Input
Input
Output
Table 2. Z89136 68-Pin Plastic Leaded Chip Carrier,
Pin Identification
Pin # Symbol Function
Direction
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
DSP0
P36
P13
P37
P40
P12
P06
P41
P42
/SYNC
P43
P44
P45
P53
P46
P11
P47
P10
PWM
R//W
/RESET
/AS
ANGND
VREF-
DSP User Output 0
Port 3, Bit 7
Port 1, Bit 3
Port 3, Bit 7
Port 4, Bit 0
Port 1, Bit 2
Port 0, Bit 6
Port 4, Bit 1
Port 4, Bit 2
Synchronization Pin
Port 4, Bit 3
Port 4, Bit 4
Port 4, Bit 5
Port 5, Bit 3
Port 4, Bit 6
Port 1, Bit 1
Port 4, Bit 7
Port 1, Bit 0
Pulse Width Modulator
Read/Write
Reset
Address Strobe
Analog Ground
Analog Voltage Ref.
Output
Output
Input/Output
Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
Output
Input/Output
Output
59
ANIN
Analog Input
Input
60
VREF+
Analog Voltage Ref.
Input
61
ANVDD
Analog Power Supply
62
63
64
65
66
67
68
GND
P07
P20
P21
P52
P51
/DS
Ground
Port 0, Bit 7
Port 2, Bit 0
Port 2, Bit 1
Port 5, Bit 2
Port 5, Bit 1
Data Strobe
PRELIMINARY
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
1-7
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
A/D CONVERTER (ADC)
Figure 4 shows the input circuit of the ADC. When conversion starts, the analog input voltage from the input is connected to the MSB and LSB flash converter inputs as
shown in the Input Impedance CKT diagram. Shunting 31
parallel internal resistances of the analog switches and simultaneously charging 31 parallel 1 pF capacitors is equivalent to a 400 Ohms input impedance in parallel with a 31
pF capacitor. Other input stray capacitance adds about 10
pF to the input load. Input source resistances up to 2 Kohms can be used under normal operating conditions without any degradation of the input settling time. For larger input source resistance, longer conversion cycle times may
be required to compensate the input settling time problem.
VREF is set using the VREF + pin.
CMOS Switch
on Resistance
2-5k Ω
V Ref
R Source
C .5 pF
V Ref
C .5 pF
C Parasitic
V Ref
31 CMOS Digital
Comparators
C .5 pF
Figure 4. Input Impedance of ADC
ABSOLUTE MAXIMUM RATINGS
Symbol
Description
Min
Max
Units
VCC
Supply Voltage (*)
–0.3
+7.0
V
TSTG
Storage Temp
–65°
+150°
C
†
C
TA
Oper Ambient Temp
Notes:
Voltage on all pins with respect to GND.
† See Ordering Information.
1-8
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period
may affect device reliability.
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Figure 5).
1
+5V
2.1 kΩ
From Output
Under Test
150 pF
9.1 kΩ
Figure 5. Test Load Diagram
CAPACITANCE
TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter
Min
Max
0
0
0
12 pF
12 pF
12 pF
Input capacitance
Output capacitance
I/O capacitance
DC ELECTRICAL CHARACTERISTICS
Sym
Parameter
VCC
TA = 0°C to +55°C
Min
Max
Typical
@ 25°C
Units
ICC
Supply Current
5.0V
65
40
mA
ICC1
HALT Mode Current
5.0V
20
6
mA
ICC2
STOP Mode Current
5.0V
400
300
µA
Note: 5.0V ±0.25V.
DS97TAD0300
PRELIMINARY
1-9
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
DC ELECTRICAL CHARACTERISTICS
Sym
Parameter
VCC
TA = 0° C to +55°C
Min
Max
Typical
@ 25°C Units
Conditions
VMAX
Max Input Voltage
5.0V
7
VCH
Clock Input High Voltage
5.0V
0.9 VCC
VCC+0.3
2.5
V
VCL
Clock Input Low Voltage
5.0V
GND–0.3
0.1 VCC
1.5
V
VIH
Input High Voltage
5.0V
0.7 VCC
VCC+0.3
2.5
V
VIL
Input Low Voltage
5.0V
GND–0.3
0.2 VCC
1.5
V
VOH
Output High Voltage
5.0V
VCC–0.4
4.8
V
IOH = –2.0 mA
VOL1
Output Low Voltage
5.0V
0.4
0.1
V
IOL = +4.0 mA
VOL2
Output Low Voltage
5.0V
1.2
0.3
V
IOL = +12 mA, 3 Pin Max
VRH
Reset Input High Voltage
5.0V
0.8 VCC
VCC
2.1
V
VRl
Reset Input Low Voltage
5.0V
GND–0.3
0.2 VCC
1.7
VOFFSET
Comparator Input Offset
5.0V
25
10
mV
IIL
Voltage
Input Leakage
5.0V
–5
5
25
µA
VIN = OV, VCC
IOL
Output Leakage
5.0V
–5
5
25
µA
VIN = OV, VCC
IIR
Reset Input Current
5.0V
–55
–30
µA
Driven by External Clock
Generator
Driven by External Clock
Generator
Note: 5.0V ±0.25V
1-10
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
DC ELECTRICAL CHARACTERISTICS
Z89165 A/D Converter
Sym
Parameter
VDD
TA = 0°C to +55°C
Min
Max
1
Units
Conditions
IIL
Input Leakage Analog Input
5.0V
40
µA
ANVDD
VIN
VREFH
VREFL
=
=
=
=
5.50
0.00
5.50
0.00
V
V
V
V
IIH
Input Leakage Analog Input
5.25V
2.00
µA
ANVDD
VIN
VREFH
=
=
=
=
5.50
5.50
5.50
0.00
V
V
V
V
=
=
=
5.50
0.00
5.50
V
V
V
VREFL
VIN
VREFL
ANVDD
IVREFH
Input Current
5.25V
2.00
mA
IVREFL
Input Current
5.25V
80
µA
VIN
VREFL
ANVDD
=
=
=
5.50
5.50
5.50
V
V
V
IVEFL
Input Current
5.25V
-2.00
mA
VIN
VREFH
ANVDD
=
=
=
0.00
5.50
0.00
V
V
V
IVREFL
Input Current
5.25V
-80
µA
VIN
VREFH
ANVDD
=
=
=
0.00
5.50
5.50
V
V
V
DS97TAD0300
PRELIMINARY
1-11
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
DC ELECTRICAL CHARACTERISTICS
21 Other Non-Regular I/O
Sym
Parameter
VDD
TA = 0°C to +55°C
Min
Max
Units
Conditions
IIRH
Input Current ROMless Pin
5.25V
6.00
µA
VIN = 5.25 V
IIR1
Input Current ROMless Pin
5.25V
6.00
µA
VIN = 0.00 V
IIR
5.25V
1.00
mA
VIN = 5.25 V
5.25V
1.00
µA
VIN = 0.00 V
5.25V
1.00
µA
VIN = 5.25 V
IIHX1
Input Current ROMless Pin
During Reset Active
Input Current XTAL2 pin in
STOP Mode
Input Current XTAL2 Pin in
STOP Mode
Input current XTAL1 Pin
5.25V
30
µA
VIN = 0.00 V
IILX1
Input Current XTAL1 Pin
5.25V
30
µA
VIN = 5.25 V
VOLXR
5.25V
1.20
V
IOL = 4.00 mA
5.25V
0.60
V
IOL = 1.00 mA
IIH
Output Low Voltage XTAL2
Reset Inactive
Output Low Voltage XTAL2
Reset Inactive
Output High Voltage XTAL2
Reset Inactive
Output High Voltage XTAL2
Reset Inactive
Input Current P31,P32,P33
5.25V
IIL
Input Current P31, P32, P33
5.25V
IIHX2
IILX2
VOLX
VOHXR
IVOHX
1-12
5.25V
4.00
V
IOH = 4.00 mA
5.25V
4.00
V
IOH =1.00 mA
1.00
µA
VIN = 5.25 V
1.00
µA
VIN = 0.00 V
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
AC CHARACTERISTIC
External I/O or Memory Read and Write Timing Diagram
1
R//W
13
12
Port 0, /DM
16
19
Port 1
3
A7 - A0
1
D7 - D0 IN
2
9
/AS
8
18
11
4
5
/DS
(Read)
6
17
10
Port1
A7 - A0
D7 - D0 OUT
14
15
7
/DS
(Write)
Figure 6. External I/O or Memory Read/Write Timing
DS97TAD0300
PRELIMINARY
1-13
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Table
TA=0°C to +55°C
No
Symbol
Parameter
VCC
Min
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
TdAZ(DS)
TwDSR
TwDSW
TdDSR(DR)
ThDR(DS)
TdDS(A)
TdDS(AS)
TdR/W(AS)
TdDS(R/W)
TdDW(DSW)
TdDS(DW)
TdA(DR)
TdAS(DS)
TdDI(DS)
TdDM(AS)
Address Valid to /AS Rise Delay
/AS Rise to Address Float Delay
/AS Rise to Read Data Req’d Valid
/AS Low Width
Address Float to /DS Fall
/DS (Read) Low Width
/DS (Write) Low Width
/DS Fall to Read Data Req’d Valid
Read Data to /DS Rise Hold Time
/DS Rise to Address Active Delay
/DS Rise to /AS Fall Delay
R//W Valid to /AS Rise Delay
/DS Rise to R//W Not Valid
Write Data Valid to /DS Fall (Write) Delay
/DS Rise to Write Data Not Valid Delay
Address Valid to Read Data Req’d Valid
/AS Rise to /DS Fall Delay
Data Input Setup to /DS Rise
/DM Valid to /AS Fall Delay
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
25
35
Max
150
35
0
125
75
90
0
40
35
25
35
40
25
180
48
50
20
Units
Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2,3
2,3
1,2,3
2,3
1,2,3
1,2,3
1,2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
1,2,3
2,3
1,2,3
2,3
Notes:
1. When using extended memory timing, add 2 TpC.
2. Timing numbers given are for minimum TpC.
3. See clock cycle dependent characteristics table.
5.0V ±0.25V
Standard Test Load
All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
1-14
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
AC ELECTRICAL CHARACTERISTICS
Additional Timing Diagram
1
1
3
Clock
2
7
2
3
7
TIN
4
5
6
IRQN
8
9
Clock
Setup
11
Stop
Mode
Recovery
Source
10
Figure 7. Additional Timing
DS97TAD0300
PRELIMINARY
1-15
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
AC ELECTRICAL CHARACTERISTICS
Additional Timing Table
TA=0°C to +55°C
No
Symbol
Parameter
VCC
Min
1
2
3
4
5
6
7
Input Clock Period
Clock Input Rise & Fall Times
Input Clock Width
Timer Input Low Width
Timer Input High Width
Timer Input Period
Timer Input Rise & Fall Timer
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
48.83
8A
8B
9
10
TpC
TrC,TfC
TwC
TwTinL
TwTinH
TpTin
TrTin,
TfTin
TwIL
TwIL
TwIH
Twsm
5.0V
5.0V
5.0V
5.0V
11
12
Tost
Twdt
Int. Request Low Time
Int. Request Low Time
Int. Request Input High Time
Stop-Mode Recovery Width
Spec
Oscillator Start-up Time
Watch-Dog Timer
70
3TpC
3TpC
12
5TpC
5TpC
5
15
25
100
5.0V
5.0V
5.0V
5.0V
5.0V
Max
6
17
70
3TpC
8TpC
100
Units
Notes
ns
ns
ns
ns
1
1
1
ns
ns
1
1
1
ns
1,2
1
1
1
ms
ms
ms
ms
3
D1 = 0, D0 = 0 [4]
D1 = 0, D0 = 1 [4]
D1 = 1, D0 = 0 [4]
D1 = 1, D0 = 1 [4]
Notes:
1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
2. Interrupt request through Port 3 (P33-P31)
3. SMR-D5 = 0
4. Reg. WDT
5.0V ±0.25V
1-16
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Z89135/136 (ROMless)
Low-Cost DTAD Controller
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AC ELECTRICAL CHARACTERISTICS
Handshake Timing Diagrams
1
Data In Valid
Data In
Next Data In Valid
2
1
3
Delayed DAV
/DAV
(Input)
4
5
RDY
(Output)
6
Delayed RDY
Figure 8. Input Handshake Timing
Data Out Valid
Data Out
Next Data Out Valid
7
/DAV
(Output)
Delayed DAV
8
9
11
10
RDY
(Input)
Delayed
RDY
Figure 9. Output Handshake Timing
DS97TAD0300
PRELIMINARY
1-17
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
AC ELECTRICAL CHARACTERISTICS (Continued)
Handshake Timing Table
No
Symbol
Parameter
VCC
1
2
3
4
5
6
7
8
9
10
11
TsDI(DAV)
ThDI(DAV)
TwDAV
TdDAVI(RDY)
TdDAVId(RDY)
TdDO(DAV)
TcLDAV0(RDY)
TcLDAV0(RDY)
TdRDY0(DAV)
TwRDY
TdRDY0d(DAV)
Data In Setup Time
RDY to Data Hold Time
Data Available Width
DAV Fall to RDY Fall Delay
DAV Rise to RDY Rise Delay
RDY Rise to DAV Fall Delay
Data Out to DAV Fall Delay
DAV Fall to RDY Fall Delay
RDY Fall to DAV Rise Delay
RDY Width
RDY Rise to DAV Fall Delay
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
TA = 0°C to +55°C
Min
Max
0
0
40
70
40
0
TpC
0
70
40
40
Units
Data
Direction
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
Note: 5.0V ±0.25V
1-18
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
AC ELECTRICAL CHARACTERISTICS
A/D Electrical Characteristics
1
TA = 0°C –55°C; VCC = 5.0V ±0.25V
Parameter
Resolution
Integral non-linearity
Differential non-linearity
Zero Error at 25°C
Power Dissipation
Clock Frequency
Clock Pulse Width
Analog Input Voltage Range
Min
Max
Typical
Units
8
0.5
35
ANGND
ANVCC
bits
lsb
lsb
mV
mW
MHz
ns
V
Conversion Time
Input Capacitance on
VAHI range damage
ANGND
2
60
ANVCC
µs
pF
V
VALO range damage
ANGND
ANVCC
V
ANGND
VSS
ANVCC
V
ANVCC
ANGND
VCC
V
DS97TAD0300
1
0.5
50
75
20.48
PRELIMINARY
35
1-19
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
PIN FUCTIONS
/RESET. (input/output, active Low). This pin initializes the
MCU. Reset is accomplished either through Power-On Reset (POR), Watch-Dog Timer reset, Stop-Mode Recovery,
or external reset. During POR and WDT Reset, the internally generated reset is driving the reset pin Low for the
POR time. Any devices driving the reset line must be open
drain to avoid damage from a possible conflict during reset
conditions. A /RESET will reset both the Z8 and the DSP.
XTAL1. Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, RC network or an external single-phase clock to the on-chip oscillator input.
For the Z8:
After the POR time, /RESET is a Schmitt-triggered input.
To avoid asynchronous and noisy reset problems, the Z8
is equipped with a reset filter of four external clocks
(4TpC). If the external reset signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the reset is
detected, an internal RST signal is latched and held for an
internal register count of 18 external clocks, or for the duration of the external reset, whichever is longer. Program
execution begins at location 000CH (Hexadecimal), 5-10
TpC cycles after the /RESET is released. The Z8 does not
reset WDT, SMR, P2M, and P3M registers on a StopMode Recovery operation.
DSP0. (output). DSP0 is a general-purpose output pin
connected to bit 6 of the Analog Control Register (DSP
EXT4). This bit has no special significance and may be
used to output data by writing to bit 6 of the ACR.
For the DSP:
A low level on the /RESET pin generates an internal reset
signal. The /RESET signal must be kept low for at least
one clock cycle. The CPU will fetch a new Program
Counter (PC) value from program memory address
0FFCH after the reset signal is released.
RMLS. ROMless (input, active High). This pin, when connected to VDD, disables the internal Z8 ROM. (Note that,
when pulled Low to GND that part functions normally as
the ROM version). The DSP can not be configured as
ROMless. This pin is only available on the Z89135.
R//W. Read/Write (output, write Low). The R//W signal defines the signal flow when the Z8 is reading or writing to external program or data memory. The Z8 is reading when
this pin is High and writing when this pin is Low.
/AS. Address Strobe (output, active Low). Address Strobe
is pulsed once at the beginning of each machine cycle. Address output is through Port 0/Port 1 for all external programs. Memory address transfers are valid at the trailing
edge of /AS. Under program control, /AS is placed in the
high-impedance state along with Ports 0 and 1, Data
Strobe, and Read/Write.
XTAL2. Crystal 2 (time-based output). This pin connects a
parallel-resonant, crystal, ceramic resonant, or LC network
to the on-chip oscillator output.
DSP1. (output). DSP1 is a general-purpose output pin
connected to bit 7 of the Analog Control Register (DSP
EXT4). This bit has no special significance and may be
used to output data by writing to bit 7 of the ACR.
SCLK. System Clock (output). SCLK outputs the system
clock. This pin is available on the Z89136.
/SYNC. Synchronize (output). This signal indicates the last
clock cycle of the current executing Z8 instruction. This pin
is only available on the Z89136.
PWM. Pulse Width Modulator (output). The PWM is a 10bit resolution D/A converter. This output is a digital signal
with CMOS output levels.
ANIN. (input). Analog input for the A/D converter.
ANVDD. Analog power supply for the A/D converter.
ANGND. Analog ground for the A/D converter.
VREF+. (input). Reference voltage (High) for the A/D converter.
VREF. (input). Reference voltage (Low) for the A/D converter.
VDD. Digital power supply for the Z89135.
GND. Digital ground for the Z89135.
/DS. Data Strobe (output, active Low). Data Strobe is activated once for each external memory transfer. For read
operations, data must be available prior to the trailing edge
of /DS. For write operations, the falling edge of /DS indicates that output data is valid.
1-20
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Z89135/136 (ROMless)
Low-Cost DTAD Controller
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Port 0. (P07-P00). Port 0 is an 8-bit, bidirectional, CMOScompatible port. These eight I/O lines are configured under software control as a nibble I/O port, or as an address
port for interfacing external memory. The input buffers are
Schmitt-triggered and the output drivers are push-pull.
Port 0 is placed under handshake control. In this configuration, Port 3, lines P32 and P35 are used as the handshake control /DAV0 and RDY0. Handshake signal direction is dictated by the I/O direction to Port 0 of the upper
nibble P07-P04. The lower nibble must have the same direction as the upper nibble.
The Auto Latch on Port 0 puts valid CMOS levels on all
CMOS inputs which are not externally driven. Whether this
level is 0 or 1, cannot be determined. A valid CMOS level,
rather than a floating node, reduces excessive supply current flow in the input buffer.
ble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of
Port 0 can be programmed independently as I/O while the
lower nibble is used for addressing. If one or both nibbles
are needed for I/O operation, they are configured by writing to the Port 0 mode register.
In ROMless mode, after a hardware reset, Port 0 is configured as address lines A15-A8, and extended timing is set
to accommodate slow memory access. The initialization
routine can include reconfiguration to eliminate this extended timing mode. (In ROM mode, Port 0 is defined as
input after reset.)
Port 0 is set in the high-impedance mode if selected as an
address output state along with Port 1 and the control signals /AS, /DS and R//W (Figure 10).
For external memory references, Port 0 provides address
bits A11-A8 (lower nibble) or A15-A8 (lower and upper nib-
4
Z89135/136
MCU
Port 0
(I/O or A15 - A8)
4
Handshake Controls
/DAV0 and RDY0
(P32 and P35)
OEN
PAD
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 KΩ
Figure 10. Port 0 Configuration
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1-21
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
PIN FUCTIONS (Continued)
Port 1. (P17-P10). Port 1 is an 8-bit, bidirectional, CMOScompatible port (Figure11). It has multiplexed Address
(A7-A0) and Data (D7-D0) ports. These eight I/O lines are
programmed as inputs or outputs, or can be configured under software control as an Address/Data port for interfacing external memory. The input buffers are Schmitt triggered and the output drivers are push-pull.
mode) are referenced through Port 1. To interface external
memory, Port 1 must be programmed for the multiplexed
Address/Data mode. If more than 256 external locations
are required, Port 0 outputs the additional lines.
Port 1 can be placed in the high-impedance state along
with Port 0, /AS, /DS and R//W, allowing the Z89135/136
to share common resources in multiprocessor and DMA
applications.
Port 1 may be placed under handshake control. In this configuration, Port 3, lines P33 and P34 are used as the handshake controls RDY1 and /DAV1 (Ready and Data Available). Memory locations greater than 24575 (in ROM
8
Z89135/136
MCU
Port 1
(I/O or AD7 - AD0)
Handshake Controls
/DAV2 and RDY2
(P31 and P36)
OEN
PAD
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 KΩ
Figure 11. Port 1 Configuration
1-22
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Z89135/136 (ROMless)
Low-Cost DTAD Controller
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Port 2. (P27-P20). Port 2 is an 8-bit, bidirectional, CMOScompatible I/O port. These eight I/O lines are configured
under software control as an input or output, independently. Port 2 is always available for I/O operation. The input
buffers are Schmitt triggered. Bits programmed as outputs
may be globally programmed as either push-pull or opendrain.
Port 2 may be placed under handshake control. In this configuration, Port 3 lines P31 and P36 are used as the handshake controls lines /DAV2 and RDY2. The handshake
signal assignment for Port 3 lines P31 and P36 is dictated
by the direction (input or output) assigned to bit 7, Port 2
(Figure 12).
The Auto Latch on Port 2 puts valid CMOS levels on all
CMOS inputs which are not externally driven. Whether this
level is 0 or 1, cannot be determined. A valid CMOS level,
rather than a floating node, reduces excessive supply current flow in the input buffer.
Port 2
(I/O)
Z89135/136
MCU
Handshake Controls
/DAV2 and RDY2
(P31 and P36)
Open Drain
OEN
PAD
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 KΩ
Figure 12. Port 2 Configuration
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PRELIMINARY
1-23
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
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PIN FUCTIONS (Continued)
Handshake lines for Ports 0, 1, and 2 are available on P31
through P36.
Port 3. (P37-P31). Port 3 is a 7-bit, CMOS-compatible port
with three fixed inputs (P33-P31) and four fixed outputs
(P37-P34). It is configured under software control for input/output, counter/timers, interrupt, and port handshakes.
Pins P31, P32, and P33 are standard CMOS inputs; outputs are push-pull.
Port 3 also provides the following control functions: handshake for Ports 0, 1, and 2 (/DAV and RDY); three external
interrupt request signals (IRQ3-IRQ1); timer input and output signals (TIN and TOUT); (Figure 13).
Two on-board comparators can process analog signals on
P31 and P32 with reference to the voltage on P33. The analog function is enabled by programming the Port 3 Mode
Register (bit 1). Port 3, pin 3 is a falling edge interrupt input. P31 and P32 are programmable as rising, falling or
both edge-triggered interrupts (IRQ register bits 6 and 7).
P33 is the comparator reference voltage input. Access to
counter/timers 1 is through P31 (TIN) and P36 (TOUT).
Comparator Inputs. Port 3, Pins P31 and P32 each have
a comparator front end. The comparator reference voltage, Pin P33, is common to both comparators. In analog
mode, the P31 and P32 are the positive inputs to the comparators and P33 is the reference voltage supplied to both
comparators. In digital mode, pin P33 can be used as a
P33 register input or IRQ1 source.
Table 3. Port 3 Pin Assignments
Pin
I/O
CTC1
AN IN
Int.
P31
IN
TIN
AN1
IRQ2
P32
P33
P34
P35
P36
IN
IN
OUT
OUT
OUT
AN2
REF
IRQ0
IRQ1
P37
OUT
P0 HS
P1 HS
P2 HS
EXT
D/R
D/R
D/R
R/D
DM
R/D
TOUT
R/D
Notes:
HS = Handshake Signals
D = DAV
R = RDY
1-24
PRELIMINARY
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Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
1
Port 3
(I/O or Control)
Z89135/136
MCU
R247 = P3M
D1
1 = Analog
0 = Digital
DIG.
IRQ2, Tin, P31 Data Latch
P31 (AN1)
+
AN.
-
IRQ0, P32 Data Latch
P32 (AN2)
+
P33 (REF)
-
IRQ1, P33 Data Latch
From Stop Mode
Recovery Source
Figure 13. Port 3 Configuration
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PRELIMINARY
1-25
Z89135/136 (ROMless)
Low-Cost DTAD Controller
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PIN FUCTIONS (Continued)
Port 4. (P47-P40). Port 4 is an 8-bit, bidirectional, CMOScompatible I/O port (Figure 14). These eight I/O lines are
configured under software control as an input or output, independently. Port 4 is always available for I/O operation.
The input buffers are Schmitt-triggered. Bits programmed
as outputs may be globally programmed as either pushpull or open-drain.
Z89135/136
MCU
Port 4 is a bit programmable general-purpose I/O port. The
control registers for Port 4 are mapped into the expanded
register file (Bank F) of the Z8.
Auto Latch. The Auto Latch on Port 4 puts valid CMOS
levels on all CMOS inputs which are not externally driven.
Whether this level is 0 or 1, cannot be determined. A valid
CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer.
Port 4
(I/O)
Open-Drain
OEN
PAD
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 KΩ
Figure 14. Port 4 Configuraton
1-26
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Z89135/136 (ROMless)
Low-Cost DTAD Controller
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Port 5. (P57-P50). Port 5 is an 8-bit, bidirectional, CMOScompatible I/O port (Figure 15). These eight I/O lines are
configured under software control as an input or output, independently. Port 5 is always available for I/O operation.
The input buffers are Schmitt-triggered. Bits programmed
as outputs may be globally programmed as either pushpull or open-drain.
Port 5 is a bit programmable general-purpose I/O port. The
control registers for Port 5 are mapped into the expanded
register file (Bank F) of the Z8.
Auto Latch. The Auto Latch on Port 5 puts valid CMOS
levels on all CMOS inputs which are not externally driven.
Whether this level is 0 or 1, cannot be determined. A valid
CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer.
Z89135/136
MCU
Port 5
(I/O)
Open-Drain
OEN
PAD
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 KΩ
Figure 15. Port 5 Configuration
DS97TAD0300
PRELIMINARY
1-27
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
FUNCTIONAL DESCRIPTION
The Z8 CCP™ core incorporates special functions to enhance the Z8’s application in industrial, scientific research
and advanced technologies applications.
65535
24575
Reset. The device is reset in one of the following conditions:
■
Power-On Reset
■
Watch-Dog Timer
■
Stop-Mode Recovery Source
■
External Reset
Location of
First Byte of
Instruction
Executed
After RESET 12
Program Memory. The Z8 addresses up to 24 KB of internal program memory and 40 KB external memory (Figure
16). The first 12 bytes of program memory are reserved for
the interrupt vectors. These locations contain six 16-bit
vectors that correspond to the five user interrupts and one
DSP interrupt. Byte 12 to byte 24575 consists of on-chip
mask-programmed ROM. At addresses 24576 and greater, the Z8 executes external program memory. In ROMless mode, the Z8 will execute external program memory
beginning at byte 12 and continuing through byte 65535.
External
ROM and RAM
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
On-Chip
ROM
In ROM Mode
11
IRQ5
10
IRQ5
9
IRQ4
8
IRQ4
7
IRQ3
6
IRQ3
5
IRQ2
4
IRQ2
3
IRQ1
2
IRQ1
1
IRQ0
0
IRQ0
Figure 16. Program Memory Map
1-28
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DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
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ROM Protect. The 24 KB of internal program memory for
the Z8 is mask programmable. A ROM protect feature prevents “dumping” of the ROM contents of Program Memory
by inhibiting execution of LDC, LDCI, LDE, and LDEI instructions. The ROM Protect option is mask-programmable, to be selected by the customer at the time when the
ROM code is submitted.
Data Memory. (/DM). In ROM Mode, the Z8 can address
up to 40 KB of external data memory beginning at location
24576 (Figure 17). In ROMless mode, the Z8 can address
the full 64 KB of external data memory beginning at location 12. External data memory may be included with, or
separated from, the external program memory space.
/DM, an optional I/O function that can be programmed to
appear on Port 34, is used to distinguish between data and
program memory space. The state of the /DM signal is
controlled by the type of instruction being executed. An
LDC opcode references PROGRAM (/DM inactive) memory, and an LDE instruction references data (/DM active
Low) memory.
65535
1
External
Data
Memory
24756
Not Addressable
(In ROM Mode)
0
Figure 17. Data Memory Map
DS97TAD0300
PRELIMINARY
1-29
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Register File. The standard Z8 register file consists of four
I/O port registers, 236 general-purpose registers, and 15
control and status registers (R3-R0, R239-R4, and R255R241, respectively). The instructions access registers directly or indirectly through an 8-bit address field. This allows a short, 4-bit register address using the Register
Pointer (Figure 18). In the 4-bit mode, the register file is
divided into 16 working register groups, each occupying 16
continuous locations. The Register Pointer addresses the
starting location of the active working register group (Figure 19).
Note: Register Group E (Registers E0-EF) is only accessed through a working register and indirect addressing
modes.
R253 RP
D7
D6 D5
D4
D3 D2
D1 D0
Expanded Register Bank
Working Register Group
Default setting after RESET = 00000000
Figure 18. Register Pointer Register
r7 r6
r5 r4
r3 r2
r1 r0
Group 15 (F) Control Registers
R255
R253
R240
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group
R239
Group 14 (E)
R223
Group 13 (D)
R79
Group 4 (4)
Group 3 (3)
R63
Specified Working
Register Group
R47
Group 2 (2)
The upper nibble
of the register
file address
provided by the
instruction points
to the specified
working-register
group
R31
Group 1 (1)
R15
Group 0 (0)
I/O Ports
R3
R0
Figure 19. Register Pointer
1-30
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
RAM Protect. The upper portion of the Z8’s RAM address
spaces 80FH to EFH (excluding the control registers) are
protected from reading and writing. The RAM Protect bit
option is mask-programmable and is selected by the customer when the ROM code is submitted. After the mask
option is selected, the user activates from the internal
ROM code to turn off/on the RAM Protect by loading a bit
D6 in the IMR register to either a 0 or a 1, respectively. A
1 in D6 indicates RAM Protect enabled.
Stack. The Z8’s external data memory or the internal register file is used for the stack. The 16-bit Stack Pointer
(R255-R254) is used for the external stack which can reside only from 24576 to 65535 in ROM Mode or 0 to 65535
in ROMless mode. An 8-bit Stack Pointer (R255) is used
for the internal stack that resides within the 236 generalpurpose registers (R239-R4). SPH can be used as a general-purpose register when using internal stack only.
DS97TAD0300
Expanded Register File. The register file on the Z8 has
been expanded to allow for additional system control registers, and for mapping of additional peripheral devices
along with I/O ports into the register address area. The Z8
register address space has now been implemented as 16
banks of 16 registers groups per bank (Figure 20). These
register banks are known as the ERF (Expanded Register
File). Bits 7-4 of register RP (Register Pointer) select the
working register group. Bits 3-0 of register RP select the
expanded register bank (Figure 20).
The SMR register, WDT register, control and data registers for Port 4 and Port 5, and the DSP control register are
located in Bank F of the Expanded Register File. Bank B
of the Expanded Register File consists of the Mailbox Interface in which the Z8 and the DSP communicate. The
rest of the Expanded Register is not physically implemented and is open for future expansion.
PRELIMINARY
1-31
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Z8 STANDARD CONTROL REGISTERS
REGISTER BANK (0)
RESET CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER GROUP 15(F)
FFH
SPL
U
U
U
U
U
U
U
U
FEH
SPH
U
U
U
U
U
U
U
U
FDH
RP
0
0
0
0
0
0
0
0
REGISTER POINTER
7
6
5
4
3
2
1
0
Working Register
Expanded Register
FCH
FLAGS
U
U
U
U
U
U
U
U
Group Pointer
Bank Pointer
FBH
IMR
0
U
U
U
U
U
U
U
FAH
IRQ
0
0
0
0
0
0
0
0
F9H
IPR
U
U
U
U
U
U
U
U
F8H
P01M
0
1
0
0
1
1
0
1
F7H
P3M
0
0
0
0
0
0
0
0
F6H
P2M
1
1
1
1
1
1
1
1
F5H
PRE0
U
U
U
U
U
U
U
0
% F4
T0
U
U
U
U
U
U
U
U
F3H
PRE1
U
U
U
U
U
U
0
0
F2H
T1
U
U
U
U
U
U
U
U
F1H
TMR
0
0
0
0
0
0
0
0
F0H
Reserved
†
*
*
Z8 Reg. File
FFH
FOH
Z8 EXPANDED REGISTER BANK (F)
REGISTER GROUP 0 (0)
*
F
7FH
E
D
C
B
Re
A
se
9
rve
8
d
7
*
6
5
4
3
d
rve
0
se
0FH
00H
Re
2
1
(F) 0FH
WDTMR
(F) 0EH
Reserved
(F) 0DH
Reserved
RESET CONDITION
U
U
U
0
1
1
0
1
(F) 0CH
DSP CON
U
U
U
1
U
U
U
U
(F) 0BH
SMR
0
0
1
0
0
0
0
0
(F) 0AH
Reserved
(F) 09H
Reserved
(F) 08H
Reserved
(F) 07H
Reserved
(F) 06H
P45CON
U
U
U
0
U
U
U
0
(F) 05H
P5M
1
1
1
1
1
1
1
1
(F) 04H
P5
U
U
U
U
U
U
U
U
(F) 03H
P4M
1
1
1
1
1
1
1
1
(F) 02H
P4
U
U
U
U
U
U
U
U
(F) 01H
Reserved
(F) 00H
PCON
1
1
1
1
1
1
1
0
Z8 EXPANDED REGISTER BANK (B)
Z8-DSP
Mailbox Interface
(R0...R15)
Z8 STANDARD REGISTER BANK (0)
REGISTER GROUP 0
*
*
*
*
RESET CONDITION
(0) 03H
P3
1
1
1
1
U
U
U
U
(0) 02H
P2
U
U
U
U
U
U
U
U
(0) 01H
P1
U
U
U
U
U
U
U
U
(0) 00H
P0
U
U
U
U
U
U
U
U
U = Unknown
† = For ROMless mode, RESET Condition 10110110
*
Will not be Reset with a Stop-Mode Recovery
Figure 20. Expanded Register File Architecture
1-32
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
1
IRQ0 IRQ2
IRQ1, 3, 4, 5
Interrupt
Edge
Select
IRQ Register
(D6, D7)
IRQ
IMR
6
IPR
Global
Interrupt
Enable
Interrupt
Request
Priority
Logic
Vector Select
Figure 21. Interrupt Block Diagram
Table 4. Interrupt Types, Sources, and Vectors
Name
Source
IRQ0
IRQ1
IRQ2
/DAV0, P32, AN2
/DAV1, P33
/DAV2, P31,TIN, AN2
IRQ3
IRQ4
IRQ5
IRQ3
T0
TI
DS97TAD0300
Vector Location Comments
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
External (P32), Programmable Rise or Fall Edge Triggered
External (P33), Fall Edge Triggered
External (P31), Programmable Rise or Fall Edge Triggered
Internal (DSP activated), Fall Edge Triggered
Internal
Internal
PRELIMINARY
1-33
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z8 has six different interrupts from six different sources. The interrupts are maskable and prioritized
(Figure 21). The six sources are divided as follows; three
sources are claimed by Port 3 lines P33-P31, two in
counter/timers, and one by the DSP (Table 4). The Interrupt Mask Register globally or individually enables or disables the six interrupt requests.When more than one interrupt is pending, priorities are resolved by a programmable
priority encoder that is controlled by the Interrupt Priority
Register. An interrupt machine cycle is activated when an
interrupt request is granted. This disables all subsequent
interrupts, pushes the Program Counter and Status Flags
to the stack, and then branches to the program memory
vector location reserved for that interrupt.
All Z8 interrupts are vectored through locations in the program memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request Register is polled to determine which
of the interrupt requests need service.
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 may be rising, falling or both edge triggered, and are programmable by the user. The software
may poll to identify the state of the pin.
Programming bits for the Interrupt Edge Select is located
in the IRQ Register (R250), bits D7 and D6. The configuration is shown in Table 5.
Table 5. IRQ Register
IRQ
D7
0
0
1
1
D6
0
1
0
1
P31
F
F
R
R/F
P32
F
R
F
R/F
Notes:
F = Falling Edge
R = Rising Edge
Clock. The Z89135/136 on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a crystal, LC,
ceramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal should be
AT cut, 20.48 MHz max., with a series resistance (RS) less
than or equal to 100 Ohms. The system clock (SCLK) is
one half the crystal frequency.
The crystal is connected across XTAL1 and XTAL2 using
capacitors from each pin to ground.
XTAL1
C1
Interrupt Edge
XTAL1
XTAL1
XTAL2
XTAL2
C1
L
XTAL2
C2
C2
Ceramic Resonator or
Crystal
LC
External Clock
Figure 22. Oscillator Configuration
1-34
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Counter/Timers. There are two 8-bit programmable
counter/timers (T0-T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the T0 prescaler is
driven by the internal clock only (Figure 23).
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each
prescaler drives its counter, which decrements the value
(1 to 256) that has been loaded into the counter. When the
counter reaches the end of the count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated.
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode).
The counters, but not the prescalers, are read at any time
without disturbing their value or count mode. The clock
source for T1 is user-definable and is either the internal microprocessor clock divided by four, or an external signal input through Port 31. The Timer Mode register configures
the external timer input (P31) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or
as a gate input for the internal clock. The counter/timers
can be cascaded by connecting the T0 output to the input
of T1.
The counters can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters can
also be programmed to stop upon reaching zero (single
DSP Clock
÷2
÷2
OSC
D7, D6
(F) OC
Internal Data Bus
(DSP CON)
T0, T2, T3
÷2
Write
D0,D1
(SMR)
Write
Read
PRE0
Initial Value
Register
T0
Initial Value
Register
6-Bit
Down
Counter
8-bit
Down
Counter
T0
Current Value
Register
÷ 16
÷4
Internal
Clock
IRQ4
TOUT
P36
÷2
External Clock
Clock
Logic
÷4
Internal Clock
Gated Clock
Triggered Clock
TIN P31
Write
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
Write
IRQ5
T1
Current Value
Register
Read
Internal Data Bus
Figure 23. Counter/Timer Block Diagram
DS97TAD0300
PRELIMINARY
1-35
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Port Configuration Register (PCON). The PCON register configures the port individually; comparator output is
on Port 3. The PCON register is located in the Expanded
Register File at Bank F, location 00H (Figure 24).
Comparator Output Port 3 (D0). Bit 0 controls the comparator use in Port 3. A 1 in this location brings the comparator outputs to P34 and P35, and a 0 releases the Port
to its standard I/O configuration.
PCON (F) %00
D7 D6 D5 D4 D3 D2
D1 D0
R Always "1"
W 0 P34,P37 Standard output
1 P34,P37 Comparator output
R Always "1"
W No effect
Note: Reset condition is 11111110
Figure 24. Port Configuration Register (PCON)
Port 4 and 5 Configuration Register (P45CON). The
P45CON register configures Port 4 and Port 5, individually, to open-drain or push-pull active. This register is located
in the Expanded Register File at Bank F, location 06H
(Figure 25).
Port 4 Open-Drain (D0). Port 4 can be configured as an
open-drain by resetting this bit (D0 = 0) or configured as
push-pull active by setting this bit (D0 = 1). The default value is 1.
Port 5 Open-Drain (D4). Port 5 can be configured as an
open-drain by resetting this bit (D4 = 0) or configured as
push-pull active by setting this bit (D4 = 1). The default value is 1.
P45M (FH) 06H
(Write only)
D7 D6 D5 D4 D3
D2 D1 D0
Port 4 Configuration Bit
0 Open-Drain
1 Push-pull
No effect
Port 5 Configuration Bit
0 Open-Drain
1 Push-pull
No effect
Figure 25. Port 4 and 5 Configuration Register (F) 06H (Write Only)
1-36
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR time allows VCC and
the oscillator circuit to stabilize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one
of three conditions:
■
Power fail to Power OK status
■
Stop-Mode Recovery (if D5 of SMR=1)
■
WDT time-out.
The POR time is a nominal 5 ms. Bit 5 of the Stop-Mode
Register determines whether the POR timer is bypassed
after Stop-Mode Recovery (typical for external clock,
RC/LC oscillators).
STOP. This instruction turns off the internal clock and external crystal oscillation. It reduces the standby current to
300 µA or less. The STOP Mode is terminated by a reset
only, either by WDT time-out, POR, SMR recovery or external reset. This causes the processor to restart the application program at address 000CH. In order to enter STOP
(or HALT) Mode, it is necessary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction.
To do this, the user must execute a NOP (opcode=FFH)
immediately before the appropriate sleep instruction, for
example:
FF
6F
NOP
STOP
FF
7F
NOP
HALT
;clear the pipeline
;enter STOP Mode
or
;clear the pipeline
;enter HALT Mode
HALT. HALT turns off the internal CPU clock, but not the
XTAL oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The devices are recovered by interrupts, either externally or internally generated.
DS97TAD0300
PRELIMINARY
1-37
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Stop-Mode Recovery Register (SMR). This register selects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 26). All bits are Write Only,
except bit 7 which is Read Only. Bit 7 is a flag bit that is
hardware set on the condition of Stop recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or
a high level is required from the recovery source. Bit 5 con-
trols the reset delay after recovery. Bits 2, 3, and 4, or the
SMR register, specify the source of the Stop-Mode Recovery signal. Bits 0 and 1 determine the time-out period of the
WDT. The SMR is located in Bank F of the Expanded Register Group at address 0BH.
SMR (FH) 0BH
D7 D6 D5 D4 D3 D2 D1 D0
W 00 SCLK/TCLK Not Divide by 16†
01 SCLK/TCLK Not Divide by 16
10 SCLK/TCLK Divide by 16
11 SCLK/TCLK Divide by 16
R Always "1"
W 000 POR only*
001 No effect
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
R Always "1"
W 0 Stop delay on*
1 Stop delay off
R Always "1"
W 0 Low Stop Recovery Level*
1 High Stop Recovery Level
R Always "1"
W No effect
R 0 POR*
1 Stop-Mode Recovery
* Default Setting After Reset
† Reset After Stop-Mode Recovery
Figure 26. Stop-Mode Recovery Register (SMR)
1-38
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
SCLK/TCLK divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power
consumption during normal processor execution (SCLK
control) and/or HALT Mode (where TCLK sources
counter/timers and interrupt logic).
Stop-Mode Recovery Source (D4-D2). These three bits
of the SMR specify the wake-up source of the Stop-Mode
Recovery (Figure 27 and Table 6).
SMR D4 D3 D2
0 0 0
SMR D4 D3 D2 SMR D4 D3 D2
0 1 0
1 0 0
0 1 1
VDD
P31
P32
P33
SMR D4 D3 D2
1 0 1
SMR D4 D3 D2
1 1 0
P20
P20
P23
P27
SMR D4 D3 D2
1 1 1
P27
To POR
RESET
Stop-Mode Recovery Edge
Select (SMR)
To P33 Data
Latch and IRQ1
MUX
P33 From Pads
Digital/Analog Mode
Select (P3M)
Figure 27. Stop-Mode Recovery Source
Table 6. Stop-Mode Recovery Source
SMR:432
D4
D3
D2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DS97TAD0300
Operation
Description of Action
POR and/or external reset recovery
No effect
P31 transition
P32 transition
P33 transition
P27 transition
Logical NOR of P20 through P23
Logical NOR of P20 through P27
Stop-Mode Recovery Delay Select (D5). This bit, if High,
disables the 5 ms /RESET delay after Stop-Mode Recovery. The default configuration of this bit is one. If the “fast”
wake-up is selected, the Stop-Mode Recovery source is
kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select (D6). A 1 in this bit position indicates that a high level on any one of the recovery
sources wakes the Z89165 from STOP Mode. A 0 indicates low level recovery. The default is 0 on POR .
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP Mode. It is active High, and is 0 (cold)
on POR/WDT /RESET. This bit is Read Only. It is used to
distinguish between cold or warm start.
PRELIMINARY
1-39
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
DSP Control Register (DSPCON). The DSPCON register
controls various aspects of the Z8 and the DSP. It can configure the internal system clock (SCLK) or the Z8, RESET,
and HALT of the DSP, and control the interrupt interface
between the Z8 and the DSP (Table 7).
Table 7. DSP Control Register
(F) 0CH [Read/Write]
Field
DSPCON (F)0CH
Position
Attrib
Value
Z8_SCLK
76------
R/W
00
01
1x
DSP_Reset
--5-----
R
W
DSP_Run
---4----
R/W
Reserved
----32--
W
R
IntFeedback
------1-
R
W
IntFeedback
1
0
R
W
-------0
Z8 IRQ3 (D0). This bit, when read, indicates the status of
Z8 IRQ3. Z8 IRQ3 is set by the DSP by writing to D9 of
DSP External Register 4 (ICR). By writing a 1 to this bit, Z8
IRQ3 is Reset.
DSP INT2 (D1). This bit is linked to DSP INT2. Writing a 1
to this bit sets DSP INT2. Reading this bit indicates the status of DSP INT2.
0
1
0
1
1
0
Label
2.5 MHz (OSC/8)
5 MHz (OSC/4)
10 MHz (OSC/2)
Return “0
No effect
Reset DSP
HALT_DSP
Run_DSP
No effect
Return “0”
No effect
FB_DSP_INT2
Set DSP_INT2
No effect
FB_Z8_IRQ3
Clear IRQ3
No effect
DSP RESET (D5). Setting this bit to 1 will reset the DSP.
If the DSP was in HALT Mode, this bit is automatically preset to 1. Writing a 0 has no effect.
Z8 SCLK (D8-D7). These bits define the SCLK frequency
of the Z8. The oscillator can be divided by 8, 4, or 2. After
a reset, both of these bits are defaulted to 00.
DSP RUN (D4). This bit defines the HALT Mode of the
DSP. If this bit is set to 0, then the DSP clock is turned off
to minimize power consumption. After this bit is set to 1,
then the DSP will continue code execution from where it
was halted. After a hardware reset, this bit is reset to 1.
1-40
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT is initially enabled by
executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT circuit
is driven by an on-board RC oscillator or external oscillator
from the XTAL1 pin. The POR clock source is selected
with bit 4 of the WDT register (Figure 28). The WDTMR is
accessable only within 64 Z8 clock cyles after POR.
WDTMR (FH) 0FH
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP
00
01 *
10
11
INT RC OSC External Clock
5 ms
256 TpC
15 ms
512 TpC
25 ms
1024 TpC
100 ms
4096 TpC
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC *
1 XTAL
W No Effect
R Alway "1"
* Default setting after RESET
Figure 28. Watch-Dog Timer Mode Register
DS97TAD0300
PRELIMINARY
1-41
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
WDT Time Select (D0,D1). Selects the WDT time period.
It is configured as shown in Table 8.
WDT During Halt (D2). This bit determines whether or not
the WDT is active during HALT Mode. A 1 indicates active
during HALT. The default is 1.
Table 8. WDT Time Select
D1
D0
Time-out of
Internal RC OSC
0
0
1
1
0
1
0
1
5 ms min
15 ms min
25 ms min
100 ms min
Time-out of
XTAL clock
256 TpC
512 TpC
1024 TpC
4096 TpC
WDT During Stop (D3). This bit determines whether or
not the WDT is active during STOP Mode. Since XTAL
clock is stopped during STOP Mode, the on-board RC has
to be selected as the clock source to the POR counter. A
1 indicates active during STOP. The default is 1.
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1. The default configuration of this bit is 0 which selects the RC oscillator
Notes:
TpC = XTAL clock cycle
The default on reset is 15 ms.
.
/RESET
4 Clock
Filter
Clear
CLK
18 Clock RESET
Generator
RESET
Internal
RESET
WDT Select
(WDTMR)
WDT TAP SELECT
CK Source
Select
(WDTMR)
XTAL
M
U
X
RC
OSC.
VDD
+
2V REF.
-
From Stop
Mode
Recovery
Source
5 ms POR 5 ms 15 ms 25 ms 100 ms
CK
WDT/POR Counter Chain
CLR
2V Operating
Voltage Det.
12 ns Glitch Filter
WDT
Stop Delay
Select (SMR)
Figure 29. Resets and WDT
1-42
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
DSP REGISTERS DESCRIPTION
General. The DSP is a high-performance second generation CMOS Digital Signal Processor with a modified Harvard-type architecture with separate program and data
ports. The design has been optimized for processing power and saving silicon space.
Registers. The DSP has eight internal registers and seven external registers. The external registers are for the A/D
and D/A converters, and the mailbox and interrupt interfac-
ing between DSP to the Z8. External registers are accessed in one machine cycle, the same as internal registers.
DSP Registers
There are 15 internal and extended 16-bit registers which
are defined in Table 9.
Table 9. DSP Registers
Register
Attribute
Register Definition
BUS
X
Y
A
SR
SP
PC
P
EXT0
Read
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
Read
Write
Read
Write
Read
Write
Read
Write
Read/Write
Read
Write
Read/Write
Data-Bus
X Multiplier Input, 16-Bit
Y Multiplier Input, 16-Bit
Accumulator, 24-Bit
Status Register
Stack Pointer
Program Counter
Output of MAC, 24-Bit
Z8 ERF Bank B, Register 00-01 (from Z8)
Z8 ERF Bank B, Register 08-09 (to Z8)
Z8 ERF Bank B, Register 02-03 (from Z8)
Z8 ERF Bank B, Register 0A-0B (to Z8)
Z8 ERF Bank B, Register 04-05 (from Z8)
Z8 ERF Bank B, Register 0C-0D (to Z8)
Z8 ERF Bank B, Register 06-07 (from Z8)
Z8 ERF Bank B, Register 0E-0F (to Z8)
DSP Interrupt Control Register
A/D Converter
D/A Converter
Analog Control Register
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT3-EXT0. (External Registers 3-0) are the MailBox
Registers in which the DSP and the Z8 communicate.
These four 16 bit registers correspond to the eight outgoing and eight incoming 8-bit registers in Bank B of the Z8’s
Expanded Register File.
EXT5. (D/A and A/D Data Register) is used by both D/A
and A/D converters. The D/A converter will be loaded by
writing to this register, while the A/D converter will be addressed by reading from this register. The Register EXT5
is accessible by the DSP only.
EXT4. (DSP Interrupt Control Register (ICR)) controls the
interrupts in the DSP as well as the interrupts in common
between the DSP and the Z8. It is accessible by the DSP
only, except for the bit F and bit 9.
EXT6. (Analog Control Register) controls the D/A and A/D
converters. It is a read/write register accessible by the
DSP only.
DS97TAD0300
PRELIMINARY
1-43
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Outgoing Registers
(B)00, (B)01
(B)02, (B)03
EXT0
(B)04, (B)05
(B)06, (B)07
EXT2
EXT1
EXT3
Incoming Registers
EXT0
EXT1
EXT2
(B)0C, (B)0D
(B)0E, (B)0F
(F)0C
EXT3
DSP Interrupt Control Register
EXT4
DSP Data Bus
Z8 Data Bus
(B)08, (B)09
(B)0A, (B)0B
D7, D1
D/A and A/D Data Registers
D9
EXT5
D2
Analog Control Register
EXT6
Figure 30. Z8-DSP Interface
DSP-Z8 MAILBOX
To receive information from the DSP, the Z8 uses eight incoming registers which are mapped in the Z8 extended
Register File (Bank B, 08 to 0F). The DSP treats these as
four 16-bit registers that correspond to the eight incoming
Z8 registers (Figure 30).
Both the outgoing registers and the incoming registers
share the same DSP address (EXT3-EXT0).
The Z8 can supply the DSP with data through eight outgoing registers mapped into both the Z8 Expanded Register
File (Bank B, Registers 00 to 07) and the external register
interface of the DSP. These registers are Read/Write and
can be used as general-purpose registers of the Z8. The
DSP can only read information from these registers. Since
the DSP uses a 16-bit data format and the Z8 an 8-bit data
format, eight outgoing registers of the Z8 correspond to
four DSP registers. The DSP can only read information
from the outgoing registers.
Note: The Z8 can read and write to ERF Bank B R00-R07,
Registers 08-0F are Read Only from the Z8.
1-44
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Table 10. Z8 Outgoing Registers
(Read Only from DSP)
Field
Outgoing [0]
Outgoing [1]
Outgoing [2]
Outgoing [3]
Outgoing [4]
Outgoing [5]
Outgoing [6]
Outgoing [7]
(B)00
(B)01
(B)02
(B)03
(B)04
(B)05
(B)06
(B)07
Position
Attrib
Value
Label
76543210
76543210
76543210
76543210
76543210
76543210
76543210
76543210
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
%NN
%NN
%NN
%NN
%NN
%NN
%NN
%NN
(B)00/DSP_ext0_hi
(B)01/DSP_ext0_lo
(B)02/DSP_ext1_hi
(B)03/DSP_ext1_lo
(B)04/DSP_ext2_hi
(B)05/DSP_ext2_lo
(B)06/DSP_ext3_hi
(B)07/DSP_ext3_lo
1
Table 11. Z8 Incoming Registers
(Write Only from DSP
Field
Position
Attrib
Value
Label
Incoming [8] (B)08
76543210
%NN
Incoming [9] (B)09
76543210
Incoming [a] (B)0A
76543210
Incoming [b] (B)0B
76543210
Incoming [c] (B)0C
76543210
Incoming [d] (B)0D
76543210
Incoming [e] (B)0E
76543210
Incoming [f] (B)0F
76543210
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
DSP_ext0_hi
No Effect
DSP_ext0_lo
No Effect
DSP_ext1_hi
No Effect
DSP_ext1_lo
No Effect
DSP_ext2_hi
No Effect
DSP_ext2_lo
No Effect
DSP_ext3_hi
No Effect
DSP_ext3_lo
No Effect
%NN
%NN
%NN
%NN
%NN
%NN
%NN
.
Table 12.
Field
DSP_ext0
Mail Box
DSP_ext1
Mail Box
DSP_ext2
Mail Box
DSP_ext3
Mail Box
DS97TAD0300
DSP Mailbox Registers
Position
Attrib
Value
fedcba9876543210
R
W
R
W
R
W
R
W
%NNNN
fedcba9876543210
fedcba9876543210
fedcba9876543210
PRELIMINARY
%NNNN
%NNNN
%NNNN
Label
(B)00, (B)01
(B)08, (B)09
(B)02, (B)03
(B)0A, (B)0B
(B)04, (B)05
(B)0C, (B)0D
(B)06, (B)07
(B)0E, (B)0F
1-45
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
DSP INTERRUPTS
The DSP processor has three interrupt sources (INT2,
INT1, INT0) (Figure 31). These sources have different priority levels (Figure 32). The highest priority, the next lower
and the lowest priority level are assigned to INT2, INT1
and INT0, respectively. The DSP does not allow interrupt
nesting (interrupting service routines that are currently be-
ing executed). When two interrupt requests occur simultaneously the DSP starts servicing the interrupt with the
highest priority level. Figure 33 shows the interprocessor
interrupts mechanism.
INT2
Z8_INT
A/D INT
Interrupt Priority Logic
INT2
INT1
Interrupt Request Logic
Interrupt Mask Logic
INT0
D/A INT
IPR2
INT1
INT0
CLEAR_INT0
IPR1
CLEAR_INT1
IPR0
CLEAR_INT2
FB DSP
FeedBack Z8_INT MPX
ENABLE_INT
Figure 31. DSP Interrupts
INT0
INT1
INT2
DSP Execution
INT2
INT0
INT1
INT2
Figure 32. DSP Interrupt Priority Structure
Z8 Side
DSP Side
On the Z8, set D1 to
interrupt DSP via DSP INT2.
DSP INT2
DSP CON
1
After serving IRQ3,
set D0 to clear the
interrupt request.
0
9
After serving INT2,
set D4 to clear the
interrupt request.
ICR
(EXT4)
4
The DSP sets D9 to
interrupt Z8 via Z8 IRQ3.
IRQ3 of the Z8
Figure 33. Interprocessor Interrupts Structure
1-46
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Table 13.
Field
EXT4 DSP Interrupt Control Register (ICR) Definition
Position
Attrib
Value
DSP_IRQ2
f---------------
R
1
0
DSP_IRQ1
f---------------e--------------
W
R
DSP_IRQ0
-e---------------d-------------
W
R
DSP_MaskINT2
--d---------------c------------
W
R/W
DSP_MaskINT1
----b-----------
R/W
DSP_MaskINT0
-----a----------
R/W
Z8_IRQ3
------9--------------9---------
R
W
DSPintEnable
-------8--------
R/W
DSP_IPR2
DSP_IPR1
DSP_IPR0
Clear_IRQ2
--------7---------------6---------------5---------------4--------------4----
R/W
R/W
R/W
R
W
------------3--------------3---
R
W
-------------2--------------2--
R
W
--------------10
W
R
Clear_IRQ1
Clear_IRQ0
Reserved
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Binary
Binary
Binary
1
0
1
0
1
0
1
Label
Set_IRQ2
Reset_IRQ2
No effect
Set_IRQ1
Reset_IRQ1
No effect
Set_IRQ0
Reset_IRQ0
No effect
Enable_INT2
Disable_INT2
Enable_INT1
Disable_INT1
Enable_INT0
Disable_INT0
Return "0"
Set_Z8_IRQ3
Reset_Z8_IRQ3
Enable
Disable
IPR2
IPR1
IPR0
Return "0"
Clear_IRQ2
Has_no_effect
Return "0"
Clear_IRQ1
No effect
Return "0"
Clear_IRQ0
No effect
No effect "0"
Interrupt Control Register (ICR). The ICR is mapped into
EXT4 of the DSP (Table 13). The bits are defined as follows:
output register (conversion done). This bit asserts IRQ1 of
the DSP and can be cleared by writing to the
Clear_IRQ1bit.
DSP_IRQ2 (Z8 Interrupt). This bit can be read by both Z8
and DSP and can be set only by writing to the Z8 expanded Register File (Bank F, ROC, bit 0). This bit asserts IRQ2
of the DSP and can be cleared by writing to the
Clear_IRQ2 bit.
DSP_IRQ0 (D/A Interrupt). This bit can be read by DSP
only and is set by Timer3. This bit assists IRQ0 of the DSP
and can be cleared by writing to the Clear_IRQ0 bit.
DSP_IRQ1 (A/D Interrupt). This bit can be read by the
DSP only and is set when valid data is present at the A/D
DS97TAD0300
DSP_MaskIntX. These bits can be accessed by the DSP
only. Writing a 1 to these locations allows the INT to be
serviced, while writing a 0 masks the corresponding INT
off.
PRELIMINARY
1-47
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Z8_IRQ3. This bit can be read from both Z8 and DSP and
can be set by DSP only. Addressing this location accesses
bit D3 of the Z8 IRQ register, hence this bit is not implemented in the ICR. During the interrupt service routine executed on the Z8 side, the User has to reset the Z8_IRQ3
bit by writing a 1 to bit D0 of the DSPCON. The hardware
of the Z89165/C66 automatically resets Z8_IRQ3 bit three
instructions of the Z8 after 1 is written to its location in register bank 0F. This delay provides the timing synchronization between the Z8 and the DSP sides during interrupts.
In summary, the interrupt service routine of the Z8 for IRQ3
should be finished by:
LD
OR
POP
IRET
DSP Enable_INT. Writing a 1 to this location enables global interrupts of the DSP while writing 0 disables them. A
system Reset globally disables all interrupts.
DSP_IPRX. This three-bit group defines the Interrupt Selection logic according to Table 14.
Clear_IRQX. These bits can be accessed by the DSP
only. Writing a 1 to these locations rests the corresponding
DSP_IRQX bits to 0. Clear_IRQX are virtual bits and are
not implemented.
;RP,#%0F
;r12,#%01
;RP
;
Table 14. DSP Interrupt Selection
DSP_IPR[2-0]
2 1 0
Z8_INT is
switched to
A/D_INT is
switched to
D/A_INT is
switched to
000
001
010
011
100
101
110
111
INT2
INT1
INT2
INT1
INT0
INT0
Reserved
Reserved
INT1
INT2
INT0
INT0
INT2
INT1
Reserved
Reserved
INT0
INT0
INT1
INT2
INT1
INT2
Reserved
Reserved
DSP ANALOG DATA REGISTERS
The D/A conversion is DSP driven by sending 10-bit data
to the EXT5 of the DSP. The six remaining bits of EXT5 are
not used (Figure 34).
F
E
D
C
B
A
9
8
7
6
A/D supplies 8-bit data to the DSP through the register
EXT5 of the DSP. From the 16 bits of EXT5, only bits 2
through 9 are used by the A/D (Figure 35). Bits 0 and 1 are
padded with zeroes
5
4
3
2
1
0
10-Bit Data for D/A
(Write Only)
Reserved
Figure 34. EXT5 Regoster D/A Mode Definition
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Reserved
8-Bit Data From A/D Converter
(Read Only)
Reserved
Figure 35. EXT5 Register A/D Mode Definition
1-48
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
ANALOG CONTROL REGISTER (ACR)
The Analog Control register is mapped to register EXT6 of
the DSP (Table 15). This read/write register is accessible
by the DSP only.
The 16-bit field of EXT6 defines modes of both the A/D and
the D/A. The High Byte configures the D/A, while the Low
Byte controls the A/D mode.
Table 15. EXT6 Analog Control Register (ACR)
Field
Position
Attrib
Value
MPX_DSP_INT0
f---------------
R/W
1
0
Reserved
-edcb-----------
D/A_SamplingRate
-----a98--------
R
W
R/W
DSP_port
--------76------
R/W
Enable A/D
----------5-----
R/W
ConversionDone
-----------4----
W
R
StartConversion
------------3---
R/W
A/D_SamplingRate
-------------210
R/W
DS97TAD0300
PRELIMINARY
11x
101
100
010
011
001
000
1
0
1
0
1
0
11x
101
100
010
011
001
000
Label
P26
Timer3
Return “0”
No Effect
Reserved
Reserved
64 kHz
16 kHz
10 kHz
4 kHz
Reserved
User defined DSP
Outputs
A/D Enabled
A/D Disabled
No effect
Done
Not Done
Start
Wait Timer
Reserved
Reserved
128 kHz
64 kHz
32 kHz
16 kHz
8 kHz
1-49
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
DSP IRQ0. This bit defines the source of DSP IRQ0 interrupt.
D/A_Sampling Rate. This field defines the sampling rate
of the D/A output. It changes the period to Timer3 interrupt
and the maximum possible accuracy of the D/A (Table 16).
Table 16. D/A Data Accuracy
D/A_Sampling
Rate
1
0
0
0
0
1
1
0
0
0
1
1
D/A Accuracy
Sampling Rate
64 kHz
16 kHz
10 kHz
4 kHz
8 Bits
10 Bits
10 Bits
10 Bits
Conversion Done. This Read Only flag indicates that the
A/D conversion is complete. Upon reading EXT5 (A/D data), the Conversion Done flag is cleared.
Start A/D Conversion. Writing a 1 to this location immediately starts one conversion cycle. If this bit is reset to 0 the
input data is converted upon successive Timer2 time-outs.
A hardware reset forces this bit to be 1.
A/D_Sampling Rate. This field defines the sampling rate
of the A/D. It changes the period of Timer2 interrupt (Table
17).
Table 17. A/D Sampling Rate
A/D_Sampling Rate
1
0
0
0
0
DSP0. DSP0 is a general-purpose output pin connected to
Bit 6. This bit has no special significance and may be used
to output data by writing to bit 6.
DSP1. DSP1 is a general-purpose output pin connected to
Bit 7. This bit has no special significance and may be used
to output data by writing to bit 7.
0
1
1
0
0
0
1
0
1
0
ADC Sampling Rate
128 kHz
64 kHz
32 kHz
16 kHz
8 kHz
Enable A/D. Writing a 0 to this location disables the A/D
converter, a 1 will enable it. A hardware reset forces this
bit to be 0.
DSP TIMERS
Timer2 is a free running counter that divides the XTAL frequency (20.48 MHz) to support different sampling rates for
the A/D converter. The sampling rate is defined by the Analog Control Register. Upon reaching the end of a count,
the timer generates an interrupt request to the DSP.
Analogous to Timer2, Timer3 generates the different sampling rates for the D/A converter. Timer3 also generates an
interrupt request to the DSP upon reaching its final count
value (Figure 36).
TIMER2
128, 64, 32, 16, 8 kHz
A/D
TIMER3
64, 16, 10, 4 kHz
D/A
OSC
20.48 MHz
Figure 36. Timer2 and Timer3
1-50
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
PULSE WIDTH MODULATOR (PWM)
The PWM supports four different sampling rates (4, 10, 16,
and 64 kHz), according to the settings of Bit 8, 9, 10 of the
ACR. The output of PWM can be assigned to logic 1 only
during the active region (which is 4/5 of the output signal
period). The output will be at logic 0 for the rest of the time.
An exception occurs in 10 kHz PWM, where the active region covers the whole output signal period (Figure 37). The
active region is divided into 1024 time slots. In each of
these time slots, the output can be set to logic 1 or logic 0.
In order to increase the effective sampling rate, the PWM
employs a special technique of distributing the “logic 1” period over the active region.
The 10-bit PWM data is divided into two parts: the upper 5
bits (High_Val) and the lower 5 bits (Low_Val). The 1024
time slots in the active region are divided into 32 equal
groups, with 32 time slots in each group. The first slot of
each of the 32 groups represents Low_Val, while High_Val
is represented by the remaining 31 time slots in each
group.
For example, a value of %13a is loaded into PWM data
register EXT 5:
%13a = 01 0011 1010B = 314
High_Val = 01001B = 9
Low_Val = 11010B = 26
26 out of 32 groups will then have their first slots set to logic 1. The remaining slots in each group have 9 time slots
set to logic 1.
For 10 kHz PWM, the effective output frequency is 10K x
32 = 320 kHz. Figure 38 illustrates the waveform by using
a 6-bit PWM data (3-bit High_Val and 3-bit Low_Val).
4 kHz
250 µs
10 kHz
100 µs
16 kHz
62.5 µs
64 kHz
16 µs
Figure 37. PWM Waveform
(shaded area shows the active region)
4 kHz
250 µs
10 kHz
100 µs
16 kHz
62.5 µs
64 kHz
16 µs
Figure 38. PWM Waveform of the Active Region
(for a 6-bit PWM data)
DS97TAD0300
PRELIMINARY
1-51
1
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
A/D CONVERTER (ADC)
Analog To Digital Converter
The A/D converter is an 8-bit half flash converter which
uses two reference resistor ladders for its upper four bits
(MSBs) and lower four bits (LSBs) conversion. Two reference voltage pins, VREF+ (High) and VREF- (Low), are provided for external reference voltage supplies. During the
sampling period, the converter is auto-zeroed before starting the conversion time depending on the external clock
frequency and the selection of the A/D sampling rate. The
sampling rates are in the order of 8, 10, 16, 64, or 128 kHz
(XTAL = 20.48 MHz) in order to provide oversampling. The
rates are software controlled by the ACR (DSP External
Register 6). Timer2 supports the ADC. The maximum conversion time is 2 µs.
AN IN
4-Bit
Flash
Sample
4-Bit
DAC
Auto Zero m
4 MSB
–
4-Bit
Flash
+
4 LSB
Auto Zero
Latch 4 MSB
Latch 4 LSB
Bits 9-2 Register 12 of DSP
Figure 39. A/D Converter
Conversion begins by writing to the appropriate bit in the
Analog Control Register (ACR). The start commands are
implemented in such a way as to begin a conversion at any
time. If a conversion is in progress and a new start command is received, then the conversion in progress is aborted and a new conversion initiated. This allows the programmed values to be changed without affecting a
conversion in progress. The new values take effect only after a new start command is received.
1-52
The ADC can be disabled (for low power) or enabled by an
analog Control Register bit.
Though the ADC functions for a smaller input voltage and
voltage reference, the noise and offsets remain constant
over the specified electrical range. The errors of the converter will increase and the conversion time may also take
slightly longer due to smaller input signals.
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Z8 EXPANDED REGISTER FILE REGISTERS
Expanded Register Bank B
7
1
(B) 04
(B) 00
6
5
4
3
2
1
7
0
6
5
4
3
2
1
0
DSP EXT2, Bits D15-D8
DSP EXT0, Bits D15-D8
Figure 44. Outgoing Register to DSP EXT2
(High Byte)
(B) 04H [Read/Write]
Figure 40. Outgoing Register to DSP EXT0
(High Byte)
(B) 00H [Read/Write]
(B) 01
7
(B) 05
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DSP EXT0, Bits D7-D0
DSP EXT2, Bits D7-D0
Figure 45. Outgoing Register to DSP EXT2
(Low Byte)
(B) 05H [Read/Write]
Figure 41. Outgoing Register to DSP EXT0
(Low Byte)
(B) 01H [Read/Write]
(B) 06
(B) 02
7
6
5
4
3
2
1
7
0
6
5
4
3
2
1
0
DSP EXT3, Bits D15-D8
DSP EXT1, Bits D15-D8
Figure 42. Outgoing Register to DSP EXT1
(High Byte)
(B) 02H [Read/Write]
(B) 03
7
Figure 46. Outgoing Register to DSP EXT3
(High Byte)
(B) 06H [Read/Write]
(B) 07
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DSP EXT1, Bits D7-D0
DSP EXT3, Bits D7-D0
Figure 43. Outgoing Register to DSP EXT1
(Low Byte)
(B) 03H [Read/Write]
Figure 47. Outgoing Register to DSP EXT3
(Low Byte)
(B) 07H [Read/Write]
DS97TAD0300
PRELIMINARY
1-53
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Z8 EXPANDED REGISTER FILE REGISTERS (Continued)
(B) 08
(B) 0C
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DSP EXT0, Bits D15-D8
DSP EXT2, Bits D15-D8
Figure 48. Incoming Register to DSP EXT0
(High Byte)
(B) 08H [Read/Write]
(B) 09
7
Figure 52. Incoming Register to DSP EXT2
(High Byte)
(B) 0CH [Read/Write]
(B) 0D
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DSP EXT0, Bits D7-D0
DSP EXT2, Bits D7-D0
Figure 53. Incoming Register to DSP EXT2
(Low Byte)
(B) 0DH [Read/Write]
Figure 49. Incoming Register to DSP EXT0
(Low Byte)
(B) 09H [Read/Write]
(B) 0E
(B) 0A
7
6
5
4
3
2
1
7
0
6
5
4
3
2
1
0
DSP EXT3, Bits D15-D8
DSP EXT1, Bits D15-D8
Figure 54. Incoming Register to DSP EXT3
(High Byte)
(B) 0EH [Read/Write]
Figure 50. Incoming Register to DSP EXT1
(High Byte)
(B) 0AH [Read/Write]
(B) 0F
(B) 0B
7
6
5
4
3
2
1
7
0
6
1-54
4
3
2
1
0
DSP EXT3, Bits D7-D0
DSP EXT1, Bits D7-D0
Figure 51. Incoming Register to DSP EXT1
(Low Byte)
(B) 0BH [Read/Write]
5
Figure 55. Incoming Register to DSP EXT3
(Low Byte)
(B) 0FH [Read/Write]
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Expanded Register Bank F
P5M (FH) 05H
PCON (FH) 00H
D7 D6 D5
D7 D6 D5
D4 D3 D2 D1
D4 D3 D2 D1
P50-P57 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input*
Returns "FF" Upon Read
R Always "1"
W 0 P34,P37
Standard output
1 P34,P37
Comparator output
* Default setting after Reset
Figure 60. Port 5 Mode Register (PCON)
(F) 05H [Write Only]
R Always "1"
Note: Reset condition is 11111110
W No effect
Figure 56. Port Configuration Register (PCON)
(F) 00H [Write Only]
P45CON (FH) 06H
D7
D6 D5
D4
D3
D2 D1
D0
Port 4 Configuration Bit
0 Open Drain *
1 Push-pull Active
P4D (FH) 02H
D7
1
D0
D0
D6 D5 D4 D3
Reserved
D2 D1 D0
Port 5 Configuration Bit
0 Open Drain *
1 Push-pull Active
Data
Reserved
Figure 57. Port 4 Data Register
(F) 02H [Write Only]
* Default setting after Reset
Figure 61. Port 4 and 5 Configuration Register
(F) 06H [Write Only]
P4M (FH) 03H
D7 D6 D5
D4 D3 D2
D1 D0
SMR (FH) 0BH
P40-P47 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input
Returns "FF" Upon Read
D7 D6
D5 D4 D3
D2 D1
W 00 SCLK/TCLK Not Divide by 16†
01 SCLK/TCLK Not Divide by 16
10 SCLK/TCLK Divide by 16
11 SCLK/TCLK Divide by 16
R Always "1"
Figure 58. Port 4 Mode Register
(F) 03H [Write Only]
W 000 POR only*
001 No effect
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
R Always "1"
W 0 Stop delay on*
1 Stop delay off
R Always "1"
P5D (FH) 04H
D7 D6 D5 D4
D0
D3 D2 D1 D0
W 0 Low Stop Recovery Level*
1 High Stop Recovery Level
R Always "1"
W No effect
R 0 POR*
1 Stop-Mode Recovery
Data
*
Default Setting After Reset
† Reset After Stop-Mode Recovery
Figure 59. Port 5 Data Register (PCON)
(F) 04H [Read/Write]
DS97TAD0300
Figure 62. Stop-Mode Recovery Register
(F) 07H [Read/Write]
PRELIMINARY
1-55
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Table 18. DSP Control Register
(F) 0FH [Read/Write]
Field
DSPCON (F)0CH
Position
Attrib
Value
Z8_SCLK
76------
R/W
00
0.1
1x
DSP_Reset
--5-----
R
W
DSP_Run
---4----
Reserved
----32--
IntFeedback
------1-
-------0
0
1
0
1
xx
R/W
R
W
1
0
R
W
1
0
Label
2.5 MHz (OSC/8)
5 MHz (OSC/4)
10 MHz (OSC/2)
Return “0”
No effect
Reset DSP
Halt_DSP
Run_DSP
Return “0”
No effect
FB_DSP_INT2
Set DSP_INT2
No effect
FB_Z8_IRQ3
Clear IRQ 3
No effect
WDTMR (FH) 0FH
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP
00
01 *
10
11
INT RC OSC External Clock
5 ms
256 TpC
15 ms
512 TpC
25 ms
1024 TpC
100 ms
4096 TpC
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC *
1 XTAL
Reserved
* Default setting after RESET
Note: The WDTMR Register is only accessed within 64 Z8®
clock cycles after POR.
Figure 63. Watch-Dog Timer Mode Register
(F) 0FH [Read/Write]
1-56
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Z8 CONTROL REGISTERS
D7 D6 D5
1
R243 PRE1
D4 D3 D2 D1 D0
D7 D6 D5
D4 D3 D2 D1 D0
RESERVED
Count Mode
0 T1 Single Pass
1 T1 Modulo N
Figure 64. Reserved
(F0H)
Clock Source
1 T1Internal
0 T1External Timing Input
(TIN) Mode
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R241 TMR
D7 D6 D5 D4 D3
D2 D1 D0
Figure 67. Prescaler 1 Register
(F3H: Write Only)
0 No Function
1 Load T0
0 Disable T0 Count
1 Enable T0 Count
0 No Function
1 Load T1
R244 T0
0 Disable T1 Count
1 Enable T1 Count
D7 D6 D5 D4 D3
D2 D1 D0
TIN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
T0 Low Byte Initial Value
(When Written)
T0 Low Byte Current Value
(When Read)
TOUT Modes
00 Not Used
01 T0 Out
10 T1 Out
11 Internal Clock Out (P36)
Figure 65. Timer Mode Register
(F1H: Read/Write)
Figure 68. Counter/Timer 0 Register
(F4H: Read/Write)
R245 PRE0
D7 D6 D5
D4 D3 D2 D1
D0
Count Mode
0 T0 Single Pass
1 T0 Modulo N
R242 T1
D7 D6 D5 D4 D3 D2
D1 D0
Reserved
T1 Low Byte Initial Value
(When Written)
T1 Low Byte Current Value
(When Read)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
Figure 69. Prescaler 0 Register
(F5H: Write Only)
Figure 66. Counter/Timer 1 Register
(F2H: Read/Write)
DS97TAD0300
PRELIMINARY
1-57
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
Z8 CONTROL REGISTERS (Continued)
R248 P01M
R246 P2M
D7 D6 D5
D7
D4 D3 D2 D1 D0
D6
D5
D4
D3 D2
D1
D0
P00 - P03 Mode
00 Output
01 Input *
1X A11 - A8
P20 - P27 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input *
Stack Selection
0 External
1 Internal *
* Default Setting After Reset
P10 - P17 Mode
00 Byte Output
01 Byte Input *
10 AD7 - AD0
11 High-Impedance AD7 - AD0,
/AS, /DS, /R//W, A11 - A8,
A15 - A12, If Selected
Figure 70. Port 2 Mode Register
(F6H: Write Only)
External Memory Timing
0 Normal *
1 Extended
R247 P3M
D7 D6 D5 D4 D3 D2
P04 - P07 Mode
00 Output
01 Input *
1X A15 - A12
D1 D0
0 Port 2 Pull-Ups Open Drain *
1 Port 2 Pull-Ups Active
* Default Setting After Reset
0 P31, P32 Digital Mode *
1 P31, P32 Analog Mode
Figure 72. Port 0 Mode Register
(F8H: Write Only)
0 P32 = Input *
P35 = Output *
1 P32 = /DAV0/RDY0
P35 = RDY0//DAV0
00 P33 = Input *
P34 = Output *
01 P33 = Input
P34 = /DM
10 P33 = Input
P34 = /DM
11 P33 = /DAV1/RDY1
P34 = RDY1//DAV1
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
0 P31 = Input (TIN) *
P36 = Output (TOUT) *
1 P31 = /DAV2/RDY2
P36 = RDY2//DAV2
0 P30 = Input
P37 = Output
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
Reserved
* Default Setting After Reset
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
Figure 71. Port 3 Mode Register
(F7H: Write Only)
Reserved
Figure 73. Interrupt Priority Register
(F9H: Write Only)
1-58
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
R253 RP
R250 IRQ
D7
D6 D5 D4 D3 D2
D7 D6
D1 D0
D5 D4 D3 D2
Expanded Register File Bank
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = DSP
IRQ4 = T0
IRQ5 = T1
Working Register Group
Figure 77. Register Pointer
(FDH: Read/Write)
Inter Edge
P31 ↓ P32 ↓ = 00
P31 ↓ P32 ↑ = 01
P31 ↑ P32 ↓ = 10
P31 ↑↓ P32 ↑↓ = 11
Figure 74. Interrupt Request Register
1
D1 D0
R254 SPH
D7 D6 D5
D4 D3 D2 D1
D0
Stack Pointer Upper
Byte (SP8 - SP15)
R251 IMR
D7
D6 D5 D4 D3 D2 D1
D0
Figure 78. Stack Pointer High
(FEH: Read/Write)
1 Enables IRQ0-IRQ5
(D0 = IRQ0)
1 Enables RAM Protect
1 Enables Interrupts
R255 SPL
D7 D6 D5
Figure 75. Interrupt Mask Register
(FBH: Read/Write)
D0
Stack Pointer Lower
Byte (SP0 - SP7)
Figure 79. Stack Pointer Low
(FFH: Read/Write)
R252 FLAGS
D7
D4 D3 D2 D1
D6 D5 D4 D3 D2
D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
Figure 76. Flag Register
(FCH: Read/Write)
DS97TAD0300
PRELIMINARY
1-59
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
PACKAGE INFORMATION
1
Figure 80. 68-Pin PLCC Package Diagram
DS97TAD0300
PRELIMINARY
1-60
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
ORDERING INFORMATION
Z89135
Z89136
20 MHz
68-Pin PLCC
Z8913520VSC
20 MHz
68-Pin PLCC
Z8913620VSC
1
Speed
Temperature
20 = 20.48 MHz
S = 0°C to +55°C
Package
Environmental
V = Plastic Leaded Chip Carrier (PLCC)
C = Plastic Standard
Example:
Z 89135 20 V S C
is a Z89135, 20.48 MHz, PLCC, 0°C to +55°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
DS97TAD0300
PRELIMINARY
1-61
Z89135/136 (ROMless)
Low-Cost DTAD Controller
1-62
Zilog
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
1
DS97TAD0300
PRELIMINARY
1-63
Z89135/136 (ROMless)
Low-Cost DTAD Controller
1-64
Zilog
PRELIMINARY
DS97TAD0300
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
1
DS97TAD0300
PRELIMINARY
1-65
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Zilog
1
DS97TAD0300
PRELIMINARY
1-66