PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION 1 Z90365 1 DIGITAL TELEVISION CONTROLLER FEATURES Device ROM (KW) RAM* (Words) PWM (8-Bit) Voltage Range Z90365 32 640 8 4.5 to 5.5V Note: *General-Purpose ■ 42-Pin SDIP ■ 0°C to +70°C Temperature Range ■ Fully Customized Character Set ■ Character-Control and Closed-Caption Modes ■ Keypad User Control ■ TV Tuner Serial Interface ■ Direct Video Signals ■ Supports Violence Blocking ■ Speed: 12 MHz GENERAL DESCRIPTION The Z90365 Digital Television Controller is designed to provide complete audio and video control of television receivers, video recorders, and advanced on-screen display facilities. The television controller features a Z89C00 RISC processor core that controls the on-board peripheral functions and registers using the standard processor instruction set. Character attributes can be controlled through two modes: the on-screen display Character-Control Mode and the Closed-Caption Mode. The Character-Control Mode provides access to the full set of attribute controls, allowing the modification of attributes on a character-by-character basis. The insertion of control characters permits direction of other character attributes. Closed-caption text can be decoded directly from the composite video signal and displayed on-screen with the assistance of the processor's digital signal processing (DSP) capabilities. The fully customized 512 character set, formatted in two 256 character banks, can be displayed with a host of display attributes that include underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency. CP97TEL2800 Serial interfacing with the television tuner is provided through the tuner serial port. Other serial devices, such as digital channel tuning adjustments, may be accessed through the industry-standard I2C port. User control can be monitored through the keypad scanning port, or the 16-bit remote control capture register. Receiver functions such as color and volume can be directly controlled by eight 8-bit pulse width modulated ports. Notes: All Signals with a preceding front slash, "/", are active Low. For example, B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power VCC VDD Ground GND VSS PRELIMINARY 1 Z90365 Digital Television Controller Zilog GENERAL DESCRIPTION (Continued) PWM PWM1 PWM2 PWM3 PWM4 PWM5 PWM9 PWM10 Capture IRIN ADC Port 17 Port 00 ADC0 ADC1 ADC2 ADC3 ADC4 Port1 Port 0 Port 00 Port 01 Port 02 Port 03 Port 04 Port 05 Port 06 Port 07 Port 08 Port 09 Port 0F Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 Control XTAL1 XTAL2 LPF HSYNC VSYNC /Reset Register Addr/Data V1 V2 V3 VBLANK HALFBLNK CPU RAM 640 x 16 OSD Port0F Address ROM Addr Data ROM 32K x 16 ROM Data Figure 1. Functional Block Diagram 2 PRELIMINARY CP97TEL2800 Z90365 Digital Television Controller Zilog PIN DESCRIPTION PWM10 1 42 Port12/I2MSD PWM9 2 41 P11/I2MSC PWM5 3 40 Port02/I2SSD PWM4 4 39 Port01/I2SSC PWM3 5 38 Port09 PWM2 6 37 Port08/R<1> PWM1 7 36 IRIN Port03 8 35 Port07/CSync Port04/ADC4 9 34 Vcc Port05/ADC3 10 33 /Reset Port00/ADC2 11 32 XTAL2 Port17/ADC1 12 31 XTAL1 GND 13 30 ANGND Port10/R<0> 14 29 LPF Port06/Counter 15 28 CVI/ADC0 Port18/G<0> 16 27 VSync Port13/G<1> 17 26 HSync Port14/B<0> 18 25 VBlank Port15/B<1> 19 24 V1 Port16/SCLK 20 23 V2 Port0F/Half Blank 21 22 V3 Z90365 Shrink DIP 1 Figure 2. 42-Pin Shrink DIP CP97TEL2800 PRELIMINARY 3 Z90365 Digital Television Controller Zilog PIN DESCRIPTION (Continued) Table 1. 42-Pin SDIP Pin Identification Name Function Z90365 Direction Reset VCC + 5 Volts 34 PWR – 0 Volts 13, 30 Infrared Remote Capture 36 Input ADC[4:0] 4-Bit A/D Converter Input 9, 10, 11, 12, 28 PWM10, PWM9 14-Bit Pulse Width 1, 2 Modulator Output PWM[5:1] 8-Bit Pulse Width Modulator 3, 4, 5, 6, 7 Output Port0[F:0] Bit Programmable 21, -, -, -, -, -, 38, 37, Input/Output Ports 35, -, -, 15, 8, 40, 39, 11 Port1[8:0] Bit Programmable 16, 12, 20, 19, 18, 17, Input/Output Ports 42, 41, 14 2 39 or 41 SCL I C Clock I/O PWR I – I AI O I O O O B I B I BOD 2 40 or 42 I Data I/O Crystal Oscillator Input 31 Crystal Oscillator Output 32 Loop Filter 29 H_SYNC 26 V_SYNC 27 Device Reset 33 OSD Video Output Typically 22, 23, 24 Drive B, G, and R Outputs OSD Blank Output 25 OSD HalfBlank Output 21 R[1:0], G[1:0], and B[1:0] 37, 14, 17, 16, 19, 18 Outputs of the RGB Matrix Internal Processor SCLK 20 BOD 3 GND IRIN SCD XTAL1 XTAL2 LPF HSYNC VSYNC /Reset V[3:1] Blank HalfBlank RGB Digital Outputs SCLK 2C AI AO AB B B I O I O O I I I O O O O O O Notes 1 4 5 6 Notes: 1. SCL I/O pin is shared with Port 0 or Port 11. 2. SCD I/O pin is shared with Port 02 or Port 12. 3. Half Blank output is a function shared with Port 0F. 4. Digital RGB outputs and the internal SCLK are shared with Port 1 [5:0]. 5. Internal processor SCLK is shared with Port 16. PWM outputs are push/pull 4 PRELIMINARY CP97TEL2800 Z90365 Digital Television Controller Zilog V1, V2, V3 (R, G, B) ANALOG OUTPUT (PRELIMINARY) TA = 0°C to 70°C Output Voltage (30 kΩ load) data = 00 data = 01 data = 10 data = 11 1 Settling Time VCC = 4.75 5.00V 5.25V 70% of DC level, 10pF load 0.00v .. 0.65v 1.70v ± 0.20v 2.80v ± 0.25v 3.90v ± 0.3v 0.00v .. 0.70v 1.80v ± 0.20v 2.90v ± 0.25v 4.0v ± 0.30v 0.00v .. 0.75v 1.90v ± 0.20v 3.00v ± 0.25v 4.10v ± 0.30v ‹ 50 ns 32.768 KHz 22 pF 10 MΩ Z90365 XTAL1 XTAL2 68 KΩ 47 pF Figure 3. 32 kHz Oscillator Recommended Circuit Z90365 510 Ω 47 µF 0.1 µF Figure 4. Recommended Low Pass Filter Circuit CP97TEL2800 PRELIMINARY 5 Z90365 Digital Television Controller Zilog ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Units VCC Power Supply Voltage VID Conditions 0 7 V Input Voltage –0.3 VCC +0.3 V Digital Inputs VIA Input Voltage –0.3 VCC +0.3 V Analog Inputs (A/D0...A/D4) VO Output Voltage –0.3 VCC +0.3 V All Push-Pull Digital Output VO Output Voltage –0.3 VCC +0.3 V Push/Pull PWM Outputs (PWM1...PMW8) IOH Output Current High –10 mA One Pin IOH Output Current High –100 mA All Pins IOL Output Current Low 20 mA One Pin IOL Output Current Low 200 mA All Pins TA Operating Temperature 0 70 °C TA Storage Temperature –65 150 °C DC CHARACTERISTICS TA = 0°C to + 70°C; VCC = 4.5V to + 5.5V; FOSC = 32.768 kHz Symbol Parameter Min Max Typical Units VIL Input Voltage Low 0 0.2 VCC 0.4 V VIH Input Voltage High 0.7 VCC VCC 3.6 V VPU Max. Pull-Up Voltage VCC +0.3 VOL Output Voltage Low 0.4 VOH Output Voltage High VXL Input Voltage XTAL1 Low VXH Input Voltage XTAL1 High VHY Schmitt Hysteresis IIR Reset Input Current IIL Input Leakage ICC IADC Conditions V All Pins 0.16 V @ IOL = 1 mA 4.75 V @ IOL = 0.75 mA 1.0 V External Clock 3.5 V Generator Driven 0.75 0.5 V On XTAL1 Input Pin 150 90 µA VRL = 0V 3.0 0.01 µA @ 0V and VCC Supply Current 100 60 mA Input Current 10 VCC –0.4 0.3 VCC VCC –2.0 3.0 –3.0 µA Notes: 1. The Z90365 should not be operated for extended periods with the crystal oscillator disconnected, except in the defined powerdown modes. In the event that the Z90365 is operated with the oscillator disconnected, the device may draw higher than typical current. 2. Each line of the on-screen display can consist of any number of characters, up to a maximum of 30 characters. 6 PRELIMINARY CP97TEL2800 Z90365 Digital Television Controller Zilog AC CHARACTERISTICS TA = 0°C to 70°C; VCC = 4.5V to 5.25V; FOSC = 32.768 kHz Symbol Parameter Min TPC Input Clock Period 16 TRC,TFC Clock Input Rise and Fall TDPOR Power-On Reset Delay TWRES Power-On Reset Minimum Width TDHS H-SYNC Incoming Signal Width 1 TDVS V-SyYNC Incoming Signal Width 1 TDES 0.8 Typical 32 Max Units 100 µS 12 nS 1.2 S 5 TPC µS 10 15 µS 200 10,000 µS 0 +12 µS TDOS Time Delay Between Leading Edge of V-SYNC and H-SYNC in –12 EVEN Field Time Delay Between Leading Edge of H-SYNC in ODD Field 20 32 44 µS TWHVS H_Sync/V_Sync Edge Width 0.5 2.0 µS 1 Note: All timing of the I2C bus interface are defined by related specifications of the I2C bus interface. © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. CP97TEL2800 Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com PRELIMINARY 7 Z90365 Digital Television Controller 8 Zilog PRELIMINARY CP97TEL2800