P R E L I M I N A R Y Zilog Z90341 PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z90341 DIGITAL TELEVISION CONTROLLER FEATURES ■ Part Number OTP ROM RAM (Word) Speed (MHz) ■ Direct Closed Caption Decoding Z90341 64K x 16 1K x 16 12 ■ TV Tuner Serial Interface ■ 52-Pin Shrink DIP Package ■ Customized Character Set ■ 4.5- to 5.5-Volt Operating Range ■ Character Control Mode ■ Z89C00 RISC Processor Core ■ Directly Controlled Receiver Functions ■ 0°C to +70°C Temperature Range ■ V-Chip Decode GENERAL DESCRIPTION The Z90341 is a member of Zilog's family of Digital Television Controllers designed to provide complete audio and video control of television receivers, video recorders, and advanced on-screen display facilities. Serial interfacing with the television tuner is provided through the tuner serial port. Digital channel tuning adjustments may be accessed through the industrystandard I2C port. The Z90341 features a powerful Z89C00 RISC processor core that controls on-board peripheral functions and registers using the standard processor instruction set. Additional hardware provides the capability to display two to three times normal size characters. The smoothing logic contained in the on-screen display circuit improves the appearance of larger fonts. Special circuitry can be activated to improve the visibility of text by adding a rightsided shadow effect to the characters. In closed caption mode, text can be decoded directly from the composite video signal and displayed on the screen with assistance from the processor's digital signal processing capabilities. The character representation in this mode allows for a simple attribute control through the insertion of control characters. The character control mode provides access to the full set of attribute controls. The modification of attributes is allowed on a character-by-character basis. The insertion of control characters permits direction of other character attributes. Display attributes, including underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency, are made possible through a fully customized 512 character set. CP97TEL2500 Receiver functions such as color and volume can be directly controlled by six 8-bit pulse width modulated ports. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS 1 P R E L I M I N A R Y Zilog Z90341 GENERAL DESCRIPTION (Continued) PWM Capture IRIN CVI Port 17 Port 00 Port 05 Port 04 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 ADC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 Port1 Port 0 Port 00 Port 01 Port 02 Port 03 Port 04 Port 05 Port 06 Port 07 Port 08 Port 09 Port 0A Port 0B Port 0C Port 0D Port 0E Port 0F Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 Control XTAL1 XTAL2 LPF HSYNC HSYNC2 VSYNC /Reset PWM6 I2C SCL/MSCL2 SCD/MSCD2 MSCL1 MSCD1 Register Addr/Data Port 01/11 Port 02/12 OSD V1(R) V2(G) CPU V3(B) RAM 1K x 16 Address ROM Addr Data ROM Data OTP ROM 64K X 16 Functional Block Diagram 2 CP97TEL2500 P R E L I M I N A R Y Zilog Z90341 PIN DESCRIPTION Port 16/SCLK 1 52 Port15/B1 IRIN 2 51 Port14/B0 Port 0C 3 50 Port13/G1 Port 0B 4 49 Port18/G0 Port 0A 5 48 Port08/R1 Port 09 6 47 Port10/R0 Port 0D 7 46 PWM6/Hsync2 Port 07/CSync 8 45 PWM5 Port 06/Counter 9 44 PWM4 43 PWM3 42 PWM2 Port 03 10 Z90341 Port 02/I2CSSC 11 Port 01/I2CSSD 12 41 PWM1 CVI/ADC0 13 40 AGNDX LPF 14 39 VCC AGNDF 15 38 GND ADC5 16 37 XTAL2 Port 04/ADC4 17 36 XTAL1 Port 05/ADC3 18 35 /Reset Port 00/ADC2 19 34 I2MSC1 Port 17/ADC1 20 33 I2MSD1 AGND 21 32 Port 0E AVCC 22 31 Port11/I2CMSC2 Port0F/Stransp 23 30 Port12/I2CMSD2 V3/B 24 29 VSync V2/B 25 28 HSync V1/B 26 27 Blank 52-Pin Shrink DIP Configuration CP97TEL2500 3 P R E L I M I N A R Y Zilog Z90341 PIN DESCRIPTION Z89313 Pin Name Function Z90341 52-Pin Configuration Direction 39,22 38,21,15,40 PWR PWR – – 2 16,17,18,19,20 I AI I I 46,45,44,43,42,41 O O 23,32,7,3,4,5,6,48,8,9,18, 17,10,12,11,19 B I 49,20,1,52,51,50,30, 31,47 B I 11,31,34 12,30,33 BOD BOD Reset VCC , AVCCa GND, AGND, AGNDF, AGNDXb +5 V 0V IRIN ADC[5:1] Infrared Remote Capture Input 4-Bit Analog-to-Digital Converter Input PWM[6:1] Port0[F:0] 8-Bit Pulse Width Modulator Output Bit Programmable Input/Output Ports Port1[8:0] Bit Programmable Input/Output Ports SCL SCD I2C Clock I/O I2C Data I/O XTAL1 XTAL2 Crystal Oscillator Input Crystal Oscillator Output 36 37 AI AO I O LPF Loop Filter 14 AB O HSYNC VSYNC H_Sync V_Sync 28,46 29 B B I I /RESET Device Reset 35 I I V[3:1] 24,25,26 O O Blank Semi transparent OSD Video Output (Typically Drive B, G, and R Outputs) OSD Blank Output OSD Semi transparent Output 27 23 O O O SCLK Internal Processor SCLK – O Notes: Please refer to pin-out diagram for shared pin numbers. a) AVCC is for the reference voltage of the ADC input. b) AGND is for the reference ground of the ADC input. AGNDF is for LPF ground, and AGNDX is for XTAL circuit ground. 4 CP97TEL2500 P R E L I M I N A R Y Zilog Z90341 V1, V2, V3 ANALOG OUTPUT Specifications VCC = 5.25 V VCC = 5.25 V Condition Limit Output Voltage Bit = 11 Bit = 10 Bit = 01 Bit = 00 2.10 V ± 0.3 V 1.75 V ± 0.3 V 1.28 V ± 0.30 V 0.0 + 0.3V Setting Time 70% of DC Level, 10pf Load < 50 ns VCC = 4.75 V Condition Limit Output Voltage Bit = 11 Bit = 10 Bit = 01 Bit = 00 1.90 V ± 0.30 V 1.60 V ± 0.30 V 1.20 V ± 0.30 V 0 V + 0.3 V Setting Time 70% of DC Level, 10pf Load < 50 ns V1, V2, V3 ANALOG OUTPUT Specifications VCC = 4.75 V XTAL1 32.768k 68pF 10 Mohm Z9034X XTAL2 27k 560pF 32K Oscillator Recommended Circuit CP97TEL2500 5 P R E L I M I N A R Y Zilog Z90341 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Units Conditions VCC VID Power Supply Voltage Input Voltage 0 –0.3 7 VCC +0.3 V V Digital Inputs VIA VO IOH IOH IOL IOL Input Voltage Output Voltage Output Current High Output Current High Output Current Low Output Current Low –0.3 –0.3 VCC +0.3 VCC +0.3 –10/–1a –100 20/1b 200 V V mA mA mA mA Analog Inputs (A/D0...A/D4) All Push-Pull Digital Output One Pin All Pins One Pin All Pins TA TS Operating Temperature Storage Temperature 0 –65 70 150 °C °C Notes: a) 1 mA max. when output pad impedance is 600 Ω. b) 1 mA max. when output pad impedance is 600 Ω. DC CHARACTERISTICS TA = 0°C to + 70°C; VCC = 4.5 V to + 5.5 V; FOSC = 32.768 KHz Symbol Parameter Min Max Typical 0.2 VCC VCC 0.4 3.6 V V 0.4 0.16 4.75 V V @ IOL = 1 mA @ IOL = 0.75 mA 0.3 VCC 0.75 150 1.0 3.5 0.5 90 V V V µA External Clock Generator Driven On XTAL1 Input Pin VRL = 0 V 3.0 100 0.01 60 µA mA @ 0 V and VCC 300 40 100 5 µA µA Sleep Mode @ 32 KHz Stop Mode VIL VIH Input Voltage Low Input Voltage High 0 0.6 VCC VOL VOH Output Voltage Low Output Voltage High VCC –0.9 VXL VXH VHY IIR Input Voltage XTAL1 Low Input Voltage XTAL1 High Schmitt Hysteresis Reset Input Current IIL ICC Input Leakage Supply Current ICC1 ICC2 Supply Current Supply Current 6 VCC –2.0 3.0 –3.0 Units Conditions CP97TEL2500 P R E L I M I N A R Y Zilog Z90341 AC CHARACTERISTICS TA = 0°C to + 70°C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz Symbol Parameter Min Max Typical Units TP C TRC,TFC Input Clock Period Clock Input Rise and Fall 16 100 32 12 µs µs TD POR Power On Reset Delay 0.8 1.2 s Note Depends on Crystal AC CHARACTERISTICS* TA = 0°C to + 70°C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz Symbol Parameter Min Max Typical Units TW RES TD HS Power-On Reset Min. Width H_Sync Incoming Signal Width 5.5 5TPC 12.5 11 µs µS TD VS TD ES V_Sync Incoming Signal Width Time Delay Between Leading Edge of V_Sync and H_Sync in Even Field 0.15 –12 1.5 +12 1.0 0 ms µs TD OS Time Delay Between Leading Edge of H_Sync in Odd Field H_Sync/V_Sync Edge Width 20 44 32 µs 2.0 0.5 µs TW HVS Notes: All timing of the I2C bus interface are defined by related specifications of the I2 C bus interface. © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. CP97TEL2500 Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com 7