SN75437A QUADRUPLE PERIPHERAL DRIVER SLRS019B – DECEMBER 1986 – REVISED SEPTEMBER 2000 D D D D D D D D NE PACKAGE (TOP VIEW) Saturating Outputs With Low On-State Resistance High-Impedance Inputs Compatible With CMOS and TTL Levels Very Low Standby Power . . . 21 mW Max High-Voltage Outputs . . . 70 V Min No Power-Up or Power-Down Output Glitch No Latch-Up Within Recommended Operating Conditions Output-Clamp Diodes for Transient Suppression Packaged in 2-W Power, Thermally Enhanced Plastic DIP 1Y 1, 2 D 2Y HEAT SINK AND GND 1 16 2 15 3 14 4 13 5 12 3Y 3, 4 D 4Y 6 11 7 10 8 9 1A 2A G HEAT SINK AND GND VCC 3A 4A description The SN75437A quadruple peripheral driver is designed for use in systems requiring high current, high voltage, and high load power. This device features four inverting open-collector outputs with a common-enable (G) input that, when taken low, disables all four outputs. The envelope of 1-V characteristics exceeds the specifications sufficiently to avoid high-current latch-up. Applications include driving relays, lamps, solenoids, motors, LEDs, transmission lines, hammers, and other high-power-demand devices. The SN75437A is characterized for operation over the free-air temperature range of 0°C to 70°C. FUNCTION TABLE (each NAND driver) INPUTS OUTPUT A G Y H H L L X H X L H H = high level, L = low level, X = irrelevant Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN75437A QUADRUPLE PERIPHERAL DRIVER SLRS019B – DECEMBER 1986 – REVISED SEPTEMBER 2000 logic diagram (positive logic)† G 1A 2A 3A 4A 14 EN 1 16 CLAMP 15 3 2 6 10 8 9 7 1Y 2Y 1, 2 D 3Y 4Y 3, 4 D † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC publication 617-12. logic diagram (positive logic, each driver) A VCC Y equivalent schematic of each input VCC D G To One Other Driver Input GND To Three Other Drivers absolute maximum ratings over operating temperature range (unless otherwise noted) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V Output current (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 A Output clamp-diode current, IOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 A Output voltage, VO (off state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 V Continuous total power dissipation at (or below) 25°C free-air temperature (see Note 2) . . . . . . . . 2075 mW Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C NOTES: 1. All four sections of these circuits may conduct rated current simultaneously; however, power dissipation averaged over a short time interval must fall within the continuous dissipation ratings. 2. For operation above 25°C free-air temperature, derate linearly to 1328 mW at 70°C at the rate of 16.6 mW/°C. recommended operating conditions PARAMETER Supply voltage, VCC High-level input voltage, VIH MIN NOM MAX UNIT 4.75 5 5.25 V 2 V Low-level input voltage, VIL 0.8 V Output supply voltage in inductive switching circuit (see Figure 2), 2) VS 35 V Output current, IO Operating free-air temperature, TA 2 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0.5 A 70 °C SN75437A QUADRUPLE PERIPHERAL DRIVER SLRS019B – DECEMBER 1986 – REVISED SEPTEMBER 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK Input clamp voltage VCC = 4.75 V, VOL Low level output voltage Low-level VCC = 4.75 V,, VIH = 2 V VR(K) VF(K) Output clamp-diode reverse voltage VCC = 4.75 V, IF = 500 mA Output clamp-diode forward voltage IOH High level output current High-level IIH IIL High-level input current TYP† MAX UNIT II = – 12 mA IOL = 250 mA – 0.9 – 1.5 V 0.14 0.25 IOL = 500 mA IR = 100 µA 0.28 0.5 TEST CONDITIONS Low-level input current ICCH Supply current, outputs high ICCL Supply current, outputs low † All typical values are at VCC = 5 V, TA = 25°C. VCC = 4.75 V,, VIL = 0.8 V, VIH = 2 V,, VOH = 70 V VCC = 5.25 V, VCC = 5.25 V, VI = 5.25 V VI = 0.8 V VCC = 5.25 V, VCC = 5.25 V, VI = 0 VI = 5 V MIN 70 100 V V 1 1.6 V 1 100 µA 0.1 10 µA – 0.25 – 10 µA 1 4 mA 45 65 mA TYP MAX UNIT 1950 5000 ns 150 500 ns switching characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output tTLH tTHL Transition time, low-to-high-level output VOH Propagation delay time, high-to-low-level output CL = 30 pF,, See Figure 1 RL = 60 Ω,, VS = 35 V,, RL = 70 Ω, IO ≈ 500 mA,, See Figure 2 MIN Transition time, high-to-low-level output High level output voltage after switching High-level POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VS – 10 40 ns 36 ns mV 3 SN75437A QUADRUPLE PERIPHERAL DRIVER SLRS019B – DECEMBER 1986 – REVISED SEPTEMBER 2000 PARAMETER MEASUREMENT INFORMATION Input 30 V VCC 5 µs ≤ 5 ns 2.4 V Input RL = 60 Ω A/G Pulse Generator (see Note A) G/A 3V 10% 10% Output Circuit Under Test ≤ 10 ns 90% 1.5 V 90% 1.5 V t PHL 0V t PLH 90% VOH 90% CL = 30 pF (see Note B) Output 50% 10% 50% 10% t THL Open TEST CIRCUIT VOL t TLH VOLTAGE WAVEFORMS NOTES: A. The pulse generator has the following characteristics: PRR = 100 kHz, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 1. Test Circuit and Voltage Waveforms VS Input 5V RL Pulse Generator (see Note A) A 2.4 V G 40 µs 2 mH Circuit Under Test GND SUB Input 1.5 V 10% 90% 1.5 V 10% ≤ 5 ns Output 0V ≤ 10 ns VOH CL = 15 pF (see Note B) Output VOL VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 2. Latch-Up Test Circuit and Voltage Waveforms 4 3V 90% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN75437ANE ACTIVE PDIP NE 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75437ANEE4 ACTIVE PDIP NE 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDI003 – OCTOBER 1994 NE (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 20 PIN SHOWN 0.070 (1,78) MAX 11 20 PINS ** DIM A C 1 20 0.914 (23,22) MIN MAX B 16 0.780 (19,80) 0.975 (24,77) MIN 0.930 (23,62) MAX 1.000 (25,40) 10 C MIN 0.240 (6,10) 0.260 (6,61) MAX 0.260 (6,60) 0.280 (7,11) 0.020 (0,51) MIN A 0.200 (5,08) MAX Seating Plane 0.155 (3,94) 0.125 (3,17) 0.100 (2,54) 0.021 (0,533) 0.015 (0,381) 0.010 (0,25) M 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN B 0.200 (5,08) MAX Seating Plane 0.155 (3,94) 0.125 (3,17) 0.100 (2,54) 0.021 (0,533) 0.015 (0,381) 0.010 (0,25) M 0°– 15° 0.010 (0,25) NOM 4040054 / B 04/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (16 pin only) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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