ICS ICS9148F-75-T

ICS9148-75
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Mother Boards
General Description
The ICS9148-75 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro™, AMD™ or Cyrix™. Sixteen different reference
frequency multiplying factors are externally selectable with
smooth frequency transitions.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-75
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection. The
SDRAM12 output may be used as a feed back into an off chip
PLL.
Block Diagram
Features
•
Generates the following system clocks:
- 3 CPU(2.5V/3.3V) up to 100MHz.
- 6 PCI(3.3V) @ 33.3MHz (including one free
running PCICLK)
- 3AGP(3.3V) @ 2 x PCI
- 13 SDRAMs(3.3V) up to 100MHz
- 1 REF (3.3V) @ 14.318MHz
- 1 - 48MHz (3.3V) fixed
•
Skew characteristics:
- CPU – CPU<250ps
- CPU(early) – PCI : 1-4ns
- AGP – PCI: 250ps
- PCI – PCI <500ps
•
Supports Spread Spectrum modulation & I2C
programming for Power Management, Frequency Select
•
Efficient Power management scheme through power
down PCI, AGP and CPU_STOP clocks.
•
Uses external 14.318MHz crystal
•
48 pin 300mil SSOP.
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core
VDD4 = AGP (1:2)
VDD5 = Fixed PLL, 48MHz , AGP0
VDDL = CPUCLK (0:3)
9148-75 Rev C 3/01/00
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
ICS9148-75
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
1
2
3,9,16,22,27,
33,39,45
4
P I N NA M E
VDD1
REF0
TYPE
PWR
OUT
FS3
IN
GND
PWR
PCICLK0
FS21, 2
PCICLK(1:4)
VDD5
BUFFERIN
OUT
IN
OUT
PWR
IN
CPU_STOP#
IN
SDRAM 11
OUT
PCI_STOP#1
IN
SDRAM 10
OUT
SDRAM (0:9)
OUT
SDRAM clock outputs.
AGP_STOP#1
IN
IN
5
X2
OUT
VDD2
PWR
PCICLK_F
OUT
7
FS11, 2
10, 11, 12, 13
14
15
17
18
28, 29, 31, 32, 34,
35,37,38
20
SDRAM9
IN
OUT
1
IN
SDRAM8
OUT
19,30,36
VDD3
PWR
23
24
SDATA
SCLK
IN
IN
AGP0
OUT
21
PD#
25
MODE1, 2
48MHz
26
41, 43, 44
40
42
46, 47
48
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew
(CPU early) This is not affected by PCI_STOP#
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Supply for fixed PLL, 48MHz, AGP0
Input pin for SDRAM buffers.
Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile
Mode, MODE=0)
SDRAM clock output
Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode,
MODE=0)
SDRAM clock output
X1
6
8
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
1, 2
FS0
CPUCLK(0:3)
SDRAM12
VDDL
AGP (1:2)
VDD4
IN
OUT
IN
OUT
OUT
PWR
OUT
PWR
This asynchronous input halts AGP(1:2) clocks at logic "0" level when input
low (in Mobile Mode, MODE=0) Does not affect AGP0
SDRAM clock output
This asyncheronous Power Down input Stops the VCO, crystal & internal
clocks when active, Low. (In Mobile Mode, MODE=0)
SDRAM clock output
Supply for SDRAM (0:11), CPU Core, 48MHz clocks,
nominal 3.3V.
Data input for I2C serial input.
Clock input of I2C input
Advanced Graphic Port output, powered by VDD4. Not affected by
AGP_STOP#
Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock for USB timing.
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Feedback SDRAM clock output.
Supply for CPU (0:3), either 2.5V or 3.3V nominal
Advanced Graphic Port output powered by VDD4.
Supply for AGP (0:2)
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2
ICS9148-75
Preliminary Product Preview
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
0
1
Pin 17
Pin 18
Pin 20
Pin 21
CPU_STOP#
(INPUT)
SDRAM 11
(OUTPUT)
PCI_STOP#
(INPUT)
SDRAM 10
(OUTPUT)
AGP_STOP#
(INPUT)
SDRAM 9
(OUTPUT)
PD#
(INPUT)
SDRAM 8
(OUTPUT)
Power Management Functionality
AGP_STOP# CPU_STOP# PCI_STOP#
CPUCLK
Outputs
PCICLK
(0:5)
PCICLK_F,
REF, 48MHz
and SDRAM
Crystal
OSC
VCO
AGP(1:2)
1
0
1
Stopped Low
Running
Running
Running
Running
Running
1
1
1
Running
Running
Running
Running
Running
Running
1
1
0
Running
Stopped Low
Running
Running
Running
Running
0
1
1
Running
Running
Running
Running
Running
Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Input level
(Latched Data)
1
0
Buffer Selected for
operation at:
2.5V VDD
3.3V VDD
3
ICS9148-75
Preliminary Product Preview
Functionality
VDD1, 2, 3, 4 = 3.3V±5%, TA= 0 to 70°C
Crystal (X1, X2) = 14.31818MHz
FS3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
FS2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
FS1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
FS0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CPU,SDRAM
(MHZ)
105
110
115
120
125
130
135
140
100
95.25
83.3
75
75
68.5
66.8
60
4
PCI (MHZ) AGP (MHZ)
35
70
36.67
73.34
38.33
76.66
40
80
41.66
83.32
43.33
86.66
45
90
46.67
93.44
33.3
66.6
31.75
63.5
33.3
66.6
30
60
37.5
75
34.25
68.5
33.4
66.8
30
60
REF, IOAPIC
(MHZ)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
ICS9148-75
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ICS (Slave/Receiver)
ACK
Byte Count
ACK
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Byte 6
Byte 6
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
5
ICS9148-75
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Bit
(2, 6:4)
Bit 3
Bit 1
Bit 0
Description
PWD
0 - ±0.25% Spread Spectrum Modulation
0
1 - ±0.6% Spread Spectrum Modulation
Bit (2, 6:4) CPU CLKs PCI CLKs AGP CLKs
1111
105
35
70
1110
110
36.67
73.34
1101
115
38.33
76.66
1100
120
40
80
1011
125
41.66
83.32
1010
130
43.33
86.66
1001
135
45
90
1000
140
46.67
93.44
Note1
0111
100
33.3
66.6
0110
95.25
31.75
63.5
0101
83.3
33.3
66.6
0100
75
30
60
0011
75
37.5
75
0010
68.5
34.25
68.5
0001
66.8
33.4
66.8
0000
60
30
60
0 - Frequency is selected by hardware select,
Latched Inputs
0
1 - Frequency is selected by Bit 6:4 (above)
0 - Normal
0
1 - Spread Spectrum Enabled (center spread)
0 - Running
0
1- Tristate all outputs
Note 1: Default at power-up will be for latched logic inputs to define frequency;
Bits 2, 6:4 are default to 000
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
6
ICS9148-75
Preliminary Product Preview
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
40
41
43
44
PWD
1
1
1
1
1
1
1
1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Pin #
7
15
13
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
PCICLK_F (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
28
29
31
32
34
35
37
38
PWD
1
1
1
1
1
1
1
1
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Pin #
8
7
47
2
46
2
PWD
1
1
1
1
1
Pin #
25
26
-
PWD
1
1
1
Bit 3
17
1
Bit 2
18
1
Bit 1
Bit 0
20
21
1
1
Description
AGP0 (Active/Inactive)
(Reserved)
FS0#
(Reserved)
SDRAM11 (Act/Inact)
(Desktop Mode Only)
SDRAM10 (Act/Inact)
(Desktop Mode Only)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Byte 6: Optional Register for Possible
Future Requirements
Description
(Reserved)
FS2#
FS1#
AGP2 (Act/Inact)
(Reserved)
FS3#
AGP1 (Act/Inact)
REF0 (Act/Inact)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Pin #
-
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
7
ICS9148-75
Preliminary Product Preview
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148-75. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9148-75.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
8
ICS9148-75
Preliminary Product Preview
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-75. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9148-75 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
9
ICS9148-75
Preliminary Product Preview
AGP_STOP# Timing Diagram
AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP (0:1) clocks. for low power
operation. AGP_STOP# is synchronized by the ICS9148-75. The AGP2 clock is free-running and is not affected by AGP_STOP#.
All other clocks will continue to run while the AGPCLKs are disabled. The AGPCLKs will always be stopped in a low state and
start in such a manner that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK and
AGPCLK off latency is less than 4 AGPCLKs. This function is available only with MODE pin latched low.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. AGP_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9148-75.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
5. Only applies if MODE pin latched 0 at power up.
10
ICS9148-75
Preliminary Product Preview
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9148-75
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
11
ICS9148-75
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
Input frequency
Input Capacitance1
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP
Transition Time1
1
Settling Time
Clk Stabilization
Skew1
1
1
CONDITIONS
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; 66.8 MHz
Fi
VDD = 3.3 V;
CIN
CINX
Logic Inputs
X1 & X2 pins
Ttrans
To 1st crossing of target Freq.
MIN
2
VSS-0.3
-5
-200
TYP
0.1
2.0
-100
100
MAX
VDD+0.3
0.8
5
160
14.318
27
Ts
From 1st crossing to 1% target Freq.
TSTAB
From VDD = 3.3 V to 1% target Freq.
TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads
TCPU-PCI1 VT = 1.5 V; CPU Leads
36
UNITS
V
V
mA
mA
mA
mA
MHz
5
45
pF
pF
2
ms
ms
-500
2
200
5
2
ms
500
6
ps
ns
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
Supply Current
Skew1
1
SYMBOL
IDD2.5OP
CONDITIONS
CL = 0 pF; 66.8 MHz
MIN
TYP
10
MAX
20
UNITS
mA
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads
TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
-500
2
200
5
500
6
ps
ns
Guaranteed by design, not 100% tested in production.
12
ICS9148-75
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
VOH2A
VOL2A
IOH2A
IOL2A
Rise Time
tr2A1
tf2A1
d t2A1
tsk2A1
tj1s2A1
tjabs2A1
Fall Time
Duty Cycle
Skew
Jitter, One Sigma
Jitter, Absolute
1
CONDITIONS
IOH = -28 mA
IOL = 27 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.5
33
TYP
2.6
0.35
-29
37
MAX
0.4
-23
UNITS
V
V
mA
mA
VOL = 0.4 V, VOH = 2.4 V
1.75
2
ns
VOH = 2.4 V, VOL = 0.4 V
1.1
2
ns
50
55
%
50
250
ps
VT = 1.5 V
45
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
-250
65
150
ps
165
250
ps
TYP
3
0.2
-60
50
MAX
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
VOH1
VOL1
IOH1
IOL1
Rise Time
tr1 1
VOL = 0.4 V, VOH = 2.4 V
1.8
2
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
1.6
2
ns
1
VT = 1.5 V
50
55
%
1
VT = 1.5 V
130
250
ps
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
40
200
150
250
ps
ps
135
500
250
650
ps
ps
tf1
Duty Cycle
d t1
Skew
tsk1
Jitter, One Sigma
Jitter, Absolute
1
tj1s1a
tj1s1b
CONDITIONS
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.4
41
45
1
tab s1a VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
tjabs1b
1
Guaranteed by design, not 100% tested in production.
13
-250
-650
0.4
-40
UNITS
V
V
mA
mA
ICS9148-75
Preliminary Product Preview
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
CONDITIONS
IOH = -28 mA
Output High Voltage
VOH1
IOL = 23 mA
Output Low Voltage
VOL1
VOH = 2.0 V
Output High Current
IOH1
VOL = 0.8 V
Output Low Current
IOL1
Rise Time1
Tr1
VOL = 0.4 V, VOH = 2.4 V
Fall Time1
Tf1
VOH = 2.4 V, VOL = 0.4 V
Duty Cycle1
1
Skew
1
Dt1
VT = 1.5 V
MIN
2.4
TYP
3
0.2
-60
50
41
45
Tsk1
VT = 1.5 V
Jitter, One Sigma1
Tj1s1
VT = 1.5 V
Jitter, Absolute1
Jitter, Absolute1
Tjabs1
Tjabs1
VT = 1.5 V (with synchronous PCI)
VT = 1.5 V (with asynchronous PCI)
MAX
UNITS
V
V
mA
mA
0.4
-40
1.75
2
ns
1.5
2
ns
50
55
%
200
500
ps
150
ps
-250
50
+250
ps
-400
400
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; C L = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
1
SYMBOL
VOH1
VOL1
IOH1
IOL1
CONDITIONS
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.4
41
TYP
3
0.2
-60
50
MAX
0.4
-40
UNITS
V
V
mA
mA
Rise Time
tr1
1
VOL = 0.4 V, VOH = 2.4 V
1.1
2
ns
Fall Time
tf1 1
VOH = 2.4 V, VOL = 0.4 V
1
2
ns
Duty Cycle
d t1 1
VT = 1.4 V
50
55
%
1
VT = 1.5 V
130
250
ps
tj1s1
VT = 1.5 V
Skew
Jitter, One Sigma1
tsk1
Jitter, Absolute1
tabs1a
tjabs1b
45
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
Guaranteed by design, not 100% tested in production.
14
-5
-6
2
3
%
2.5
4.5
5
6
%
%
ICS9148-75
Preliminary Product Preview
Electrical Characteristics - 24MHz, 48MHz, REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
VOH5
VOL5
IOH5
IOL5
Rise Time
tr5 1
Fall Time
TYP
2.6
0.3
-32
25
MAX
VOL = 0.4 V, VOH = 2.4 V
2
4
ns
1
VOH = 2.4 V, VOL = 0.4 V
1.9
4
ns
1
VT = 1.5 V
45
50
55
%
VT = 1.5 V
VT = 1.5 V
-5
Duty Cycle
d t5
Jitter, One Sigma
tj1s5 1
tjabs5 1
Jitter, Absolute
1
tf5
CONDITIONS
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.4
16
Guaranteed by design, not 100% tested in production.
15
0.4
-22
UNITS
V
V
mA
mA
1
3
%
-
5
%
ICS9148-75
Preliminary Product Preview
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
3 Optional crystal load capacitors are
recommended.
Capacitor Values:
C1, C2 : Crystal load values determined by user
C3 : 100pF ceramic
All unmarked capacitors are 0.01 F ceramic
16
ICS9148-75
Preliminary Product Preview
Ordering Information
ICS9148yF-75-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
17
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.