ICS ICS952702YFLF-T

ICS952702
Integrated
Circuit
Systems, Inc.
Programmable Timing Control Hub for K7TM System
Recommended Application:
SiS746/746FX style chipset
Output Features:
•
1 - Pair of differential open drain CPU outputs
•
1 - Single-ended open drain CPU output
•
8 - PCICLK @ 3.3V including 2 PCI clock free running
•
2 - AGPCLK @ 3.3V
•
3 - REF @ 3.3V
•
2 - ZCLK @ 3.3V
•
2 - IOAPIC @ 2.5V
•
1 - 12_48MHz @ 3.3V
•
1 - 24_48MHz @ 3.3V
Key Specifications:
•
CPU Output Jitter <250ps
•
AGP Output Jitter <250ps
•
ZCLK Output Jitter <250ps
•
PCI Output Jitter <500ps
•
CPU-AGP/PCI/ZCLK skew: 2.5ns~3.5ns
Features/Benefits:
•
Selectable synchronous/asynchronous AGP/PCI
frequency
•
Programmable output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I2C Index read/write and block read/write
operations.
•
Uses external 14.318MHz reference or XTAL input.
Pin Configuration
Functionality
48 VDDLAPIC
Bit4
Bit3
Bit2
Bit1
Bit0
CPU
ZCLK
AGP
PCI
**FS0/REF0 2
VDDREF 1
47 IOAPIC1
**FS1/REF1 3
46 IOAPIC0
**FS4/REF2 4
45 GNDAPIC
44 CPU_STOP#*
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MHz
200.00
200.99
200.00
206.00
133.33
214.00
218.00
222.00
100.00
100.99
100.00
103.00
100.00
107.00
109.00
111.00
166.67
166.99
166.67
MHz
133.33
133.99
66.67
137.33
133.33
142.66
145.33
148.00
133.33
134.65
66.67
137.33
133.33
142.66
145.33
148.00
133.33
133.59
66.67
MHz
66.67
67.00
66.67
68.67
66.67
71.33
72.67
74.00
66.67
67.33
66.67
68.67
66.67
71.33
72.67
74.00
66.67
66.80
66.67
MHz
33.33
33.50
33.33
34.33
33.33
35.67
36.33
37.00
33.33
33.66
33.33
34.33
33.33
35.67
36.33
37.00
33.33
33.40
33.33
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
137.33
140.00
142.66
145.33
148.00
133.33
133.99
66.67
68.67
70.00
71.33
72.67
74.00
66.67
67.00
34.33
35.00
35.67
36.33
37.00
1
1
1
1
1
1
1
1
171.67
175.00
178.34
181.67
185.00
133.33
133.99
66.67
68.67
70.00
71.33
72.67
74.00
33.33
34.33
35.00
35.67
36.33
37.00
GNDREF 5
X1 6
43 CPUCLKODT1
42 RESET#
X2 7
41 GNDCPU
40 CPUCLKODT0
ZCLK1 10
VDDZ 11
*PCI_STOP# 12
VDDPCI 13
**FS2/PCICLK_F0 14
*FS3/PCICLK_F1 15
ICS952702
GNDZ 8
ZCLK0 9
PCICLK0 16
39 CPUCLKODC0
38 VDDCPU
37 AGND
36 AVDD
35 SCLK
34 SDATA
33 PD#*
GNDPCI 18
32 GNDAGP
31 AGPCLK0
VDDPCI 19
30 AGPCLK1
PCICLK2 20
29 VDDAGP
PCICLK3 21
28 AVDD48
PCICLK4 22
27 12_48MHz/SEL12#_48MHz*
PCICLK1 17
PCICLK5 23
26 24_48MHz/SEL24#_48MHz**
GNDPCI 24
25 GND48
48-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
0795D—05/06/05
133.33
137.33
140.00
142.66
145.33
148.00
137.33
140.00
142.66
145.33
148.00
33.33
33.50
ICS952702
Integrated
Circuit
Systems, Inc.
General Description
The ICS952702 is a two chip clock solution for desktop designs using SIS 746 style chipsets. When used with a zero delay
buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals
for such a system.
The ICS952702 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
Frequency
Dividers
PLL2
12_48MHZ
24_48MHZ
X1
X2
XTAL
REF (2:0)
CPUCLKODT (1:0)
CPUCLKODC0
CPU_STOP#
PCI_STOP#
RESET#
SCLK
Programmable
Spread
PLL1
SEL24_48MHZ
SEL12_48
Programmable
Frequency
Dividers
Control
Logic
PD#
SDATA
STOP
Logic
IOAPIC (1:0)
PCICLKF (1:0)
PCICLK (5:0)
ZCLK (1:0)
FS (4:0)
AGPCLK (1:0)
Power Groups
Pin Number
Description
VDD
GND
1
5
REF output, Xtal
11
8
Hyper ZCLK output
28
25
24/48MHz fixed, Fixed PLL (Fix1)
13,19
18,24
PCICLK output
29
32
AGP output
48
45
IOAPIC output
38
41
CPU_T/C output
36
37
CPU PLL, CPU MCLK
0795D—05/06/05
2
ICS952702
Integrated
Circuit
Systems, Inc.
Pin Description
PIN #
PIN NAME
PIN
TYPE
1
VDDREF
PWR
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
**FS0/REF0
**FS1/REF1
**FS4/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
ZCLK1
VDDZ
*PCI_STOP#
VDDPCI
**FS2/PCICLK_F0
*FS3/PCICLK_F1
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
GND48
I/O
I/O
I/O
PWR
IN
OUT
PWR
OUT
OUT
PWR
IN
PWR
I/O
I/O
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
26
24_48MHz/SEL24#_48MHz**
27
12_48MHz/SEL12#_48MHz*
28
29
30
31
32
AVDD48
VDDAGP
AGPCLK1
AGPCLK0
GNDAGP
33
PD#*
34
35
36
37
38
SDATA
SCLK
AVDD
AGND
VDDCPU
39
CPUCLKODC0
40
CPUCLKODT0
41
GNDCPU
42
RESET#
43
CPUCLKODT1
44 CPU_STOP#*
45 GNDAPIC
46 IOAPIC0
47 IOAPIC1
48 VDDLAPIC
* Internal Pull-Up Resistor
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin for the REF outputs.
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin for the ZCLK outputs
3.3V Hyperzip clock output.
3.3V Hyperzip clock output.
Power supply for ZCLK clocks, nominal 3.3V
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low.
Power supply for PCI clocks, nominal 3.3V
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Ground pin for the 48MHz outputs
Selectable 24 or 48MHz clock output / Latched select input for 24/48MHz output. 0=24MHz,
I/O
1 = 48MHz.
Selectable 12 or 48MHz clock output / Latched select input for 12/48MHz output. 0=12MHz,
I/O
1 = 48MHz.
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
PWR Power supply for AGP clocks, nominal 3.3V
OUT AGP clock output
OUT AGP clock output
PWR Ground pin for the AGP outputs
Asynchronous active low input pin used to power down the device into a low power state. The
IN
internal clocks are disabled and the VCO and the crystal are stopped. The latency of the
power down will not be greater than 1.8ms.
I/O
Data pin for I2C circuitry 5V tolerant
IN
Clock pin of I2C circuitry 5V tolerant
PWR 3.3V Analog Power pin for Core PLL
PWR Analog Ground pin for Core PLL
PWR Supply for CPU clocks, 3.3V nominal
"Complememtary" clocks of differential pair CPU outputs. These open drain outputs need an
OUT
external 1.5V pull-up.
True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V
OUT
pull-up.
PWR Ground pin for the CPU outputs
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
OUT
This signal is active low.
True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V
OUT
pull-up.
IN
Stops all CPUCLK besides the free running clocks
PWR Ground pin for the IOAPIC outputs.
OUT IOAPIC clock outputs, norminal 2.5V.
OUT IOAPIC clock outputs, norminal 2.5V.
PWR Power pin for the IOAPIC outputs. 2.5V.
** Internal Pull-Down Resistor
0795D—05/06/05
3
ICS952702
Integrated
Circuit
Systems, Inc.
General SMBus serial interface information for the ICS952702
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each
byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
0795D—05/06/05
4
Not acknowledge
stoP bit
ICS952702
Integrated
Circuit
Systems, Inc.
Table 1: Frequency Selection Table
FSA
FSB
Bit4
Bit3
Bit2
Bit1
Bit0
CPU
ZCLK
AGP
PCI
Spread %
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MHz
133.33
133.99
66.67
137.33
133.33
142.66
145.33
148.00
133.33
134.65
66.67
137.33
133.33
142.66
145.33
148.00
MHz
66.67
67.00
66.67
68.67
66.67
71.33
72.67
74.00
66.67
67.33
66.67
68.67
66.67
71.33
72.67
74.00
MHz
33.33
33.50
33.33
34.33
33.33
35.67
36.33
37.00
33.33
33.66
33.33
34.33
33.33
35.67
36.33
37.00
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
1
0
0
0
0
MHz
200.00
200.99
200.00
206.00
133.33
214.00
218.00
222.00
100.00
100.99
100.00
103.00
100.00
107.00
109.00
111.00
166.67
133.33
66.67
33.33
+/-0.35% center
1
0
0
0
1
166.99
133.59
66.80
33.40
+/-0.35% center
1
0
0
1
0
166.67
66.67
66.67
33.33
+/-0.35% center
1
0
0
1
1
171.67
137.33
68.67
34.33
+/-0.35% center
1
0
1
0
0
175.00
140.00
70.00
35.00
+/-0.35% center
1
0
1
0
1
178.34
142.66
71.33
35.67
+/-0.35% center
1
1
0
0
1
1
1
1
0
1
181.67
185.00
145.33
148.00
72.67
74.00
36.33
37.00
+/-0.35% center
+/-0.35% center
1
1
0
0
0
133.33
133.33
66.67
1
1
0
0
1
133.99
133.99
67.00
33.33
33.50
+/-0.35% center
+/-0.35% center
1
1
0
1
0
133.33
66.67
66.67
33.33
+/-0.35% center
1
1
0
1
1
137.33
137.33
68.67
34.33
+/-0.35% center
1
1
1
0
0
140.00
140.00
70.00
35.00
+/-0.35% center
1
1
1
0
1
142.66
142.66
71.33
35.67
+/-0.35% center
1
1
1
1
1
1
1
1
0
1
145.33
148.00
145.33
148.00
72.67
74.00
36.33
37.00
+/-0.35% center
+/-0.35% center
0795D—05/06/05
5
ICS952702
Integrated
Circuit
Systems, Inc.
I2C Table: Frequency Select Register
Byte 0
Pin #
Name
Control Function
Type
0
1
PWD
RW
Latch Inputs
IIC
0
SS_EN
SEL12/48MHz
FS4
Frequency H/W IIC
Select
Spread Enable Control
Output Control
Freq Select Bit 4
RW
RW
RW
OFF
12MHz
ON
48MHz
1
Latch
Latch
-
FS3
Freq Select Bit 3
RW
-
FS2
Freq Select Bit 2
RW
Bit 1
-
FS1
Freq Select Bit 1
RW
Latch
Bit 0
-
FS0
Freq Select Bit 0
RW
Latch
Name
Control Function
Type
0
1
PWD
24_48MHz
48MHz
SEL24/48MHz
IOAPIC1
IOAPIC0
Reserved
CPUCLKODT1
CPUCLKODT0/C0
Output Control
Output Control
Output Control
Output Control
Output Control
Reserved
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
24MHz
Disable
Disable
Reserved
Disable
Disable
Enable
Enable
48MHz
Enable
Enable
Reserved
Enable
Enable
1
1
Latch
1
1
0
1
1
Name
Control Function
Type
0
1
PWD
PCICLK_F1
PCICLK_F0
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Name
Control Function
Type
0
1
PWD
REF2
REF1
REF0
Reserved
ZCLK1
ZCLK0
AGPCLK1
AGPCLK0
Output Control
Output Control
Output Control
Reserved
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Reserved
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Reserved
Enable
Enable
Enable
Enable
1
1
1
0
1
1
1
1
Bit 7
-
FS Source
Bit 6
Bit 5
Bit 4
27
-
Bit 3
Bit 2
Latch
See Table 1: Frequency Selection Table
Latch
I2C Table: Output Control Register
Byte 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
26
27
47
46
43
40/39
I2C Table: Output Control Register
Byte 2
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15
14
23
22
21
20
17
16
I2C Table: Output Control Register
Byte 3
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
4
3
2
10
9
30
31
0795D—05/06/05
6
ICS952702
Integrated
Circuit
Systems, Inc.
I2C Table: Async Frequency Selection & Output Skew Control Register
Byte 4
Pin #
Name
Control Function
Bit 7
-
ASYNC2
Bit 6
-
ASYNC1
Bit 5
Bit 4
-
ASYNC0
Reserved
Bit 3
-
ZCLKSkw1
Type
RW
Fix PLL Async Freq
Programming bits
RW
RW
-
RW
CPU-ZCLK Skew Control
Bit 2
-
ZCLKSkw0
Bit 1
-
AGPSkw1
RW
RW
CPU-AGP Skew Control
Bit 0
-
AGPSkw0
PWD
See Table 2: Async Frequency Selection
Table
RW
Reserved
1
0
RW
0
0
0
1
-
00:0ps; 01:250ps; 10:500ps; 11:750ps
This byte will advance or delay the skew
by 250ps per step
0
00:0ps; 01:250ps; 10:500ps; 11:750ps
This byte will advance or delay the skew
by 250ps per step
0
1
1
Table 2: Asynchronous Frequency Selection Table
B4 bit7
B4 bit6
B4 bit5
ZCLK
AGP
PCI
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Main PLL
132
132
132
Main PLL
132
132
132
Main PLL
66
75.4
88
Main PLL
66
75.4
88
Main PLL
33
37.7
44
Main PLL
33
33
33
Table 3: AGP Divider Ratio Combination Table
Divider (1:0)
Bit
0
1
10
11
LSB
Divider (3:2)
*01
0
0
1
10
11
Address
1
4
3
5
15
Div
100
101
110
111
Address
10
2
8
6
10
30
Div
11
4
16
12
20
60
Div
1000
1001
1010
1011
Address
1100
1101
1110
1111
Address
I2C Table: Revision ID & Output Divider Control Register
Byte 5
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
-
REV_ID3
REV_ID2
REV_ID1
REV_ID0
Bit 2
-
AGPDiv2
Bit 1
-
Bit 0
-
AGPDiv1
AGPDiv0
AGPDiv3
Control Function
Revision ID
AGP divider ratio can be
configured via these 4
bits individually.
Type
0
1
PWD
R
R
R
R
RW
-
-
0
0
0
1
1
RW
RW
RW
0795D—05/06/05
7
See Table 3: Divider Ratio Combination
Table
1
0
1
MSB
8
32
24
40
120
Div
ICS952702
Integrated
Circuit
Systems, Inc.
I2C Table: Slew Rate Control Register
Byte 6
Pin #
Name
Control Function
Type
PCICLK_F(1:0) Strength
Control
RW
PCICLK(2:0) Strength
Control
RW
RW
0
1
PWD
Bit 7
-
PCIStr1
Bit 6
-
PCIStr0
Bit 5
-
PCIStr1
Bit 4
-
PCIStr0
Bit 3
-
PCIStr1
Bit 2
-
PCIStr0
PCICLK(5:3) Strength
Control
Bit 1
-
AGPStr1
AGPStr0
AGPCLK Strength
Control
RW
RW
Name
Control Function
Type
0
1
PWD
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R
R
R
R
R
R
R
R
-
-
1
1
1
1
1
1
1
1
Control Function
Type
0
1
PWD
Writing to this register will
configure how many
bytes will be read back,
default is 0F = 15 bytes.
RW
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
0
0
1
1
1
1
Type
RW
0
Disable
1
Enable
PWD
0
R
Normal
Alarm
X
R
Normal
Alarm
X
RW
Disable
Enable
0
290ms base
1160ms base
0
Bit 0
RW
RW
RW
00=.63x; 01=.75x; 10=.88x; 11=1x
Strength
1
00=.63x; 01=.75x; 10=.88x; 11=1x
Strength
1
00=.63x; 01=.75x; 10=.88x; 11=1x
Strength
1
00=.7x; 01=.8x; 10=.9x; 11=1x Strength
1
1
1
1
1
I2C Table: Reserved Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
I2C Table: Byte Count Register
Byte 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
I2C Table: Watchdog Timer Control Register
Byte 9
Pin #
Name
Control Function
Bit 7
WDSA control
WD soft alarm control
WD Hard Alarm Status
Bit 6
WDHRB
Read back
WD Soft Alarm Status
Bit 5
WDSRB
Read back
Bit 4
-
GR_EN
Bit 3
-
WDTCtrl
Gear Shift Reset Enable
Bit 2
-
WD2
Watch Dog Time base
control
WD Timer Bit2
Bit 1
-
WD1
WD Timer Bit1
RW
Bit 0
-
WD0
WD Timer Bit0
RW
RW
0795D—05/06/05
8
RW
These bits represent X*290ms (or
1.16S) the watchdog timer will wait
before it goes to alarm mode. Default is
7 X 290ms =2s.
1
1
1
ICS952702
Integrated
Circuit
Systems, Inc.
I2C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Control Function
Name
M/N Programming
Enable
Watchdog Enable
WD Safe Frequency
Mode
Type
0
1
PWD
RW
Disable
Enable
0
RW
Disable
Enable
0
RW
Latched FS/Byte0
WD B10 b(4:0)
0
Bit 7
-
M/NEN
Bit 6
-
WDEN
Bit 5
-
WDFSEN
Bit 4
-
WD SF4
RW
Bit 3
-
WD SF3
RW
Bit 2
-
WD SF2
Bit 1
-
WD SF1
RW
0
Bit 0
-
WD SF0
RW
0
Watch Dog Safe Freq
Programming bits
RW
0
Writing to these bit will configure the
safe frequency as Byte 0 Bit (4:0)
1
0
I2C Table: VCO Frequency Control Register
Byte 11
Pin #
Name
Control Function
Type
0
1
PWD
N Divider Bit 8
N Divider Bit 9
The decimal
representation of M Div
(5:0) + 2 is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
RW
RW
RW
RW
-
-
X
X
X
X
RW
-
-
X
RW
-
-
X
RW
-
-
X
RW
-
-
X
Bit 7
Bit 6
Bit 5
Bit 4
-
N Div8
N Div9
M Div5
M Div4
Bit 3
-
M Div3
Bit 2
-
M Div2
Bit 1
-
M Div1
Bit 0
-
M Div0
I2C Table: VCO Frequency Control Register
Byte 12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
Name
Control Function
Type
0
1
PWD
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
The decimal
representation of N Div
(9:0) + 8 is equal to VCO
divider value. Default at
power up = latch-in or
Byte 0 Rom table.
RW
RW
RW
RW
RW
RW
RW
RW
-
-
X
X
X
X
X
X
X
X
I2C Table: Spread Spectrum Control Register
Byte 13
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
Name
Control Function
Type
0
1
PWD
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
These Spread Spectrum
bits will program the
spread percentage. It is
recommended to use ICS
Spread % table for
spread programming.
RW
RW
RW
RW
RW
RW
RW
RW
-
-
X
X
X
X
X
X
X
X
0795D—05/06/05
9
ICS952702
Integrated
Circuit
Systems, Inc.
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . .
4.6 V
3.6V
GND –0.5 V to VDD +0.5 V
0°C to +70°C
–65°C to +150°C
115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating Supply
Current
Power Down Supply
Current
Input frequency
VIH
VIL
IIH
IIL1
IIL2
Input Capacitance1
Spread Modulation
Frequency1
1
CONDITIONS
MIN
TYP
2
VSS - 0.3
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
MAX
UNITS
VDD + 0.3
0.8
5
V
V
mA
mA
mA
-5
-200
IDD(op)
Full Active, CL = full load; Select @ 100MHz
180
250
mA
IDDPD
All diff pairs tri-stated
1.2
12
mA
Fi
CIN
CINX
VDD = 3.3 V;
Logic Inputs
X1 & X2 pins
11
14.318
27
30
16
5
45
MHz
pF
pF
33
KHz
1.8
ms
3.5
3.5
3.5
ns
ns
ns
fSS
Clk Stabilization
TSTAB
Skew
Skew
TCPU-AGP
TCPU-ZCLK
TCPU-PCI
320
From VDD Power-Up of de-assertion of PD#
to 1st clock.
CPU @ crossing, AGP @ 1.5V
CPU @ crossing, ZCLK @ 1.5V
VT = 1.5 V CPU @ crossing, PCI @ 1.5V
Skew1
1
Guaranteed by design, not 100% tested in production.
0795D—05/06/05
10
2.5
2.5
2.5
3.1
3.3
2.9
ICS952702
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - CPUCLKODC/T
TA = 0 - 70°C; VDD = 1.7 V +/-5%; CL = 5 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output High Voltage
Output Low Voltage
Output Low Current
VOH2B
VOL2B
IOL2B
tr2B
tf2B
1
Rise Time
1
Fall Time
Differential voltage1
AC
Differential voltage-
CONDITIONS
Termination to Vpull-up(external)
Termination to Vpull-up(external)
VOL = 0.3 V
VOL = 20%, VOH = 80%
VOH = 80%, VOL = 20%,
MIN
TYP
1
MAX
UNITS
1.2
0.4
V
V
mA
ns
ns
18
0.38
0.44
0.9
0.9
VDIF
0.4
V
VDIF
1
DC
Differential Crossover
VX
1
Voltage
1
dt2B
VT = 50%
Duty Cycle
1
tsk2B
VT = 50%
Skew
Jitter Diff, Cycle-totjcyc-cyc2B VT = VX
1
cycle
Jitter SE, Cycle-totjcyc-cyc2B VT = 1.0V
1
cycle
1
tjabs2B
VT = 50%
Jitter, Absolute
Notes:
1
- Guaranteed by design, not 100% tested in production.
0.2
V
550
1200
1250
mV
45
51.5
140
55
200
%
ps
60
250
ps
100
250
ps
250
ps
MAX
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
ps
-250
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3 V,+/-5%; CL = 30 pF
PARAMETER
SYMBOL
CONDITIONS
Output High Voltage
VOH1
IOH = -18 mA
Output Low Voltage
VOL1
IOL = 9.4 mA
Output High Current
IOH1
VOH = 2.0 V
Output Low Current
IOL1
VOL = 0.8 V
1
Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
1
Duty Cycle
dt1
VT = 1.5 V
1
Skew
tsk1
VT = 1.5 V
1
VT = 1.5 V
tjcyc-cyc
Jitter
VT = 1.5 V
tjabs1
1
Guaranteed by design, not 100% tested in production.
0795D—05/06/05
11
MIN
2.1
TYP
16
45
2.25
2.1
50
170
150
0.4
-22
57
2.5
2.5
55
500
500
500
ICS952702
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - AGPCLK, ZCLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Frequency
FO1
1
Output Impedance
RDSP1
VO = VDD*(0.5)
1
IOH = -1 mA
Output High Voltage
VOH
1
IOL = 1 mA
Output Low Voltage
VOL
V
OH = 1.0 V
1
Output High Current
IOH
VOH = 3.135 V
VOL = 1.95 V
1
Output Low Current
IOL
VOL = 0.4 V
1
Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
1
VOH = 2.4 V, VOL = 0.4 V
Fall Time
tf1
1
VT = 1.5 V
Duty Cycle
dt1
1
Skew
tsk1
VT = 1.5 V
1
tjcyc-cyc
VT = 1.5 V
Jitter
MIN
TYP
66.66
12
2.4
MAX
55
0.55
-33
-33
38
UNITS
MHz
Ω
V
V
mA
0.5
0.5
45
2
1.9
50.5
70
240
30
2.2
2.2
55
250
250
MIN
2.6
TYP
MAX
mA
ns
ns
%
ps
ps
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
IOH = -12 mA
Output High Voltage
VOH5
Output Low Voltage
VOL5
IOL = 9 mA
VOH = 2.0 V
Output High Current
IOH5
Output Low Current
IOL5
VOL = 0.8 V
1
Rise Time
tr5
VOL = 0.4 V, VOH = 2.4 V
1
Fall Time
tf5
VOH = 2.4 V, VOL = 0.4 V
1
Duty Cycle
dt5
VT = 1.5 V
t
VT = 1.5 V
jcyc-cyc5
1
Jitter
tjabs5
VT = 1.5 V
0795D—05/06/05
12
16
45
1.6
1.6
53
210
UNITS
V
0.4
V
-22
mA
mA
4
ns
4
ns
55
%
1000
ps
800
ps
ICS952702
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - IOAPIC
TA = 0 - 70°C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
1
Output Impedance
RDSP4B
VO = VDD*(0.5)
1
VO = VDD*(0.5)
Output Impedance
RDSN4B
IOH = -5.5 mA
Output High Voltage
VOH4\B
IOL = 9.0 mA
Output Low Voltage
VOL4B
VOH = 1.0 V
1
Output High Current
IOH
VOH = 2.375 V
VOL = 1.2 V
Output Low Current
IOL1
VOL = 0.3 V
1
Rise Time
tr4B
VOL = 0.4 V, VOH = 2.0 V
1
VOH = 2.0 V, VOL = 0.4 V
Fall Time
tf4B
1
VT = 1.25 V
Duty Cycle
dt4B
VT = 1.25 V
Jitter
tjcyc-cyc
Tsk41
Skew
1
MIN
9
9
2
TYP
MAX
30
30
0.4
-27
-27
27
0.4
0.4
45
UNITS
Ω
Ω
V
V
mA
30
1.6
1.6
55
500
250
1
1
49.8
300
10
mA
ns
ns
%
ps
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 12_48MHz, 24_48MHz
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
VO = VDD*(0.5)
Output Impedance
RDSP11
IOH = -1 mA
Output High Voltage
VOH1
IOL = 1 mA
Output Low Voltage
VOL1
VOH = 1.0 V
Output High Current
IOH1
VOH = 3.135 V
VOL = 1.95 V
Output Low Current
IOL1
VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
Rise Time
tr11
VOH = 2.4 V, VOL = 0.4 V
Fall Time
tf11
1
VT = 1.5 V
Duty Cycle
dt1
Jitter
1
tjcyc-cyc1
VT = 1.5 V
Guaranteed by design, not 100% tested in production.
0795D—05/06/05
13
MIN
20
2.4
TYP
MAX
60
0.4
-29
-23
29
0.5
0.5
45
UNITS
Ω
V
V
mA
1.5
1.5
52.8
27
4
4
55
mA
ns
ns
%
370
500
ps
ICS952702
Integrated
Circuit
Systems, Inc.
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K)
resistor is used to provide both the solid CMOS programming
voltage needed during the power-up programming period and to
provide an insignificant load on the output clock during the
subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0795D—05/06/05
14
ICS952702
Integrated
Circuit
Systems, Inc.
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their next
high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion
of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state
of the stopped CPU signals is CPUT=Low and CPUC=High. There is to be no change to the output drive current values. The CPUT
will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUT
CPUC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
Normal
Normal
0
iref * Mult
Float
0795D—05/06/05
15
ICS952702
Integrated
Circuit
Systems, Inc.
c
N
L
E1
E
INDEX
AREA
1 2
α
h x 45°
D
A
300 mil SSOP
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
SEE VARIATIONS
SEE VARIATIONS
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
0.635 BASIC
0.025 BASIC
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A1
e
b
-C-
N
SEATING
PLANE
48
VARIATIONS
D mm.
MIN
MAX
15.75
16.00
D (inch)
MIN
.620
Ref erence Doc.: JEDEC Publicat ion 95, M O-118
.10 (.004) C
300 mil SSOP Package
Ordering Information
ICS952702yFLFT
Example:
ICS 95XXXX y FLF - T
Designation for tape and reel packaging
Annealed Lead Free (optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
0795D—05/06/05
Prefix
ICS = Standard Device
16
MAX
.630
ICS952702
Integrated
Circuit
Systems, Inc.
Revision History
Rev.
D
Issue Date Description
5/6/2005 Added LF Ordering Information
Page #
16
0795D—05/06/05
17