ICS950703 Integrated Circuit Systems, Inc. Programmable Timing Control HubTM for P4TM Recommended Application: Intel Tehema and Tehema-E Chipsets Output Features: • 4 Differential CPU Clock Pairs @ 3.3V • 2 - 3V MREF clocks for memory reference seeds, (separate single ended but 180 degrees out of phase) • 4 - 66MHz 3V66 output • 10 - 3V 33MHz PCI clocks • 2 - 48MHz clocks (180 degrees out of phase) • 2 - 14.318 reference output (180 degrees out of phase) Key Specifications: • 3V66 Output jitter <300ps • CPU Output Jitter <200ps • MREF Output jitter <250ps Frequency Table Features/Benefits: • QuadRomTM frequency selection. • Programmable asynchronous 3V66/PCI frequency. • Programmable output frequency. • Programmable output divider ratios. • Programmable output rise/fall time. • Programmable output skew. • Programmable spread percentage for EMI control. • Programmable watch dog safe frequency. • Support I2C Index read/write and block read/write operations. • Uses external 14.318MHz reference input. Pin Configuration Bit3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 Bit2 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 Bit1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 Bit0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 CPU MHz 90.00 100.00 100.90 103.00 105.00 108.00 110.00 112.00 115.00 118.00 120.00 122.00 125.00 127.00 130.00 133.60 120.00 133.33 133.90 136.00 138.00 140.00 142.00 144.00 145.00 148.00 150.00 152.00 154.00 156.00 158.00 160.00 MREF MHz 45.00 50.00 50.45 51.50 52.50 54.00 55.00 56.00 57.50 59.00 60.00 61.00 62.50 63.50 65.00 66.80 60.00 66.67 66.95 68.00 69.00 70.00 71.00 72.00 72.50 74.00 75.00 76.00 77.00 78.00 79.00 80.00 PCI MHz 30.00 33.33 33.63 34.33 35.00 36.00 36.67 37.33 38.33 39.33 40.00 40.67 41.67 42.33 43.33 44.53 30.00 33.33 33.48 34.00 34.50 35.00 35.50 36.00 36.25 37.00 37.50 38.00 38.50 39.00 39.50 40.00 3V66 MHz 60.00 66.67 67.27 68.67 70.00 72.00 73.33 74.67 76.67 78.67 80.00 81.33 83.33 84.67 86.67 89.07 60.00 66.67 66.95 68.00 69.00 70.00 71.00 72.00 72.50 74.00 75.00 76.00 77.00 78.00 79.00 80.00 GND 1 56 VDDMREF MULTSEL0/REF0 2 55 3VMREF MULTSEL1/REF1 3 54 3VMREF_B VDDREF 4 53 GNDMREF X1 5 52 SCLK X2 6 51 CPUCLKT3 GNDREF 7 50 CPUCLKC3 PCICLK0 8 49 VDDCPU PCICLK1 9 48 CPUCLKT2 VDDPCI 10 47 CPUCLKC2 PCICLK2 11 46 GNDCPU PCICLK3 12 45 CPUCLKT1 GNDPCI 13 PCICLK4 14 PCICLK5 15 VDDPCI 16 ICS950703 Bit4 Sel133/100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 PCICLK6 17 44 CPUCLKC1 43 VDDCPU 42 CPUCLKT0 41 CPUCLKC0 40 GNDCPU **FS2/PCICLK7 18 39 IREF GNDPCI 19 38 AVDD **FS3/PCICLK8 20 37 GND **SEL100_133#/PCICLK9 21 36 VDD3V66 VDDPCI 22 35 3V66_3 SDATA 23 34 3V66_2 GND48 24 33 GND3V66 *FS0/48MHz_0 25 32 GND3V66 **FS1/48MHz_1 26 31 3V66_1 AVDD48 27 30 3V66_0 PD# 28 29 VDD3V66 56-SSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor 0690D—05/14/04 ICS950703 Integrated Circuit Systems, Inc. General Description The ICS950703 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with Rambus RDRAM memory. It provides all necessary clock signals for such a system. The ICS950703 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/ N control can configure output frequency with resolution up to 0.1MHz increment. This part also provides 128 frequency selections via ICS QuadROMTM technology as an alternate to M/N programming. Block Diagram Frequency Dividers PLL2 X1 X2 48MHZ (1:0) XTAL REF (1:0) 4 4 MULTSEL (1:0) FS (3:0) Control Logic SEL100_133# SDATA Programmable Spread PLL1 Programmable Frequency Dividers STOP Logic CPUCLKT (3:0) CPUCLKC (3:0) PCICLK (9 :0) MREF MREF_B 3V66 (3:0) SCLK PD# I REF Power Groups Pin Number AVDD GND Description 4 7 REF output, Crystal 27 24 48MHz fixed, Fixed PLL CPU PLL, CPU Master Clock, 38 37 VDD GND -- 10, 16, 22 13, 19 PCI outputs 29, 36 32, 33 3V66 outputs 43, 49 40, 46 CPU Outputs, IREF, MULTSEL 56 53 MREF outputs 0690D—05/14/04 2 ICS950703 Integrated Circuit Systems, Inc. Pin Description PIN PIN PIN # NAME TYPE 1 GND 2 MULTSEL0/REF0 3 MULTSEL1/REF1 DESCRIPTION PWR Ground pin. 3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference I/O clock. 3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference I/O clock. PWR Ref, XTAL power supply, nominal 3.3V 4 VDDREF 5 X1 I/O Frequency select latch input pin / 3.3V PCI free running clock output. 6 X2 I/O Frequency select latch input pin / 3.3V PCI free running clock output. 7 GNDREF PWR Ground pin for the REF outputs. 8 PCICLK0 OUT PCI clock output. 9 PCICLK1 I/O Watchdog enable latch input/ 3.3V PCI clock output. 10 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 11 PCICLK2 OUT PCI clock output. 12 PCICLK3 OUT PCI clock output. 13 GNDPCI PWR Ground pin for the PCI outputs 14 PCICLK4 OUT PCI clock output. 15 PCICLK5 OUT PCI clock output. 16 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 17 PCICLK6 OUT PCI clock output. 18 **FS2/PCICLK7 19 GNDPCI 20 **FS3/PCICLK8 21 **SEL100_133#/PCICLK9 22 VDDPCI 23 SDATA 24 GND48 I/O Frequency select latch input pin / 3.3V PCI clock output. PWR Ground pin for the PCI outputs I/O Frequency select latch input pin / 3.3V PCI clock output. Latched select input for 100 or 133.3MHz selection. 0=133MHz, 1 = 100MHz / 3.3V PCI I/O clock output. PWR Power supply for PCI clocks, nominal 3.3V I/O Data pin for SMBus circuitry, 5V tolerant. PWR Ground pin for the 48MHz outputs 25 *FS0/48MHz_0 I/O Frequency select latch input pin / Fixed 48MHz clock output. 3.3V 26 **FS1/48MHz_1 I/O Frequency select latch input pin / Fixed 48MHz clock output. 3.3V 27 AVDD48 28 PD# PWR Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V IN Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used to power down the device. The internal clocks are disabled and the VCO and the crystal are stopped. * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2X drive 0690D—05/14/04 3 ICS950703 Integrated Circuit Systems, Inc. Pin Description (Continued) PIN PIN PIN # NAME TYPE DESCRIPTION 29 VDD3V66 PWR Power pin for the 3V66 clocks. 30 3V66_0 OUT 3.3V 66.66MHz clock output 31 3V66_1 OUT 3.3V 66.66MHz clock output 32 GND3V66 PWR Ground pin for the AGP outputs 33 GND3V66 PWR Ground pin for the AGP outputs 34 3V66_2 OUT 3.3V 66.66MHz clock output 35 3V66_3 OUT 3.3V 66.66MHz clock output 36 VDD3V66 PWR Power pin for the 3V66 clocks. 37 GND PWR Ground pin. 38 AVDD 39 IREF 40 GNDCPU 41 CPUCLKC0 42 CPUCLKT0 43 VDDCPU 44 CPUCLKC1 45 CPUCLKT1 46 GNDCPU 47 CPUCLKC2 48 CPUCLKT2 49 VDDCPU 50 CPUCLKC3 51 CPUCLKT3 52 SCLK PWR 3.3V Analog Power pin for Core PLL This pin establishes the reference current for the differential current-mode output pairs. This OUT pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. PWR Ground pin for the CPU outputs Complimentary clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External OUT resistors are required for voltage bias. PWR Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External OUT resistors are required for voltage bias. PWR Ground pin for the CPU outputs Complimentary clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External OUT resistors are required for voltage bias. PWR Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External OUT resistors are required for voltage bias. IN Clock pin of SMBus circuitry, 5V tolerant. 53 GNDMREF PWR Ground pin for the 3VMREF outputs. 54 3VMREF_B OUT 3V reference output to memory clock driver (180 degree out of phase with 3VMREF) 55 3VMREF OUT 3V reference output to memory clock driver 56 VDDMREF PWR Power supply for 3VMREF clocks, nominal 3.3V * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2X drive 0690D—05/14/04 4 ICS950703 Integrated Circuit Systems, Inc. Maximum Allowed Current Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND Pin Description Condition Powerdown Mode (PWRDWN# = 0) 40mA Full Active 360mA CPUCLK Swing Select Functions MULTSEL0 BYTE 1 BIT 3 Board Target Trace/Term Z Reference R, Iref= Vdd/(3*Rr) Output Current Voh @ Z, Iref=2.32mA 0 0 60 ohms Rr = 475 1% Iref = 2.32mA Ioh = 4*Iref 0.56V @ 60 0 0 50 ohms Rr = 475 1% Iref = 2.32mA Ioh = 4*Iref 0.47V @ 50 0 1 60 ohms Rr = 475 1% Iref = 2.32mA Ioh = 6*Iref 0.85V /2 60 0 1 50 ohms Rr = 475 1% Iref = 2.32mA Ioh = 6*Iref 0.71V @ 50 1 0 60 ohms Rr = 475 1% Iref = 2.32mA Ioh = 5*Iref 0.71V @ 60 1 0 50 ohms Rr = 475 1% Iref = 2.32mA Ioh = 5*Iref 0.59V @ 50 1 1 60 ohms Rr = 475 1% Iref = 2.32mA Ioh = 7*Iref 0.99V @ 60 1 1 50 ohms Rr = 475 1% Iref = 2.32mA Ioh = 7*Iref 0.82V @ 50 0 0 30 (DC equiv) Rr = 221 1% Iref = 5mA Ioh = 5*Iref 0.75V @ 30 0 0 25 (DC equiv) Rr = 221 1% Iref = 5mA Ioh = 5*Iref 0.62V @ 20 0 1 30 (DC equiv) Rr = 221 1% Iref = 5mA Ioh = 6*Iref 0.90V @ 30 0 1 25 (DC equiv) Rr = 221 1% Iref = 5mA Ioh = 6*Iref 0.75V @ 20 1 0 30 (DC equiv) Rr = 221 1% Iref = 5mA Ioh = 4*Iref 0.60 @ 20 1 0 25 (DC equiv) Rr = 221 1% Iref = 5mA Ioh = 4*Iref 0.5V @ 20 1 1 30 (DC equiv) Rr = 221 1% Iref = 5mA Ioh = 7*Iref 1.05V @ 30 1 1 25 (DC equiv) Rr = 221 1% Iref = 5mA Ioh = 7*Iref 0.84V @ 20 0690D—05/14/04 5 ICS950703 Integrated Circuit Systems, Inc. General I2C serial interface information How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P *See notes on the following page. 0690D—05/14/04 6 Not acknowledge stoP bit ICS950703 Integrated Circuit Systems, Inc. Table1: QuadRom Frequency Selection Table Bit6 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit5 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit4 Sel133/100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit2 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz MREF MHz PCI MHz 3V66 MHz 90.00 100.00 100.90 103.00 105.00 108.00 110.00 112.00 115.00 118.00 120.00 122.00 125.00 127.00 130.00 133.60 120.00 133.33 133.90 136.00 138.00 140.00 142.00 144.00 145.00 148.00 150.00 152.00 154.00 156.00 158.00 160.00 45.00 50.00 50.45 51.50 52.50 54.00 55.00 56.00 57.50 59.00 60.00 61.00 62.50 63.50 65.00 66.80 60.00 66.67 66.95 68.00 69.00 70.00 71.00 72.00 72.50 74.00 75.00 76.00 77.00 78.00 79.00 80.00 30.00 33.33 33.63 34.33 35.00 36.00 36.67 37.33 38.33 39.33 40.00 40.67 41.67 42.33 43.33 44.53 30.00 33.33 33.48 34.00 34.50 35.00 35.50 36.00 36.25 37.00 37.50 38.00 38.50 39.00 39.50 40.00 60.00 66.67 67.27 68.67 70.00 72.00 73.33 74.67 76.67 78.67 80.00 81.33 83.33 84.67 86.67 89.07 60.00 66.67 66.95 68.00 69.00 70.00 71.00 72.00 72.50 74.00 75.00 76.00 77.00 78.00 79.00 80.00 Notes: Table1 continues on the next three pages. 0690D—05/14/04 7 ICS950703 Integrated Circuit Systems, Inc. QuadRomTM Frequency Selection Table Description Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Sel133/100 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCO MHZ CPUCLK MHz 3V66 MHz PCICLK MHz 456.00 460.00 464.00 468.00 472.00 476.00 480.00 484.00 488.00 492.00 500.00 508.00 516.00 524.00 532.00 540.00 456.00 459.00 462.00 465.00 468.00 471.00 474.00 477.00 480.00 483.00 486.00 489.00 492.00 495.00 498.00 501.00 114.00 115.00 116.00 117.00 118.00 119.00 120.00 121.00 122.00 123.00 125.00 127.00 129.00 131.00 133.00 135.00 152.00 153.00 154.00 155.00 156.00 157.00 158.00 159.00 160.00 161.00 162.00 163.00 164.00 165.00 166.00 167.00 76.00 76.67 77.33 78.00 78.67 79.33 80.00 80.67 81.33 82.00 83.33 84.67 86.00 87.33 88.67 90.00 76.00 76.50 77.00 77.50 78.00 78.50 79.00 79.50 80.00 80.50 81.00 81.50 82.00 82.50 83.00 83.50 38.00 38.33 38.67 39.00 39.33 39.67 40.00 40.33 40.67 41.00 41.67 42.33 43.00 43.67 44.33 45.00 38.00 38.25 38.50 38.75 39.00 39.25 39.50 39.75 40.00 40.25 40.50 40.75 41.00 41.25 41.50 41.75 Notes: Continuation of Table1 from previous page. 0690D—05/14/04 8 ICS950703 Integrated Circuit Systems, Inc. QuadRomTM Frequency Selection Table Description Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Sel133/100 FS3 FS2 FS1 FS0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCO MHZ CPUCLK MHz 3V66 MHz PCICLK MHz 400.02 408.00 420.00 432.00 444.00 456.00 468.00 480.00 492.00 504.00 516.00 528.00 540.00 552.00 564.00 576.00 588.00 600.00 612.00 624.00 636.00 648.00 660.00 672.00 666.68 668.00 672.00 676.00 680.00 684.00 688.00 692.00 66.67 68.00 70.00 72.00 74.00 76.00 78.00 80.00 82.00 84.00 86.00 88.00 90.00 92.00 94.00 96.00 98.00 100.00 102.00 104.00 106.00 108.00 110.00 112.00 166.67 167.00 168.00 169.00 170.00 171.00 172.00 173.00 66.67 68.00 70.00 72.00 74.00 76.00 78.00 80.00 82.00 84.00 86.00 88.00 90.00 92.00 94.00 96.00 98.00 100.00 102.00 104.00 106.00 108.00 110.00 112.00 66.67 66.80 67.20 67.60 68.00 68.40 68.80 69.20 33.34 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 42.00 43.00 44.00 45.00 46.00 47.00 48.00 49.00 50.00 51.00 52.00 53.00 54.00 55.00 56.00 33.33 33.40 33.60 33.80 34.00 34.20 34.40 34.60 Notes: Continuation of Table1 from previous page. 0690D—05/14/04 9 ICS950703 Integrated Circuit Systems, Inc. QuadRomTM Frequency Selection Table Description Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Sel133/100 FS3 FS2 FS1 FS0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCO MHZ CPUCLK MHz 3V66 MHz PCICLK MHz 696.00 700.00 704.00 708.00 712.00 716.00 720.00 724.00 320.00 330.00 340.00 350.00 360.00 370.00 380.00 390.00 400.00 402.00 404.00 406.00 408.00 412.00 416.00 420.00 424.00 428.00 432.00 436.00 440.00 444.00 448.00 452.00 174.00 175.00 176.00 177.00 178.00 179.00 180.00 181.00 160.00 165.00 170.00 175.00 180.00 185.00 190.00 195.00 200.00 201.00 202.00 203.00 204.00 206.00 208.00 210.00 212.00 214.00 216.00 218.00 220.00 222.00 224.00 226.00 69.60 70.00 70.40 70.80 71.20 71.60 72.00 72.40 53.33 55.00 56.67 58.33 60.00 61.67 63.33 65.00 66.67 67.00 67.33 67.67 68.00 68.67 69.33 70.00 70.67 71.33 72.00 72.67 73.33 74.00 74.67 75.33 34.80 35.00 35.20 35.40 35.60 35.80 36.00 36.20 26.67 27.50 28.33 29.17 30.00 30.83 31.67 32.50 33.33 33.50 33.67 33.83 34.00 34.33 34.67 35.00 35.33 35.67 36.00 36.33 36.67 37.00 37.33 37.67 Notes: Continuation of Table1 from previous page. 0690D—05/14/04 10 ICS950703 Integrated Circuit Systems, Inc. I2C Table: Frequency Select Register Byte 0 Pin # Name Bit 7 - FS Source Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - FS6 FS5 FS4 FS3 FS2 FS1 FS0 Control Function Frequency H/W IIC Select Freq Select Bit 6 Freq Select Bit 5 Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Selcet Bit 0 Type RW RW RW RW RW RW RW RW I2C Table: Spreading, Device Behavior and Output Control Register Byte 1 Pin # Name Control Function Type Bit 7 RW SS1 Spread Select 1 Bit 6 SS0 Spread Select 0 RW Spread Enable Bit 5 SSEN RW Control Bit 4 Reserved Reserved RW 51/50 Bit 3 RW CPUT/C3 Output Control 48/47 Bit 2 CPUT/C2 Output Control RW 45/44 Bit 1 CPUT/C1 Output Control RW 42/41 Bit 0 CPUT/C0 Output Control RW 0 Latch Inputs 1 PWD IIC 0 See Table 1: Quad TM Rom Frequency Selection Table 0 0 0 0 0 0 1 0 1 See Table 2: Spread Spectrum Table PWD 0 0 Disable Enable 0 Disable Disable Disable Disable Enable Enable Enable Enable 0 1 1 1 1 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 Table2: Spread Spectrum Select SS1 SS0 (Byte 1 bit 7) 0 (Byte 1 bit 6) 0 Spread % 0.35% 0 1 1 0 1 1 Downspread % Note 0.32% Default 0.50% 0.45% Spread 2 0.70% 0.75% Spread 3 1.00% 1.00% Spread 4 I2C Table: Output Control Register Byte 2 Pin # Name 18 Bit 7 PCICLK7 17 Bit 6 PCICLK6 15 Bit 5 PCICLK5 14 Bit 4 PCICLK4 12 Bit 3 PCICLK3 11 Bit 2 PCICLK2 9 Bit 1 PCICLK1 8 Bit 0 PCICLK0 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control 0690D—05/14/04 11 Type RW RW RW RW RW RW RW RW ICS950703 Integrated Circuit Systems, Inc. I2C Table: Output Control Register Byte 3 Pin # Name 26 Bit 7 48MHz_1 25 Bit 6 48MHz_0 Bit 5 Reserved Bit 4 Reserved 55 Bit 3 3VMREF 54 Bit 2 3VMREF_B 21 Bit 1 PCICLK_9 20 Bit 0 PCICLK_8 Control Function Output Control Output Control Reserved Reserved Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable PWD 1 1 0 1 1 1 1 1 I2C Table: Output Control Register Byte 4 Pin # Name 3 Bit 7 REF1 2 Bit 6 REF0 Bit 5 Reserved 35 Bit 4 3V66_3 Bit 3 Reserved 34 Bit 2 3V66_2 31 Bit 1 3V66_1 30 Bit 0 3V66_0 Control Function Output Control Output Control Reserved Output Control Reserved Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 Control Function Reserved FIX_2 PLL Control 3V66/PCI Freq Source Select Async Rom SEL_2 Async Rom SEL_1 Async Rom SEL_0 Async Divider SEL_1 Async Divider SEL_0 Type RW RW 0 OFF CPU_PLL Sync 1 ON FIX_PLL Async PWD 0 1 I2C Table: Output Control Register Byte 5 Pin # Name Bit 7 Reserved Bit 6 PLL2EN Bit 5 - AEN Bit 4 Bit 3 Bit 2 - AFS4 AFS3 AFS2 Bit 1 - AFS1 Bit 0 - AFS0 0690D—05/14/04 12 RW RW RW RW RW RW See Table 3: Async 3V66/PCI Frequency Selection Table 0 0 0 0 0 1 ICS950703 Integrated Circuit Systems, Inc. Table 3: Async 3V66/PCI Frequency Selection Table Byte 5 Bit4 Byte 5 Bit3 Byte 5 Bit2 Byte 5 Bit1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 I2C Table: Read Back Register Byte 6 Pin # Name Bit 7 - WDHRB Bit 6 - MULTSEL0 Bit 5 - MULTSEL1 Bit 4 - Bit 3 Bit 2 Bit 1 Bit 0 - SEL100/ 133#RB FS3RB FS2RB FS1RB FS0RB I2C Table: Vendor & Revision ID Register Byte 7 Pin # Name Bit 7 RID3 Bit 6 RID2 Bit 5 RID1 Bit 4 RID0 Bit 3 VID3 Bit 2 VID2 Bit 1 VID1 Bit 0 VID0 Byte 5 Bit0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3V66 66.00 74.25 84.86 99.00 64.00 72.00 82.29 96.00 59.26 66.67 76.19 88.89 67.22 75.63 86.43 100.83 70.00 78.75 90.00 105.00 PCI 33.00 37.13 42.43 49.50 32.00 36.00 41.15 48.00 29.63 33.34 38.10 44.45 33.61 37.82 43.22 50.42 35.00 39.38 45.00 52.50 Control Function WD Hard Alarm Status Read back MULTSEL0 Read back MULTISEL1 Read back SEL100/133 # Read back FS3 Read back FS2 Read back FS1 Read back FS0 Read back Type 0 1 PWD R - - X R - - X R - - X R - - X R R R R - - X X X X Control Function Type R R R R R R R R 0 - 1 - PWD 0 0 0 1 0 0 0 1 REVISION ID VENDOR ID 0690D—05/14/04 13 ICS950703 Integrated Circuit Systems, Inc. I2C Table: Byte Count Register Byte 8 Pin # Name Bit 7 BC7 Bit 6 BC6 Bit 5 BC5 Bit 4 BC4 Bit 3 BC3 Bit 2 BC2 Bit 1 BC1 Bit 0 BC0 I2C Table: Watchdog Timer Register Byte 9 Pin # Name Bit 7 WD7 Bit 6 WD6 Bit 5 WD5 Bit 4 WD4 Bit 3 WD3 Bit 2 WD2 Bit 1 WD1 Bit 0 WD0 Control Function Writing to this register will configure how many bytes will be read back, default is 0FH = 15 bytes. Control Function These bits represent X*290ms the watchdog timer will wait before it goes to alarm mode. Default is 10*290ms = 2.9 seconds. I2C Table: VCO Control Select Bit & WD Timer Control Register Byte 10 Pin # Name Control Function M/N Programming Bit 7 M/NEN Enable Bit 6 WD Enable WD Enable WD Safe Frequency Bit 5 WD SF Mode Mode Bit 4 WDSF4 Writing to these bit Bit 3 WDSF3 will configure the Bit 2 WDSF2 safe frequency as Bit 1 WDSF1 Byte 0 Bit (4:0) Bit 0 WDSF0 I2C Table: VCO Frequency Control Register Byte 11 Pin # Name Control Function Bit 7 NDiv8 N Divider Bit 8 The decimal Bit 6 MDiv6 representation of M Bit 5 MDiv5 Div (6:0) + 2 is equal Bit 4 MDiv4 to reference divider Bit 3 MDiv3 Bit 2 value. Default at MDiv2 Bit 1 MDiv1 power up = latch-in Bit 0 MDiv0 or Byte 0 Rom table. 0690D—05/14/04 14 Type RW RW RW RW RW RW RW RW 0 - 1 - PWD 0 0 0 0 1 1 1 1 Type RW RW RW RW RW RW RW RW 0 - 1 - PWD 0 0 0 0 1 0 1 0 Type 0 1 PWD RW Disable Enable 0 RW Enable B10 Bit(4:0) - 0 RW RW RW RW RW Disable Latched Inputs - 0 0 0 0 0 Type RW RW RW RW RW RW RW RW 0 - 1 - PWD X X X X X X X X RW 0 ICS950703 Integrated Circuit Systems, Inc. I2C Table: VCO Frequency Control Register Byte 12 Pin # Name Control Function Bit 7 NDiv7 The decimal Bit 6 NDiv6 representation of N Bit 5 NDiv5 Div (8:0) +8 is equal Bit 4 NDiv4 to VCO divider Bit 3 NDiv3 value. Default at Bit 2 NDiv2 power up = latch-in Bit 1 NDiv1 or Byte 0 Rom table. Bit 0 NDiv0 Type RW RW RW RW RW RW RW RW 0 - 1 - PWD X X X X X X X X I2C Table: Spread Spectrum Control Register Byte 13 Pin # Name Control Function These Spread Bit 7 SSP7 Spectrum bits will Bit 6 SSP6 program the spread Bit 5 SSP5 pecentage. It is Bit 4 SSP4 recommended to Bit 3 SSP3 Bit 2 SSP2 use ICS Spread % Bit 1 SSP1 table for spread Bit 0 SSP0 programming. Type RW RW RW RW RW RW RW RW 0 - 1 - PWD X X X X X X X X I2C Table: Spread Spectrum Control Register Byte 14 Pin # Name Control Function Bit 7 Reserved Reserved Bit 6 Reserved Reserved Bit 5 SSP13 It is recommended to Bit 4 SSP12 use ICS Spread % Bit 3 SSP11 table for spread Bit 2 SSP10 Bit 1 SSP9 programming. Bit 0 SSP8 Type R R R RW RW RW RW RW 0 - 1 - PWD 0 0 X X X X X X I2C Table: Output Divider Control Register Byte 15 Pin # Name Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 CPUDiv3 Bit 2 CPUDiv2 Bit 1 CPUDiv1 Bit 0 CPUDiv0 Type RW RW RW RW RW RW RW RW 0 - 1 - PWD X X X X X X X X Control Function Reserved Reserved Reserved Reserved CPU divider ratio can be configured via these 4 bits individually. 0690D—05/14/04 15 See Table 4: Divider Ratio Combination Table ICS950703 Integrated Circuit Systems, Inc. Table 4: Divider Ratio Combination Table (CPU & MREF) Divider (3:2) 00 Divider (1:0) Bit 01 10 1 2 11 MSB 8 4 00 0000 2 0100 4 1000 8 1100 16 01 0001 3 0101 6 1001 12 1101 24 10 0010 5 0110 10 1010 20 1110 40 11 0011 7 0111 14 1011 28 1111 56 LSB Address Div Address Div Address Div Address Div 1 PWD X X X X X X X X I2C Table: Output Divider Control Register Byte 16 Pin # Name Control Function PCI divider ratio can Bit 7 PCIDiv3 be configured via Bit 6 PCIBit 2 these 4 bits Bit 5 PCIDiv4 Bit 4 PCIBit 3 individually. 3V66 divider ratio Bit 3 3V66Div3 can be configured Bit 2 3V66Div2 via these 4 bits Bit 1 3V66Div1 Bit 0 individually. 3V66Div0 Type RW RW RW RW RW RW RW RW I2C Table: Output Divider Control Register Byte 17 Pin # Name Control Function PCI 3V66 Phase Invert 3V66 Phase Invert Reserved CPU Phase Invert Reserved Reserved Reserved Reserved Type 0 1 PWD RW Default Inverse X RW RW RW RW RW RW RW Default Default - Inverse Inverse - X X X X X X X Control Function CPUC/T(2:1) to CPU C/T(3,0) Skew Cntrol Reserved Reserved CPUC/T(3,0) to CPU C/T(2:1) Skew Cntrol Reserved Reserved Type RW RW RW RW RW RW RW RW Bit 7 - PCIINV 3V66 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - 3V66INV Reserved CPUINV Reserved Reserved Reserved Reserved I2C Table: Group Skew Control Register Byte 18 Pin # Name Bit 7 CPUSkw1 Bit 6 CPUSkw0 Bit 5 Reserved Bit 4 Reserved Bit 3 CPUSkw1 Bit 2 CPUSkw0 Bit 1 Reserved Bit 0 Reserved 0690D—05/14/04 16 0 See Table 4: Divider Ratio Combination Table See Table 4: Divider Ratio Combination Table 0 1 See Table 5: 2-bit Skew Control Table See Table 5: 2-bit Skew Control Table - PWD 1 1 1 1 1 1 1 1 ICS950703 Integrated Circuit Systems, Inc. Table 5: 2 Bits Skew Programming Table 4 Step 0 1 LSB 0 0ps 250ps - 1 MSB 500ps 750ps - - - - I2C Table: Group Skew Control Register Byte 19 Pin # Name Bit 7 MREFSkw3 Bit 6 MREFSkw2 Bit 5 MREFSkw1 Bit 4 MREFSkw0 Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 Reserved I2C Table: Group Skew Control Register Byte 20 Pin # Name Bit 7 PCISkw3 Bit 6 PCISkw2 Bit 5 PCISkw1 Bit 4 PCISkw0 Bit 3 PCISkw3 Bit 2 PCISkw2 Bit 1 PCISkw1 Bit 0 PCISkw0 Control Function CPUC/T to MREF/MREF_B Skew Cntrol Reserved Reserved Reserved Reserved Control Function CPU to PCI(9:6) Skew Control CPU to PCI(5:0) Skew Control Table 6: 7-Steps Skew Programming Table 7 Step 11 10 01 00 11 900 ps 750 ps 600 ps 450 ps 10 N/A N/A N/A 300 ps 01 N/A N/A N/A 150 ps 00 N/A N/A N/A 0.0 ps LSB MSB 0690D—05/14/04 17 Type RW RW RW RW RW RW RW RW Type RW RW RW RW RW RW RW RW 0 1 See Table 6: 7-Steps Skew Control Table - - 0 1 See Table 6: 7-Steps Skew Control Table See Table 6: 7-Steps Skew Control Table PWD 0 1 0 0 0 1 0 0 PWD 0 1 1 0 0 1 1 0 ICS950703 Integrated Circuit Systems, Inc. I2C Table: Group Skew Control Register Byte 21 Pin # Name Bit 7 3V66Skw1 Bit 6 3V66Skw0 Bit 5 Reserved Bit 4 Reserved Bit 3 3V66Skw1 Bit 2 3V66Skw0 Bit 1 Reserved Bit 0 Reserved Control Function CPU to 3V66(3:2) Skew Control Reserved Reserved CPU to 3V66(1:0) Skew Control Reserved Reserved Type RW RW RW RW RW RW RW RW I2C Table: Slew Rate Control Register Byte 22 Pin # Name Bit 7 48MHzSlw1 Bit 6 48MHzSlw0 Bit 5 48MHzSlw1 Bit 4 48MHzSlw0 Bit 3 3V66Slw1 Bit 2 3V66Slw0 Bit 1 3V66Slw1 Bit 0 3V66Slw0 Control Function 48MHz_0 Slew Rate Control 48MHz_1 Slew Rate Control 3V66 (0) Slew Rate Control 3V66 (3:1) Slew Rate Control Type RW RW RW RW RW RW RW RW 0 - 1 - PWD 1 0 1 0 1 0 1 0 I2C Table: Slew Rate Control Register Byte 23 Pin # Name Bit 7 Reserved Bit 6 Reserved Bit 5 PCISlw1 Bit 4 PCISlw0 Bit 3 PCISlw1 Bit 2 PCISlw0 Bit 1 PCISlw1 Bit 0 PCISlw0 Control Function Reserved Reserved PCI (9:7), (5:2) Slew Rate Control PCI (6) Slew Rate Control PCI (1:0) Slew Rate Control Type RW RW RW RW RW RW RW RW 0 - 1 - PWD 1 0 1 0 1 0 1 0 I2C Table: Slew Rate Control Register Byte 24 Pin # Name Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 REFSlw1 Bit 2 REFSlw0 Bit 1 REFSlw1 Bit 0 REFSlw0 Control Function Reserved Reserved Reserved Reserved REF1 Slew Rate Control REF0 Slew Rate Control Type RW RW RW RW RW RW RW RW 0 - 1 - PWD 0 0 0 0 1 0 1 0 0690D—05/14/04 18 0 1 See Table 5: 2-bit Skew Control Table See Table 5: 2-bit Skew Control Table - PWD 0 0 0 0 0 0 0 0 ICS950703 Integrated Circuit Systems, Inc. Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage SYMBOL VIH VIL IIH VIN = VDD; Inputs with no pull-down resistors IIH VIN = VDD; Inputs with pull-down resistors IIL1 VIN = 0 V; Inputs with no pull-up resistors IIL2 VIN = 0 V; Inputs with pull-up resistors Input High Current Input Low Current Operating Supply Current Powerdown Current Input Frequency Pin Inductance 1 Input Capacitance 1 2 CONDITIONS IDD3.3OP IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX Clk Stabilization1,2 TSTAB Delay 1 tPZH,t PZL tPHZ,t PLZ CL = Full load; Select @ 100 MHz CL =Full load; Select @ 133 MHz IREF=5 mA VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From PowerUp or deassertion of PowerDown to 1st clock. Output enable delay (all outputs) Output disable delay (all outputs) Guaranteed by design, not 100% tested in production. See timing diagrams for buffered and un-buffered timing requirements. 0690D—05/14/04 19 MIN 2 V SS - 0.3 TYP -200 -200 MAX UNITS V DD + 0.3 V 0.8 V 200 µA 5 mA 200 µA -5 229 220 27 1 1 mA 230 233 35 14.318 360 360 45 36 5 6 45 mA mA mA MHz nH pF pF pF 1 3 ms 10 10 ns ns ICS950703 Integrated Circuit Systems, Inc. Electrical Characteristics - CPU (0.7V Select) TA = 0 - 70°C; VDD=3.3V Rs=33Ω , Rp(pulldown) = 50Ω (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Statistical measurement on single ended Voltage High VHigh signal using oscilloscope math function. VLow Voltage Low Measurement on single ended signal Vovs Max Voltage using absolute value. Vuds Min Voltage tr VOL = 0.175V, VOH = 0.525V Rise Time VOH = 0.525V VOL = 0.175V tf Fall Time 1 2 Duty Cycle dt3 Measurement from differential wavefrom Skew Jitter, Cycle to cycle tsk3 VT = 50% VT = 50% 1 tjcyc-cyc MIN 660 -150 MAX 850 150 1150 UNITS -450 175 175 TYP 788 16 818 11 306 330 700 700 ps ps 45 50.2 55 % 120 49 150 150 ps ps TYP MAX UNITS MHz Ω mV mV Guaranteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin. Electrical Characteristics - MREF/MREF_B TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance V O = VDD*(0.5) RDSP11 1 Output High Voltage IOH = -1 mA V OH 1 Output Low Voltage V OL Output High Current Output Low Voltage IOH1 IOL1 t r11 t f11 dt11 Rise Time Fall Time Duty Cycle Jitter t jcyc-cyc MIN 12 65 2.4 V I OL = 1 mA V V 1 OH@MIN = 1.0 V, Voh@MAX=3.135 OH@MIN = 1.95 V, Voh@MAX=0.4 0.4 V -33 -33 mA 30 38 mA 2 ns V OL = 0.4 V, VOH = 2.4 V 0.5 1.8 V OH = 2.4 V, VOL = 0.4 V 0.5 1.7 2 ns V T = 1.5 V 45 54 55 % 138 250 ps VT = 1.5 V 3V66 1 Guaranteed by design, not 100% tested in production. 0690D—05/14/04 20 ICS950703 Integrated Circuit Systems, Inc. Electrical Characteristics - 3V66 TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance V O = VDD*(0.5) RDSP11 1 IOH = -1 mA Output High Voltage V OH 1 Output Low Voltage V OL Output High Current Output Low Voltage IOH1 IOL MIN TYP 66.66 12 V V OH@MIN 65 UNITS MHz Ω 0.4 V 2.4 V I OL = 1 mA 1 MAX = 1.0 V, Voh@MAX=3.135 -33 -33 mA = 1.95 V, Voh@MAX=0.4 30 38 mA OH@MIN Rise Time t r1 1 V OL = 0.4 V, VOH = 2.4 V 0.5 1.8 2 ns Fall Time t f11 V OH = 2.4 V, VOL = 0.4 V 0.5 1.51 2 ns Duty Cycle dt11 V T = 1.5 V 45 50 55 % V T = 1.5 V 52 250 ps VT = 1.5 V 3V66 160 250 ps TYP 14.32 MAX UNITS MHz Ω V V Skew Jitter tsk1 1 t jcyc-cyc 1 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - 48MHz TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) 1 PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle SYMBOL FO1 Jitter tjcyc-cyc RDSP1 1 VOH 1 VOL 1 IOH 1 IOL 1 tr1 1 tf1 1 dt1 1 1 CONDITIONS MIN VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V VOL @MIN = 1.95 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V 20 2.4 Guaranteed by design, not 100% tested in production. 0690D—05/14/04 21 -29 29 1 1 45 60 1.15 1.4 52.5 0.4 -23 27 4 4 55 184 350 ns ns % ps ICS950703 Integrated Circuit Systems, Inc. Electrical Characteristics - REF TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 V O = VDD*(0.5) Output Impedance RDSP11 1 IOH = -1 mA Output High Voltage V OH 1 MIN TYP 14.32 20 MAX 60 UNITS MHz Ω 0.4 V 2.4 V I OL = 1 mA Output Low Voltage V OL Output High Current IOH1 = 1.0 V -29 -23 Output Low Current 1 VOL @MIN = 1.95 V 29 27 Rise Time t r1 1 V OL = 0.4 V, VOH = 2.4 V 1 1.1 4 ns Fall Time t f11 V OH = 2.4 V, VOL = 0.4 V 1 0.92 4 ns V T = 1.5 V 45 46.4 55 % 192 1000 ps Duty Cycle Jitter IOL dt1 V 1 t jcyc-cyc 1 OH@MIN V T = 1.5 V 1 Guaranteed by design, not 100% tested in production. 0690D—05/14/04 22 ICS950703 Integrated Circuit Systems, Inc. Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 0690D—05/14/04 23 ICS950703 Integrated Circuit Systems, Inc. c N L E1 INDEX AREA E 1 2 α h x 45° D A A1 In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A 2.41 2.80 A1 0.20 0.40 b 0.20 0.34 c 0.13 0.25 SEE VARIATIONS D E 10.03 10.68 E1 7.40 7.60 0.635 BASIC e h 0.38 0.64 L 0.50 1.02 SEE VARIATIONS N 0° 8° α -Ce SEATING PLANE b N .10 (.004) C 56 300 mil SSOP Package In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS D mm. MIN MAX 18.31 18.55 D (inch) MIN .720 Reference Doc.: JEDEC Publication 95, M O-118 10-0034 Ordering Information ICS950703yFLF-T Example: ICS XXXX y F LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0690D—05/14/04 24 MAX .730