[AKD5367A-A] AKD5367A-A AK5367A Evaluation Board Rev.0 GENERAL DESCRIPTION AKD5367A-A is an evaluation board for the digital audio 24bit 96kHz A/D converter, AK5367A. The AKD5367A-A includes the input circuit and also has a digital interface transmitter. Further, the AKD5367A-A can achieve the interface with digital audio systems via optical connector. And it can achieve the direct interface with AKEMD’s D/A converter evaluation boards of via 10-line flat cable. Ordering Guide AKD5367A-A --- AK5367A Evaluation Board (Cable for connecting with printer port of IBM-AT compatible PC and control software are enclosed with board. This control software does not support Windows NT.) FUNCTION • DIT with optical output • BNC connector for an external clock input • 10pin header for serial control interface AVDD CVDD DVDD AGND MCLK_EXT D3V DGND +3.3V REG JP3 AVDD CVDD JP2 12.288MHz DVDD VSS1 VSS2 LIN1 RIN1 JP4 Clock Generator LIN2 RIN2 LIN3 RIN3 AK5367A AK4104 (DIT) PORT1 Opt Out LIN4 RIN4 PORT2 ROM PORT3 uP-I/F 10pin Header Figure 1. AKD5367A-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM095000> 2008/06 -1- [AKD5367A-A] Operation Sequence 1) Set up the power supplies lines. (Note 1) Connector name Connector color Voltage Used for AVDD Orange +4.75~+5.25 V AVDD for AK5367A, Regulator T1. DVDD Red +3.0~+3.6V DVDD for AK5367A CVDD Red +3.0~+3.6V CVDD for AK5367A D3V Red +3.0~+3.6V AK4104, Logic circuit AGND Black 0V Analog ground DGND Black 0V Digital ground Comment and attention This connector must be connected. This connector is used when DVDD of AK5367A is supplied from DVDD connector without regulator T1. In this case, JP2 should be open. (Default) This connector is used when CVDD of AK5367A is supplied from CVDD connector without regulator T1. In this case, JP3 should be open. (Default) This connector is used when power of AK4104 and logic circuit is supplied from +3.3V connector without regulator T1. In this case, JP4 should be open. (Default) This connector must be connected. This connector is used when DGND is supplied separately from AGND. In this case, JP1 should be open. (Default) Default Setting +5V +3.3V +3.3V +3.3V 0V 0V Table 1. Power Supply Lines Note 1. Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK5367A and AK4104 should be reset once bringing SW1 and SW2 = “L” and return it to “H” to upon power-up. Evaluation Mode (1) Slave mode When evaluating the AK5367A using the AK4104, the setting of the AK5367A’s audio interface format should be the same as the AK4104’s format. When the AK4104 is used, the audio interface format is the default setting of 16/24bit I2S compatible. Therefore, set DIF bit=”1” to agree with the AK4104’s format. (1-1) A/D evaluation using AK4104 DIT function PORT1 (DIT) is used. DIT generates audio bi-phase signal from received data and it is output through optical connector (TOTX141). It is possible to connect AKEMD’s D/A converter evaluation boards on the digital-amplifier. The clock can be generated from crystal oscillator X1 or be input from J11 (BNC) or PORT2 (ROM). <KM095000> 2008/06 -2- [AKD5367A-A] (1-1-1) The MCLK is generated from crystal oscillator X1 Please set JP10 (CLK) “XTL”, open JP8 (XTE), and short JP5 (LRCK), JP6 (BICK), JP7 (MCLK), JP9 (EXT). MCLK can be selected to 256fs or 512fs with JP11 and JP12. In this case, please do not connect anything with PORT2 (ROM). JP7 JP8 JP9 JP10 MCLK XTE EXT CLK EXT JP6 BICK XTL JP5 LRCK Figure 2. Switch Setting when the MCLK is Generated from Crystal Oscillator X1 (1-1-2) The MCLK is input from BNC Please set JP10 (CLK) “EXT”, short JP5 (LRCK), JP6 (BICK), JP7 (MCLK) and JP8 (XTE), open JP9 (EXT). MCLK can be selected to 256fs or 512fs with JP11 and JP12. In this case, please do not connect anything with PORT2 (ROM). JP7 JP8 JP9 JP10 MCLK XTE EXT CLK EXT JP6 BICK XTL JP5 LRCK Figure 3. Switch Setting when the MCLK is Input from BNC (1-1-3) The MCLK, BICK and LRCK input from PORT2 Please open JP5 (LRCK), JP6 (BICK), JP7 (MCLK), JP8(XTE), JP9(EXT) and JP10(CLK) when input the external clock from PORT2 (ROM). JP8 XTE JP7 MCLK JP9 EXT JP10 CLK EXT JP6 BICK XTL JP5 LRCK Figure 4. Switch Setting when the External Clock is Input from PORT2 (ROM) (1-2) The A/D converter is evaluated with external AP equipment by using PORT2 (ROM) The analog to digital conversion data can be transmitted from PORT2 (ROM). The clock can be generated from crystal oscillator X1 or J11 (BNC) or PORT2 (ROM). Refer to (1-1-1), (1-1-2) and (1-1-3) to setting the switches. <KM095000> 2008/06 -3- [AKD5367A-A] (2) Master mode (2-1) A/D evaluation using AK4104 DIT function PORT1 (DIT) is used. DIT generates audio bi-phase signal from received data and it is output through optical connector (TOTX141). It is possible to connect AKEMD’s D/A converter evaluation boards on the digital-amplifier. The MCLK can be generated from crystal oscillator X1 or be input from J11 (BNC) or PORT2 (ROM). (2-1-1) The MCLK is generated from crystal oscillator X1 Please set JP10 (CLK) “XTL”, open JP5 (LRCK), JP6 (BICK) and JP8 (XTE), short JP7 (MCLK) and JP9 (EXT). In this case, please do not connect anything with PORT2 (ROM). JP7 JP8 JP9 JP10 MCLK XTE EXT CLK EXT JP6 BICK XTL JP5 LRCK Figure 5. Switch Setting when the MCLK is Generated from Crystal Oscillator X1 (2-1-2) The MCLK input from BNC Please set JP10 (CLK) “EXT”, short JP7 (MCLK) and JP8 (XTE), open JP5 (LRCK), JP6 (BICK) and JP9 (EXT). In this case, please do not connect anything with PORT2 (ROM). JP7 JP8 JP9 JP10 MCLK XTE EXT CLK EXT JP6 BICK XTL JP5 LRCK Figure 6. Switch Setting when the MCLK is Input from BNC (2-1-3) The MCLK is input from PORT2 Please open JP5 (LRCK), JP6 (BICK), JP7 (MCLK), JP8(XTE), JP9(EXT) and JP10(CLK) when input the external clock from PORT2 (ROM). JP8 XTE JP7 MCLK JP9 EXT JP10 CLK EXT JP6 BICK XTL JP5 LRCK Figure 7. Switch Setting when the MCLK is Input from PORT2 (ROM) (2-2) The A/D converter is evaluated with external AP equipment by using PORT2 (ROM) <KM095000> 2008/06 -4- [AKD5367A-A] The analog to digital conversion data can be transmitted from PORT2 (ROM). The MCLK can be generated from crystal oscillator X1 or J11 (BNC) or PORT2 (ROM). Refer to (2-1-1), (2-1-2) and (2-1-3) to setting the switches. <KM095000> 2008/06 -5- [AKD5367A-A] Other Jumper Pins Set Up 1. JP1 (GND): Analog and Digital ground OPEN: Separated. <Default> SHORT: Common. (The connector “DGND” can be open.) 2. JP2 (DVDD): Select AVDD for AK5367A OPEN: Supply from DVDD connector. <Default> SHORT: Supply from regulator T1. In this case, DVDD connector should be open. 3. JP3 (CVDD): Select DVDD for AK5367A OPEN: Supply from CVDD connector. <Default> SHORT: Supply from regulator T1. In this case, CVDD connector should be open. 4. JP4 (D3V): Select D3V for AK4104 and logic circuit OPEN: Supply from D3V connector. <Default> SHORT: Supply from regulator T1. In this case, D3V connector should be open. 5. JP11 (SBICK), JP12 (SLRCK): Select MCLK frequency 256: MCLK=256fs (=12.288MHz@fs=48kHz) <Default> 512: MCLK=512fs (=24.576MHz@fs=48kHz) The Function of the Toggle SW Upper-side is “H” and lower-side is “L”. [SW1] (5367_PDN): Resets of AK5367A. Keep “H” during normal operation. [SW2] (DIT_PDN): Resets of AK4104. Keep “H” during normal operation. Serial Control AKD5367A-A can be controlled through the printer port of IBM-AT compatible machine (parallel port). Please connect PORT3 (uP-I/F) and PC with bundled ten line flat cable. 10 wire flat cable PORT3 uP-I/F 10 Connect PC SDA(ACK) SDA AKD5367A-A SCL 1 10pin Header 10pin Connector Figure 8. 10pin Header Connecting <KM095000> 2008/06 -6- [AKD5367A-A] Analog Input/Output Circuit 1. Analog input circuit The analog input of AK5367A are input from J1~J8. J2 RIN1 R1 LIN1 short 47k MR-552LS J4 RIN2 R3 LIN2 short 47k MR-552LS J6 RIN3 R5 LIN3 short 47k MR-552LS R4 short 47k RIN2 C37 2 3 1 R6 short 47k RIN3 J8 RIN4 R7 LIN4 short 47k MR-552LS C39 2 3 1 + C38 2 3 1 C35 2 3 1 MR-552LS + J7 LIN4 RIN1 + C36 2 3 1 47k MR-552LS + J5 LIN3 short + C34 2 3 1 R2 MR-552LS + J3 LIN2 C33 2 3 1 + C32 2 3 1 + J1 LIN1 R8 short 47k RIN4 MR-552LS Figure 9. Analog Input Circuits * AKEMD assumes no responsibility for the trouble when using the circuit examples. <KM095000> 2008/06 -7- [AKD5367A-A] CONTROL SOFTWARE MANUAL Set-up of Evaluation Board and Control Software 1. Set up the AKD5367A-A according to previous term. 2. Connect IBM-AT compatible PC with AKD5367A-A by 10-line type flat cable (packed with AKD5367A-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AKD5367A-A Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “AKD5367A-A.exe” to set up the control program. 5. Then please evaluate according to the follows. Operation Flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. Explanation of Each Buttons 1. [Port Reset]: 2. [Write default]: 3. [All Write]: 4. [Function1]: 5. [Function2]: 6. [Function3]: 7. [Function4]: 8. [Function5]: 9. [SAVE]: 10. [OPEN]: 11. [Write] : Set up the USB interface board (AKDUSBIF-A) . Initialize the register of AK5367A. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of Data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM095000> 2008/06 -8- [AKD5367A-A] Explanation of Each Dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK5367A, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog]: Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK5367A, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog]: Dialog to evaluate ATT Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK5367A by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK5367A, click [OK] button. If not, click [Cancel] button. <KM095000> 2008/06 -9- [AKD5367A-A] 4. [Save] and [Open] 4-1. [Save] Save the current register setting data. The extension of file name is “akr”. (Operation flow) (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is “akr”. 4-2. [Open] The register setting data saved by [Save] is written to AK5367A. The file type is the same as [Save]. (Operation flow) (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button. <KM095000> 2008/06 - 10 - [AKD5367A-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval= “-1”. Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is “aks”. Figure 10. Window of [F3] <KM095000> 2008/06 - 11 - [AKD5367A-A] 6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure 11 opens. Figure 11. [F4] window <KM095000> 2008/06 - 12 - [AKD5367A-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 12. Figure 12. [F4] window (2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE]: The sequence file names can assign be saved. The file name is *.ak4. [OPEN]: The sequence file names assign that are saved in *.ak4 are loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change. <KM095000> 2008/06 - 13 - [AKD5367A-A] 7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 13 opens. Figure 13. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). (2) Click [WRITE] button, then the register setting is executed. 7-2. [SAVE] and [OPEN] buttons on right side [SAVE]: The register setting file names assign can be saved. The file name is *.ak5. [OPEN]: The register setting file names assign that are saved in *.ak5 are loaded. 7-3. Note (1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change. <KM095000> 2008/06 - 14 - [AKD5367A-A] MEASUREMENT RESULTS [Measurement condition] • Measurement unit • MCLK • BICK • fs • Bit • Power Supply • Interface • Temperature : Audio Precision, System Two Cascade : 512fs (fs=48kHz), 256fs (fs=96kHz) : 64fs : 48kHz, 96kHz : 24bit : AVDD = 5.0V, DVDD = CVDD = 3.3V : DSP Data (10pin Header : PSIA) : Room [Measurement Results] Parameter Result L2ch / R2ch L3ch / R3ch L1ch / R1ch Unit L4ch / R4ch ADC Analog Input Characteristics: S/(N+D): Filter=none (fs=48kHz, -1dBFS, BW=20kHz) (fs=96kHz, -1dBFS, BW=40kHz) 90.2 / 90.7 91.3 / 91.9 90.2 / 90.8 91.3 / 91.9 90.2 / 90.7 91.3 / 91.9 90.2 / 90.7 91.1 / 91.7 dB dB D-Range: Filter=A-weighted (fs=48kHz, -60dBFS, BW=20kHz) (fs=96kHz, -60dBFS, BW=40kHz) 101.7 / 101.9 102.6 / 102.8 101.8 / 101.9 102.6 / 102.8 101.7 / 101.9 102.6 / 102.8 101.7 / 102.0 102.0 / 102.2 dB dB S/N: Filter=A-weighted (fs=48kHz, No signal, BW=20kHz) (fs=96kHz, No signal, BW=40kHz) 101.8 / 102.1 102.7 / 102.9 101.9 / 102.1 102.7 / 102.9 101.9 / 102.1 102.7 / 102.9 101.9 / 102.1 102.3 / 102.5 dB dB <KM095000> 2008/06 - 15 - [AKD5367A-A] [ADC Plot: fs=48kHz] AKM AK5367A THD+N vs. Input Level AVDD=5V, DVDD=CVDD=3.3V, fs=48kHz, MCLK=512fs, fin=1kHz -70 -75 -80 -85 -90 d B F S -95 -100 -105 -110 -115 -120 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 14. THD+N vs. Input Level AKM AK5367A THD+N vs. Input Frequency AVDD=5V, DVDD=CVDD=3.3V, fs=48kHz, MCLK=512fs, -1dBFS input -70 TT T TT -75 -80 -85 -90 d B F S -95 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 15. THD+N vs. Input Frequency <KM095000> 2008/06 - 16 - [AKD5367A-A] AKM AK5367A Linearity AVDD=5V, DVDD=CVDD=3.3V, fs=48kHz, MCLK=512fs, fin=1kHz +0 TT T T -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 16. Linearity AKM AK5367A Frequency Response AVDD=5V, DVDD=CVDD=3.3V, fs=48kHz, MCLK=512fs, -1dBFS input -0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 d B F S -0.9 -1 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 -1.9 -2 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Hz Figure 17. Frequency Response <KM095000> 2008/06 - 17 - [AKD5367A-A] AKM AK5367A Crosstalk (Red=LIN1, Blue=RIN1) AVDD=5V, DVDD=CVDD=3.3V, fs=48kHz, MCLK=512fs, -1dBFS input -50 -55 -60 -65 -70 -75 -80 d B -85 -90 -95 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 18. Crosstalk AKM AK5367A FFT AVDD=5V, DVDD=CVDD=3.3V, fs=48kHz, MCLK=512fs, -1dBFS input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k Hz Figure 19. FFT Plot <KM095000> 2008/06 - 18 - [AKD5367A-A] AKM AK5367A FFT AVDD=5V, DVDD=CVDD=3.3V, fs=48kHz, MCLK=512fs, -60dBFS input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 20. FFT Plot AKM AK5367A FFT AVDD=5V, DVDD=CVDD=3.3V, fs=48kHz, MCLK=512fs, No signal input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k Hz Figure 21. FFT Plot <KM095000> 2008/06 - 19 - [AKD5367A-A] [ADC Plot: fs=96kHz] AKM AK5367A THD+N vs. Input Level AVDD=5V, DVDD=CVDD=3.3V, fs=96kHz, MCLK=256fs, fin=1kHz -70 -75 -80 -85 -90 d B F S -95 -100 -105 -110 -115 -120 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 22. THD+N vs. Input Level AKM AK5367A THD+N vs. Input Frequency AVDD=5V, DVDD=CVDD=3.3V, fs=96kHz, MCLK=256fs, -1dBFS input -70 T T T -75 -80 -85 -90 d B F S -95 -100 -105 -110 -115 -120 40 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 23. THD+N vs. Input Frequency <KM095000> 2008/06 - 20 - [AKD5367A-A] AKM AK5367A Linearity AVDD=5V, DVDD=CVDD=3.3V, fs=96kHz, MCLK=256fs, fin=1kHz +0 T -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 24. Linearity AKM AK5367A Frequency Response AVDD=5V, DVDD=CVDD=3.3V, fs=96kHz, MCLK=256fs, -1dBFS input -0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 d B F S -0.9 -1 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 -1.9 -2 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k 22.5k 25k 27.5k 30k 32.5k 35k 37.5k 40k Hz Figure 25. Frequency Response <KM095000> 2008/06 - 21 - [AKD5367A-A] AKM AK5367A Crosstalk (Red=LIN1, Blue=RIN1) AVDD=5V, DVDD=CVDD=3.3V, fs=96kHz, MCLK=256fs, -1dBFS input -50 -55 -60 -65 -70 -75 -80 d B -85 -90 -95 -100 -105 -110 -115 -120 40 50 100 200 500 1k 2k 5k 10k 20k 40k 20k 40k Hz Figure 26. Crosstalk AKM AK5367A FFT AVDD=5V, DVDD=CVDD=3.3V, fs=96kHz, MCLK=256fs, -1dBFS input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 40 50 100 200 500 1k 2k 5k 10k Hz Figure 27. FFT Plot <KM095000> 2008/06 - 22 - [AKD5367A-A] AKM AK5367A FFT AVDD=5V, DVDD=CVDD=3.3V, fs=96kHz, MCLK=256fs, -60dBFS input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 40 50 100 200 500 1k 2k 5k 10k 20k 40k 20k 40k Hz Figure 28. FFT Plot AKM AK5367A FFT AVDD=5V, DVDD=CVDD=3.3V, fs=96kHz, MCLK=256fs, No signal input +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 40 50 100 200 500 1k 2k 5k 10k Hz Figure 29. FFT Plot <KM095000> 2008/06 - 23 - [AKD5367A-A] REVISION HISTORY Date (YY/MM/DD) 08/06/09 Manual Revision KM095000 Board Revision 0 Reason Page Contents First Edition IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. <KM095000> 2008/06 - 24 - A B C D E E E CN2 C2 2.2u C1 0.1u + 1 1 U1 VCOM AVDD 30 LIN1 2 2 LIN1 VSS1 29 3 3 RIN1 DVDD +C12 10u 29 C9 0.1u R2 47k RIN1 5367_AVDD 30 C11 0.1u R1 47k + CN1 C10 10u 28 5367_DVDD 28 R3 47k LIN2 R19 51 4 4 D LIN2 LRCK 27 LRCK 27 R4 47k RIN2 5 LIN3 6 5 RIN2 MCLK 26 26 6 LIN3 BICK 25 25 5367_MCLK R5 47k AVDD DVDD T_45(ORANGE)T_45(RED) CVDD T_45(RED) D3V T_45(RED) DVDD CVDD BICK AK5367A 7 7 1 1 1 1 AVDD R17 51 R6 47k RIN3 RIN3 R16 51 SDTO 24 SDTO 24 R7 47k LIN4 VCC_3V R15 51 8 8 LIN4 SCL 23 SCL 23 R8 47k AGND DGND T_45(BLACK) T_45(BLACK) RIN4 D R18 51 R14 51 9 9 RIN4 SDA 22 SDA 22 R13 51 10 1 AGND 1 10 C DGND LOUT RISEL PDN 21 ROUT CP 20 5367_PDN 21 C +C3 10u R11(open) 11 11 R9 24k 12 12 ROPIN CN 19 13 LOPIN CVDD 18 20 C8 0.1u 19 JP1 13 GND AGND R10 24k R12(open) DGND ROUT 14 14 VSS2 17 LISEL CVEE +C7 10u 17 10u C4 + 15 15 LOUT 5367_CVDD 18 C6 0.1u C5 1u 16 16 B B 30pin_1 AVDD 30pin_2 VCC_3V ALL unmount JP4 VCC_3V D3V_SEL L1 (short) 1 2 C17 47u 5367_AVDD T1 LT1117-3.3 DVDD JP2 3 A C13 +47u + IN OUT GND 10u C14 1 + R20 (short) 2 5367_DVDD C15 0.1u + 47u C16 DVDD_SEL CVDD JP3 A L2 (short) 1 2 5367_CVDD Title CVDD_SEL Size A3 Document Number AKD5367A-A AK5367A Date: Tuesday, May 06, 2008 A B C D Sheet E 1 Rev 0 of 4 A B C D E 2 VCC_3V E 1 D1 HSU119 E 1 H 3 L R24 10k U4 C27 0.1u 2 SW1 5367_PDN 5367_PDN 1 2 3 4 5 6 7 1A 1Y 2A 2Y 3A 3Y GND VCC 6A 6Y 5A 5Y 4A 4Y 14 13 12 11 10 9 8 C20 0.1u VCC_3V 74HC14 2 VCC_3V 1 D R25 10k D2 HSU119 PORT1 3 2 VCC_3V U2 H 1 GND TOTX141 5367_MCLK 1 3 L C24 0.1u R23 0 D IN VCC C28 0.1u MCLK 2 SW2 DIT_PDN JP7 MCLK R40 51 JP6 BICK R39 51 SBICK 1 MCLK 2 BICK 3 SDTI1 TX 16 CDTO/SDTI2 15 VDD 14 VCC_3V R38 51 C SLRCK JP5 LRCK MCLK BICK LRCK SDTO BICK SDTO LRCK VSS 13 5 PDN TESTD3 12 6 CSN TESTD2 11 7 CCLK TESTD1 10 8 CDTI + 10u C26 C R37 51 VCC_3V PORT2 LRCK 4 0.1u C25 1 3 5 7 9 2 4 6 8 10 ROM TEST 9 AK4104 B B A A Title Size A3 Date: A B C D AKD5367A-A DIT AK4104 Document Number Wednesday, May 07, 2008 Sheet E 2 Rev 0 of 4 A B C D E E E J1 LIN1 J4 RIN2 J3 LIN2 ROUT C40 22u + + LIN2 R33 47k J5 LIN3 D J10 2 3 1 C41 22u + + MR-552LS LOUT R35 47k MR-552LS C36 short 2 3 1 RIN3 J9 MR-552LS R36 220 LOUT MR-552LS C37 short 2 3 1 LIN1 ROUT 2 3 1 C34 short 2 3 1 RIN2 MR-552LS J6 RIN3 R34 220 MR-552LS C35 short 2 3 1 + + RIN1 MR-552LS D C32 short 2 3 1 + C33 short 2 3 1 + J2 RIN1 LIN3 MR-552LS C C J8 RIN4 C39 short J7 LIN4 C38 short 2 3 1 RIN4 MR-552LS + + 2 3 1 LIN4 MR-552LS B B A A Title Size A3 Date: A B C D AKD5367A-A Document Number Rev 0 Input Output Wednesday, May 07, 2008 Sheet E 3 of 4 A B C D E X1 12.288MHz E E R31 JP8 XTE 1M U3 C30 5p C31 5p 1 2 3 4 5 6 7 1A 1Y 2A 2Y 3A 3Y GND VCC 6A 6Y 5A 5Y 4A 4Y 14 13 12 11 10 9 8 VCC_3V C19 0.1u 74HCU04 JP10 J11 MCLK_EXT U7 XTL EXT D R32 51 10 CLK 11 RST 16 VDD 8 VSS CLK VCC_3V JP9 EXT C18 0.1u Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1 JP11 SBICK 256fs D 512fs 256 JP12 SLRCK 512 U5 74HC4040 VCC_3V 1 C G1 VCC 20 19 G2 GND 10 2 A1 Y1 18 SBICK 3 A2 Y2 17 SLRCK 4 A3 Y3 16 MCLK 5 A4 Y4 15 6 A5 Y5 14 7 A6 Y6 13 8 A7 Y7 12 9 A8 Y8 11 C29 0.1u C VCC_3V VCC_3V R26 10k R27 470 R28 10k R29 470 SCL U6 1 3 5 9 11 13 1A 2A 3A 4A 5A 6A 14 C23 0.1u VCC 7 GND PORT3 B 1 3 5 7 9 2 4 6 8 10 R30 10K SCL SDA SDA(ACK) VCC_3V uP-I/F 2 4 6 8 10 12 1Y 2Y 3Y 4Y 5Y 6Y SDA B 74LVC07 74LVC541 A A Title Size AKD5367A-A Document Number A3 Date: A B C D Wednesday, May 07, 2008 Rev 0 LOGIC Sheet E 4 of 4 5 4 3 1 CN2 C2 2.2u C1 0.1u + 1 1 U1 VCOM AVDD 30 R1 47k 2 2 LIN1 VSS1 29 30 C11 0.1u 29 C9 0.1u R2 47k 3 D +C12 10u + CN1 D 2 C10 10u 3 RIN1 DVDD 28 28 4 LIN2 LRCK 27 27 5 RIN2 MCLK 26 26 6 LIN3 BICK 25 25 R3 47k 4 R4 47k 5 R5 47k 6 C C AK5367A R6 47k 7 RIN3 SDTO 24 24 8 LIN4 SCL 23 23 9 RIN4 SDA 22 22 10 RISEL PDN 21 21 11 ROUT CP 20 7 R7 47k 8 R8 47k 9 10 +C3 10u R11 11 B R9 24k (open) 12 13 ROPIN CN 19 13 LOPIN CVDD 18 R10 24k R12 14 14 + (open) LOUT VSS2 17 10u C4 15 15 A 12 LISEL CVEE 16 20 B C8 0.1u 19 18 C6 0.1u +C7 10u 17 C5 1u 16 A 30pin_1 30pin_2 Title AKD5367A-A-30VSOP-SUB A4 AK5367A Size Date: 5 4 3 2 Document Number Wednesday, May 07, 2008 Sheet 1 1 of 1 Rev 0