[AKD4344-A] AKD4344-A AK4344 Evaluation Board Rev.2 GENERAL DESCRIPTION The AKD4344-A is an evaluation board for the AK4344, 24bit and 96kHz DAC with DIT for portable and home audio systems. The AKD4344-A has the interface with AKM’s A/D converter evaluation boards and the interface with digital audio systems via optical connector. Therefore, it is easy to evaluate the AK4344. Ordering guide AKD4344-A --- AK4344 Evaluation Board FUNCTION • Compatible with 2 types of input data interface - Direct interface with AKM’s A/D converter evaluation boards via 10-pin header - On-board AK4112B as DIR, which accepts optical or BNC Inputs • Optical output for internal DIT • BNC connector for an external clock input • BNC connector for DAC output DGND VCC 74LVC541 Digital In OPT VDD AGND AK4344 AK4112B (DIR) BNC Digital Out OPT Analog Out LOUT MCLK Clock Divider Generator ROUT 10pin Header DSP Data Figure 1. AKD4344-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM087902> 2007/07 -1- [AKD4344-A] Operation sequence 1) Set up the power supply lines. [VDD] (Red) = 2.7 ∼ 3.6V (typ. 3.3V, for AK4344) [VCC] (Red) = 2.7 ∼ 3.6V (typ. 3.3V, for AK4112B, for 74LVC541 and for logic) [AGND] (Black) = 0V [DGND] (Black) = 0V Each supply line should be distributed from the power supply unit. 2) Set-up the evaluation modes, jumper pins and DIP switches (See the followings.) 3) Power on. When AK4112B is used, The AK4112B and AK4344 should be reset once by bringing SW2 and SW1 “L” upon power-up. When AK4112B is not used, keep SW2 to “L”, and the AK4344 should be reset once by bringing SW1 “L” upon power-up. Evaluation mode 1) D/A part evaluation using optical or S/PDIF input <Default> Use PORT1 (RX1: OPT) or J2 (RX1: BNC). The AK4112B (DIR) generates MCLK, BICK, LRCK and SDTI1 from the received data through Optical connector (TORX141) or BNC connector. This evaluation mode should be used for the evaluation using CD test disk. Nothing should be connected to PORT3 (DSP). The selection of OPT and BNC should be done by JP14 (RX1) JP4 MCLK DIR EXT JP5 BICK DIR JP6 SDTI1 JP7 JP12 LRCK EXT DIR EXT EXT 2) D/A part evaluation using 10-pin connector on the AKM’s A/D evaluation board Use PORT3 (DSP). It is able to evaluate the AK4344, connecting the 10-pin connector on the AKM’s A/D evaluation board and PORT3 (DSP) via 10-line flat cable. MCLK, BICK, LRCK and SDTI1 are sent from the A/D converter evaluation board to the AKD4344 through PORT3 (DSP) via 10-line flat cable. JP4 MCLK DIR EXT JP5 BICK DIR JP6 SDTI1 JP7 JP12 LRCK EXT DIR EXT EXT 3) D/A part evaluation using PORT3 (DSP), and supplying all interface signals from external equipments In case of using PORT3 (DSP), and supplying signals (MCLK, BICK, LRCK, SDTI1) that is needed for the AK4344 from external equipments, set up as following. JP4 MCLK DIR EXT JP5 BICK DIR JP6 SDTI1 JP7 JP12 LRCK EXT DIR EXT EXT In case of using PORT3 (DSP), and supplying SDTI2 from external equipments, setting of SDTI2 should be done by JP8 (SDTI2). <KM087902> 2007/07 -2- [AKD4344-A] Other Jumper pins set up (1) JP15 (VDD): VDD and VCC OPEN: Separated SHORT: Common. (The connector “VCC” can be open.) <Default> By opening the connector “VCC”, shorting JP15 (VDD) and supplying 3.3V to the connector “VDD”, the connector “VDD” can supply 3.3V to all circuits (2) JP16 (GND): Analog ground and Digital ground OPEN: Separated SHORT: Common. (The connector “DGND” can be open.) <Default> (3) JP10 (BCFS): Select the BICK of the AK4344 x1: BICK=128fs in case of MCLK=256fs/384fs/512fs/768fs. BICK=64fs in case of MCLK=192fs. x2: BICK=64fs in case of MCLK=128fs/256fs/384fs/512fs/768fs. <Default> BICK=32fs in case of MCLK=192fs. BICK=128fs in case of MCLK=1024fs/1536fs. x4: BICK=32fs in case of MCLK=128fs/256fs/384fs/512fs/768fs. BICK=64fs in case of MCLK=1024fs/1536fs. x8: BICK=32fs in case of MCLK=1024fs/1536fs. (4) JP11 (DIV), [JP9] (CLK), [JP13] (LRFS) When using J1 (EXT), these jumper pins should be set according to Table 1. (5) JP2 (CDTO / SDTI2): Select the signal of CDTO / SDTI2 pin CDTO: Select the CDTO<Default> SDTI2: Select the SDTI2 (6) JP8 (SDTI2): Select the input of SDTI2 pin PORT3: Input the signal from PORT3 GND: Input the “0” Data <Default> (When JP2 (CDTO / SDTI2): setting is CDTO, Set to GND) <KM087902> 2007/07 -3- [AKD4344-A] Example for External Clock setting Refer to the following setting when MCLK, BICK and LRCK are supplied to the AK4344 from J1 (EXT). Mode fs 8kHz Half 24kHz 8kHz 32kHz Normal 44.1kHz 48kHz 48kHz Double 96kHz MCLK JP11 (DIV) JP9 (CLK) 512fs = 4.096MHz x2 x2 768fs = 6.144MHz x3 x2 1024fs = 8.192MHz x2 x2 1536fs = 12.288MHz x3 x2 512fs = 12.288MHz x2 x2 768fs = 18.432MHz x3 x2 1024fs = 24.576MHz x2 x2 1536fs = 36.864MHz x3 x2 256fs = 2.048MHz x1 x2 384fs = 3.072MHz OPEN x3 512fs = 4.096MHz x2 x2 768fs = 6.144MHz x3 x2 256fs = 8.192MHz x1 x2 384fs = 12.288MHz OPEN x3 512fs = 16.384MHz x2 x2 768fs = 24.576MHz x3 x2 256fs = 11.2896MHz x1 x2 384fs = 16.9344MHz OPEN x3 512fs = 22.5792MHz x2 x2 768fs = 33.8688MHz x3 x2 256fs = 12.288MHz x1 x2 384fs = 18.432MHz OPEN x3 512fs = 24.576MHz x2 x2 768fs = 36.864MHz x3 x2 128fs = 6.144MHz OPEN x1 192fs = 9.216MHz OPEN x3 256fs = 12.288MHz x1 x2 384fs = 18.432MHz OPEN x3 128fs = 12.288MHz OPEN x1 192fs = 18.432MHz OPEN x3 256fs = 24.576MHz x1 x2 384fs = 36.864MHz OPEN x3 Table 1. Clock Setting <KM087902> JP13 (LRFS) x1 x1 x2 x2 x1 x1 x2 x2 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x3 x1 x1 x1 x3 x1 x1 Default 2007/07 -4- [AKD4344-A] DIP Switch set up [SW3]: Setting the audio data format of the AK4112B (ON=“H”, OFF=“L”) Mode 0 3 4 5 SW3-3 SW3-2 SW3-1 SDTI Format DIF2 DIF1 DIF0 L L L 16bit, LSB justified L H H 24bit, LSB justified H L L 24bit, MSB justified H L H 24bit, I2S Compatible Table 2. SW3: Audio Data Format of AK4112B Default Note. The AK4112B does not support 16bit, I2S Compatible. <KM087902> 2007/07 -5- [AKD4344-A] The function of the toggle SW [SW1] (AK4344-PDN): Resets the AK4344. Keep “H” during normal operation. The AK4344 should be reset once by bringing SW1 “L” upon power-up. [SW2] (AK4112B-PDN): Resets the AK4112B. Keep “H” during normal operation. The AK4112B should be reset once by bringing SW2 “L” upon power-up. Analog Output Circuit + The DAC of AK4344 outputs analog audio signals through J3 and J4. C13 22u R7 220 AK4344-LOUT R9 10k J3 BNC-R-PC 1 C100 1n C17 22u + R12 220 AK4344-ROUT R13 10k 2LOUT 3 4 5 J4 BNC-R-PC 1 C101 1n 2ROUT 3 4 5 Figure 2. LOUT/ROUT Output circuit * AKEMD assumes no responsibility for the trouble when using the above circuit examples. Serial control GND GND GND GND CCLK CSN 1 CDTI Red CDTO 2 NC PORT4 uP I/F GND The AKD4344-A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4 (uP-I/F) to PC by 10-line flat cable packed with the AKD4344-A. Take care of the direction of connector. There is a mark at pin#1. The pin layout of PORT4 as shown Figure 3. 10 9 Figure 3. PORT4 pin layout <KM087902> 2007/07 -6- [AKD4344-A] Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4344-A according to the Operating Sequence located on page 2. 2. Connect IBM-AT compatible PC with AKD4344-A by 10-line type flat cable (packed with AKD4344-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AKD4344-A Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “akd4344-a.exe” to set up the control program. 5. Please evaluate according to the following. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. Explanation of each buttons 1. [Port Reset]: 2. [Write default]: 3. [All Write]: 4. [Function1]: 5. [Function2]: 6. [Function3]: 7. [Function4]: 8. [Function5]: 9. [SAVE]: 10. [OPEN]: 11. [Write]: Set up the USB interface board (AKDUSBIF-A). Initialize the register of AK4344. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM087902> 2007/07 -7- [AKD4344-A] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK4344, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Input registers address in 2 figures of hexadecimal. Data Box: Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK4344, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate ATT Address Box: Start Data Box: End Data Box: Interval Box: Step Box: Input registers address in 2 figures of hexadecimal. Input starts data in 2 figures of hexadecimal. Input end data in 2 figures of hexadecimal. Data is written to AK4344 by this interval. Data changes by this step. Mode Select Box: *If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 *If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4344, click [OK] button. If not, click [Cancel] button. <KM087902> 2007/07 -8- [AKD4344-A] 4. [Save] and [Open] 4-1. [Save] Save the current register setting data. The extension of file name is “akr”. (Operation flow) (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is “akr”. 4-2. [Open] The register setting data saved by [Save] is written to AK4344. The file type is the same as [Save]. (Operation flow) (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button. <KM087902> 2007/07 -9- [AKD4344-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is “aks”. Figure 4. Window of [F3] <KM087902> 2007/07 - 10 - [AKD4344-A] 6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure opens. Figure 5. [F4] window <KM087902> 2007/07 - 11 - [AKD4344-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure. Figure 6. [F4] window(2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE]: The sequence file names can assign be saved. The file name is *.ak4. [OPEN]: The sequence file names assign that are saved in *.ak4 are loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change. <KM087902> 2007/07 - 12 - [AKD4344-A] 7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure opens. Figure 7. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). (2) Click [WRITE] button, then the register setting is executed. 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded. 7-3. Note (1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change. <KM087902> 2007/07 - 13 - [AKD4344-A] MEASUREMENT RESULTS [Measurement condition] • Measurement unit • MCLK • BICK • fs • BW • Bit • Power Supply • Interface • Temperature : Audio Precision, System Two Cascade : 512fs (fs=44.1KHz) / 256fs (fs=96KHz) : 64fs : 44.1kHz / 96kHz : 20Hz~20KHz (fs=44.1kHz) / 20Hz~40KHz (fs=96kHz) : 24bit : VDD = 3.3V : PSIA : Room [Measurement Results] Parameter DAC Analog Output Characteristics S/(N+D) (fs=44.1kHz, fin=1KHz, 0dBFS) (fs=96kHz, fin=1KHz, 0dBFS) D-Range (fs=44.1kHz, fin=1KHz, -60dBFS, A-weighted) (fs=96kHz, fin=1KHz, -60dBFS, A-weighted) Results Lch / Rch Unit -91.2/-91.2 -89.0/-89.1 dB dB 99.4/99.4 99.4/99.4 dB dB 99.6/99.5 99.4/99.4 115.0/115.2 dB dB dB S/N (fs=44.1kHz, no-input, A-weighted) (fs=96kHz, no-input, A-weighted) Interchannel Isolation (fin=1KHz, 0dBFS/ no-input) <KM087902> 2007/07 - 14 - [AKD4344-A] [DAC Plot: fs=44.1kHz] AKM THD+N vs. Input Level fs=44.1kHz, fin=1kHz 06/18/07 09:30:43 -70 -72 -74 -76 -78 -80 -82 d B r -84 -86 A -88 -90 -92 -94 -96 -98 -100 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 1. THD+N vs. Input Level (fin=1KHz) AKM THD+N vs. Input Freqency fs=44.1kHz, fin=0dBFs 06/18/07 09:28:48 -70 -72 -74 -76 -78 -80 -82 d B r -84 -86 A -88 -90 -92 -94 -96 -98 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 2. THD+N vs. Input Frequency (Input Level=0dBFS) <KM087902> 2007/07 - 15 - [AKD4344-A] [DAC Plot: fs=44.1kHz] AKM Linearity fs=44.1kHz, fin=1kHz 06/18/07 09:35:13 +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 3. Linearity (fin=1KHz) AKM Freqency Response fs=44.1kHz, fin=0dBFs 06/18/07 09:49:36 +1 +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 d B r A +0.1 +0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Hz Figure 4. Frequency Response (Input Level=0dBFS) <KM087902> 2007/07 - 16 - [AKD4344-A] [DAC Plot: fs=44.1kHz] AKM Crosstalk fs=44.1kHz 06/18/07 09:56:53 -70 -76 -82 -88 -94 d B -100 -106 -112 -118 -124 -130 10 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 5. Crosstalk (fin=1KHz, Input Level=0dBFS/no-input) AKM FFT fs=44.1kHz, fin=0dBFs,1kHz 06/18/07 10:07:31 +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 6. FFT Plot (fin=1KHz, Input Level=0dBFS) <KM087902> 2007/07 - 17 - [AKD4344-A] [DAC Plot: fs=44.1kHz] AKM FFT fs=44.1kHz, fin=-60dBFs,1kHz 06/18/07 10:08:53 +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 10 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 7. FFT Plot (fin=1KHz, Input Level=−60dBFS) AKM FFT Noise floor fs=44.1kHz 06/18/07 10:09:30 +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 8. FFT Plot (no-input) <KM087902> 2007/07 - 18 - [AKD4344-A] [DAC Plot: fs=96kHz] AKM FFT Out-of-band Noise fs=44.1kHz 06/18/07 10:32:35 +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 10 20 50 100 200 500 1k 2k 5k 10k 20k -40 -30 50k 100k Hz Figure 9. FFT Plot (out-of-band-noise) THD+N vs Input Level fs=96KHz, fin=1KHz -70 -72.5 -75 -77.5 -80 -82.5 -85 -87.5 -90 d B r -92.5 A -97.5 -95 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -20 -10 +0 dBFS Figure 10. THD+N vs. Input Level (fin=1KHz) <KM087902> 2007/07 - 19 - [AKD4344-A] [DAC Plot: fs=96kHz] THD+N vs Input Frequency fs=96KHz, Input Level=0dBFS -70 TT TT -72.5 -75 -77.5 -80 -82.5 -85 -87.5 -90 d B r -92.5 A -97.5 -95 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 10 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 11. THD+N vs. Input Frequency (Input Level=0dBFS) AKM Linearity fs=96kHz 06/18/07 10:46:53 +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 12. Linearity (fin=1KHz) <KM087902> 2007/07 - 20 - [AKD4344-A] [DAC Plot: fs=96kHz] AKM Frequency response fs=96kHz 06/18/07 10:49:42 +1 +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 d B r A +0.1 +0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k 22.5k 25k 27.5k 30k 32.5k 35k 37.5k 40k Hz Figure 13. Frequency Response (Input Level=0dBFS) AKM Crosstalk fs=96kHz 06/18/07 10:52:01 -70 -75 -80 -85 -90 -95 d B -100 -105 -110 -115 -120 -125 -130 10 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 14. Crosstalk (fin=1KHz, Input Level=0dBFS/no-input) <KM087902> 2007/07 - 21 - [AKD4344-A] [DAC Plot: fs=96kHz] AKM FFT fs=96kHz, fin=0dBFs,1kHz 06/18/07 10:24:00 +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 10 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 15. FFT Plot (fin=1KHz, Input Level= 0dBFS) AKM FFT fs=96kHz, fin=-60dBFs,1kHz 06/18/07 10:28:58 +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 16. FFT Plot (fin=1KHz, Input Level= −60dBFS) <KM087902> 2007/07 - 22 - [AKD4344-A] [DAC Plot: fs=96kHz] AKM FFT Noise floor fs=96kHz 06/18/07 10:29:37 +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 10 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 17. FFT Plot (no-input) AKM FFT Out-of-band Noise fs=96kHz 06/18/07 10:30:24 +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k Hz Figure 18. FFT Plot (out-of-band-noise) <KM087902> 2007/07 - 23 - [AKD4344-A] Revision History Date (yy/mm/dd) 07/03/15 07/04/17 Manual Revision KM087900 KM087901 Board Revision 0 1 07/07/02 KM087902 2 Reason Contents First Edition Circuit Change Change Circuit Change Add Change U1 (AK4344): 28pin SOP 16pin TSSOP Remove jumper pins: JP1 (TEST2), JP3 (TEST1). TEST2 is open. Connect TEST1 to GND. P3. Remove description: (7) JP1 (TEST2), (8) JP3 (TEST1). Capacitor between VCOM and VSS: C3: Change: 10uF 4.7uF Add capacitor C100: 1nF between J3 (LOUT) and GND. Add capacitor C101: 1nF between J4 (ROUT) and GND. Add measurement results IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. <KM087902> 2007/07 - 24 - A B C D E E E CN1 D U1 CN2 AK4344-MCLK 1 1 MCLK AK4344-BICK 2 2 BICK AK4344-SDTI1 3 3 SDTI1 TEST2 16 CDTO/SDTI2 15 VDD 14 CDTO JP2(3x1) CDTO/SDTI2 SDTI2 + C1 0.1u 4 4 LRCK VSS 13 C3 4.7u C AK4344-TX 15 AK4344-CDTO 14 AK4344-SDTI2 13 VDD D C2 10u + AK4344-LRCK 16 AK4344-PDN 5 5 PDN VCOM 12 12 AK4344-CSN 6 6 CSN LOUT 11 11 AK4344-LOUT AK4344-CCLK 7 7 CCLK ROUT 10 10 AK4344-ROUT AK4344-CDTI 8 8 CDTI TEST1 9 9 C AK4344 B B A A Title AKD4344-A A4 AK4344 Tuesday, June 12, 2007 Size Date: A B C D Document Number Sheet 1 E Rev 2 of 6 A B C D E U2 1 DVDD CM0/CDTO 28 2 DVSS CM1/CDTI 27 VCC 3 TVDD OCKS1/CCLK 26 VCC 4 V/TX OCKS0/CSN 25 5 XTI MCKO1 24 6 XTO MCKO2 23 7 PDN DAUX 22 8 R BICK 21 AK4112B-BICK 9 AVDD SDTO 20 AK4112B-SDTO 10 AVSS LRCK 19 AK4112B-LRCK AK4112B-RX1 11 RX1 ERF 18 AK4112B-ERF AK4112B-DIF0 12 RX2/DIF0 FS96 17 AK4112B-DIF1 13 RX3/DIF1 P/S 16 AK4112B-DIF2 14 RX4/DIF2 AUTO 15 VCC C4 10u C6 10u + C7 0.1u VCC C8 E C5 0.1u + E 5p D AK4112B-MCKO1 D X1 HC-49/U 11.2896MHz C9 5p AK4112B-PDN R1 18k VCC C C10 10u B + C C11 0.1u VCC B AK4112B A A Title Size A4 Date: A B C D AKD4344-A AK4112B Document Number Thursday, May 31, 2007 Rev 2 Sheet 2 E of 6 A B C D E E E VCC U3 1 G1 VCC 20 C12 0.1u EXT-MCLK D AK4112B-MCKO1 PORT3-MCLK JP4(3x1) MCLK PORT3-BICK JP5(3x1) BICK PORT3-SDTI1 JP6(2x1) SDTI1 PORT3-LRCK JP7 (3x1) LRCK EXT DIR EXT-BICK EXT AK4112B-BICK DIR AK4112B-SDTO EXT-LRCK AK4112B-LRCK C EXT DIR 74LVC541A-PDN PORT3-SDTI2 PORT3 GND JP8 (3x1) SDTI2 19 G2 GND 10 2 A1 Y1 18 3 A2 Y2 17 4 A3 Y3 16 5 A4 Y4 15 AK4344-LRCK 6 A5 Y5 14 AK4344-PDN 7 A6 Y6 13 AK4344-SDTI2 8 A7 Y7 12 9 A8 Y8 11 R2 51 D AK4344-MCLK R3 51 AK4344-BICK R4 51 AK4344-SDTI1 R5 51 C B B 74LVC541A A A Title Size A4 Date: A B C D Document Number AKD4344-A 74LVC541A Thursday, May 31, 2007 Sheet 3 E Rev 2 of 6 A B C D E EXT-MCLK VCC CLK DIV 5 Q 6 x1 1 x2 3 x3 5 2 4 6 16 Q 10 CLK 11 RST CLK VCC CLK VCC PR D 3 8 Q 7 10 2 9 1 14 13 12 11 15 U5 74HC4040 14 1 3 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1 x1 x2 x4 x8 1 2 3 4 5 6 7 8 EXT-BICK BCFS JP13 (3x2) x3 1 x1 3 x2 5 D 2 4 6 EXT-LRCK LRFS 2 U7A 74HC14 4 U7B 74HC14 C 5 8 ENP ENT CLK LOAD CLR QA QB QC QD RCO 7 VCC A B C D GND 3 4 5 6 VCC GND JP12 (2x1) VCC U6 74AC163 C 2 JP10 (4x2) 8 D EXT 2 4 6 VCC JP9 (3x2) 7 13 R6 51 x1 1 x2 3 x3 5 GND CL 11 1 9 Q JP11 (3x2) U4A 74AC74 7 1 D GND CL 2 3 4 5 12 16 EXT J1 BNC-R-PC U4B 74AC74 14 10 VCC 14 4 E VCC PR E 6 U7C 74HC14 9 8 U7D 74HC14 11 10 U7E 74HC14 B B 13 12 U7F 74HC14 A A Title Size A4 Date: A B C D AKD4344-A Document Number Rev External Master Clock Divider Thursday, May 31, 2007 Sheet 4 E of 2 6 A B C D E 2 VCC L1 47u K R8 10k A D1 HSU119 RX1(OPT) U8A 1 2 4 1 AK4344-LOUT VCC 3 GND OUT 2 1 C14 0.1u R10 R9 10k 470 74LVC541A-PDN OPT 74HC14 C100 1n JP14 (3x1) 1 RX1(BNC) 2 2 3 4 5 J2 BNC-R-PC BNC C16 1 0.1u R11 75 C17 22u J4 BNC-R-PC + R12 220 1 AK4344-ROUT VCC PORT2 TOTX141 K D R14 10k D2 HSU119 A E AK4112B-RX1 C15 0.1u TX(OPT) U8C 5 3 2 GND 1 AK4344-TX 9 74HC14 8 C101 1n 2ROUT 3 4 5 D VCC C18 0.1u U8D 6 H IN VCC R13 10k AK4112B-PDN 74HC14 1 L 3 2LOUT 3 4 5 RX1 SW1 ATE1D-2M3 AK4344-PDN 3 74HC14 H 3 L U8B J3 BNC-R-PC R7 220 + PORT1 TORX141 E C13 22u 1 VCC C19 0.1u 2 SW2 ATE1D-2M3 AK4112B-PDN C C SW3 DSS103 DIF0 DIF1 DIF2 1 2 3 VCC 4 5 6 PORT3-MCLK AK4112B-MODE R15 R16 R17 47K 47K 47K U9A 74HCT04 AK4112B-ERF PORT3-BICK PORT3-LRCK AK4112B-DIF0 AK4112B-DIF1 AK4112B-DIF2 1 R18 2 PORT3-SDTI2 PORT3 A1-10PA-2.54DSA 1 10 MCLK 2 9 BICK 3 8 LRCK 4 7 SDTI1 SDTI2 5 6 LED1 SML-210VT K 1k B PORT3-SDTI1 A VCC AK4112B-ERF B DSP U9B 74HCT04 VCC U8E 11 10 4 14 5 6 U9D 74HCT04 9 16 U8F 12 7 13 VCC VCC 74HC14 R19 10k R20 470 R22 10k R23 470 R25 10k R26 470 8 U9E 74HCT04 PORT4 A1-10PA-2.54DSA 10 9 CSN 8 7 CCLK 6 5 CDTI 4 3 CDTO 10 VCC 14 U9F 74HCT04 13 2 1 15 1A 1B 2A 2B 3A 3B 4A 4B A/B G U10 74HCT157 4 R21 100 2Y 7 R24 100 3Y 9 R27 100 4Y 12 R28 100 1Y AK4344-CSN AK4344-CCLK AK4344-CDTI AK4344-CDTO R29 100K A 8 11 A 2 3 5 6 11 10 14 13 VCC 74HC14 U9C 74HCT04 GND 3 1 12 R30 Title (short) 7 uP-I/F Size A3 Date: A B C D AKD4344-A Document Number Rev Input Output for Digital Analog Sheet of Tuesday, June 12, 2007 5 E 6 2 C D E VDDi AGND DGND 1 D L3 (short) 2 L2 (short) JP15 (2x1) For 74HC14 x 1, 74HCT04 x 1, 74AC74 x 1, 74HC4040 x 1, 74AC163 x 1, 74HC14 x 1 2 D VCCi E AGND DGND T_45(BLACK)T_45(BLACK) VCCi 1 VDDi VCC T_45(RED) 1 1 VDD T_45(RED) E 1 B 1 A R31 VCC C20 47u + VDD C21 47u + (short) C22 0.1u C23 0.1u C24 0.1u C25 0.1u C26 0.1u C27 0.1u C28 0.1u R32 C C VDD (short) JP16 AGND (2x1) DGND GND B B A A Title Size A4 Date: A B C D Document Number AKD4344-A Power Supply Thursday, May 31, 2007 Sheet 6 E Rev 2 of 6