DRV8821 www.ti.com.......................................................................................................................................... SLVS912B – JANUARY 2009 – REVISED SEPTEMBER 2009 DUAL STEPPER MOTOR CONTROLLER/DRIVER FEATURES 1 • Dual PWM microstepping motor driver – Built-In Microstepping Indexers – Up to 1.5-A Current Per Winding – Three-Bit Winding Current Control Allows up to Eight Current Levels – Low MOSFET On-Resistance – Selectable Slow or Mixed Decay Modes • 8-V to 27-V Operating Supply Voltage Range • Internal Charge Pump for Gate Drive • Built-in 3.3-V Reference 2 • • • Simple Step/Direction Interface Fully Protected Against Undervoltage, Overtemperature, and Overcurrent Thermally Enhanced Surface Mount Package APPLICATIONS • • • • • • Printers Scanners Office Automation Machines Gaming Machines Factory Automation Robotics DESCRIPTION/ORDERING INFORMATION The DRV8821 provides a dual microstepping-capable stepper motor controller/driver solution for printers, scanners, and other office automation equipment applications. Two independent stepper motor driver circuits include four H-bridge drivers and microstepping-capable indexer logic. Each of the motor driver blocks employ N-channel power MOSFETs configured as an H-bridge to drive the motor windings. A simple step/direction interface allows easy interfacing to controller circuits. Pins allow configuration of the motor in full-step, half-step, quarter-step, or eighth step modes, and the selection of slow or mixed decay modes. Internal shutdown functions are provided for over current protection, short circuit protection, under voltage lockout and overtemperature. The DRV8821 is packaged in a 48-pin HTSSOP package (Eco-friendly : RoHS & no Sb/Br). ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) PACKAGE (2) PowerPad™ (HTSSOP) - DCA ORDERABLE PART NUMBER Reel of 2000 DRV8821DCAR Tube of 40 DRV8821DCA TOP-SIDE MARKING DRV8821 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated DRV8821 SLVS912B – JANUARY 2009 – REVISED SEPTEMBER 2009.......................................................................................................................................... www.ti.com FUNCTIONAL BLOCK DIAGRAM CP1 Dig. VCC Charge Pump and Gate Drive Regulator 3.3V Regulator V3P3 0.47µF 6.3V CP2 0.01µF 35V +24 VCP VGD 0.1µF 16V +24 VCP VM ABVREF AOUT1 PWM H-bridge driver A Step Motor AOUT2 ABSTEP AISEN ABDIR ABENBLn +24 VM ABUSM0 ABUSM1 BOUT1 PWM H-bridge driver B ABDECAY BOUT2 ABRESETn BISEN Indexer Logic +24 CDSTEP VM CDDIR COUT1 PWM H-bridge driver C CDENBLn CDUSM0 COUT2 CDUSM1 CISEN Step Motor CDDECAY +24 CDRESETn VM DOUT1 PWM H-bridge driver D CDVREF DOUT2 DISEN OCP Thermal Shut down Oscillator UVLO RESET GND 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DRV8821 DRV8821 www.ti.com.......................................................................................................................................... SLVS912B – JANUARY 2009 – REVISED SEPTEMBER 2009 TERMINAL FUNCTIONS NAME NO. I/O (1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS POWER AND GROUND VM (4 pins) 1,2, 23, 24 - Motor supply voltage (multiple pins) Connect all VM pins together to motor supply voltage. Bypass to GND with several 0.1-µF, 35-V ceramic capacitors. V3P3 16 - 3.3 V regulator output Bypass to GND with TBD-µF, 6.3-V ceramic capacitor. GND 10-15, 34-39 - Power ground (multiple pins) Connect all PGND pins to GND and solder to copper heatsink areas. CP1 7 IO CP2 8 IO Charge pump flying capacitor Connect a 0.01-µF capacitor between CP1 and CP2 VCP 9 IO Charge pump storage capacitor Connect a 0.1-µF, 16 V ceramic capacitor to VM ABSTEP 45 I Motor AB step input Rising edge causes the indexer to move one step. ABDIR 43 I Motor AB direction input Level sets the direction of stepping. ABUSM0 44 I Motor AB microstep mode 0 ABUSM1 41 I Motor AB microstep mode 1 USM0 and USM1 set the step mode - full step, half step, quarter step, or eight microsteps/step. ABENBLn 42 I Motor AB enable input Logic high to disable motor A outputs, logic low to enable. ABRESETn 40 I Motor AB reset input Active-low reset input initializes the indexer logic and disables the H-bridge outputs for motor A. ABDECAY 6 I Motor AB decay mode Logic low for slow decay mode, high for mixed decay. ABVREF 17 I Motor AB current set reference voltage Sets current trip threshold. AOUT1 5 O Bridge A output 1 AOUT2 3 O Bridge A output 2 MOTOR AB Connect to first coil of bipolar stepper motor 1, or DC motor winding. AISEN 4 - Bridge A current sense Connect to current sense resistor for bridge A. BOUT1 48 O Bridge B output 1 BOUT2 46 O Bridge B output 2 Connect to second coil of bipolar stepper motor 1, or DC motor winding. BISEN 45 - Bridge B current sense Connect to current sense resistor for bridge B. CDSTEP 33 I Motor CD step input Rising edge causes the indexer to move one step. CDDIR 31 I Motor CD direction input Level sets the direction of stepping. CDUSM0 32 I Motor CD microstep mode 0 CDUSM1 29 I Motor CD microstep mode 1 USM0 and USM1 set the step mode - full step, half step, quarter step, or eight microsteps/step. CDENBLn 30 I Motor CD enable input Logic high to disable motor Boutputs, logic low to enable. CDRESETn 28 I Motor CD reset input Active-low reset input initializes the indexer logic and disables the H-bridge outputs for motor B. CDDECAY 19 I Motor CD decay mode Logic low for slow decay mode, high for mixed decay. CDREF 18 I Motor CD current set reference voltage Sets current trip threshold. COUT1 27 O Bridge C output 1 COUT2 25 O Bridge C output 2 CISEN 26 - Bridge C current sense Connect to current sense resistor for bridge C. DOUT1 22 O Bridge D output 1 DOUT2 20 O Bridge D output 2 Connect to second coil of bipolar stepper motor 2, or DC motor winding. DISEN 21 - Bridge D current sense Connect to current sense resistor for bridge D. MOTOR CD (1) Connect to first coil of bipolar stepper motor 2, or DC motor winding. Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input/output Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DRV8821 3 DRV8821 SLVS912B – JANUARY 2009 – REVISED SEPTEMBER 2009.......................................................................................................................................... www.ti.com DCA PACKAGE VM VM AOUT2 AISEN AOUT1 ABDECAY CP1 CP2 VCP PGND PGND Solder these PGND pins to copper PGND heatsink area PGND PGND V3P3 ABVREF CDVREF CDDECAY DOUT2 DISEN DOUT1 VM VM 1 48 2 3 47 46 4 45 5 6 44 43 7 8 42 41 9 40 10 11 39 38 12 13 37 36 14 15 35 34 16 17 18 19 20 33 32 31 30 29 21 22 23 24 28 27 26 25 BOUT1 BISEN BOUT2 ABSTEP ABUSM0 ABDIR ABENBLn ABUSM1 ABRESETn PGND PGND Solder these PGND pins to copper PGND heatsink area PGND PGND CDSTEP CDUSM0 CDDIR CDENBLn CDUSM1 CDRESETn COUT1 CISEN COUT2 ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) VM Power supply voltage range –0.3 to 32 V VI Logic input voltage range (3) –0.5 to 5.75 V IO(peak) Peak motor drive output current, t < 1 µs IO Motor drive output current (4) PD Continuous total power dissipation TJ Operating virtual junction temperature range TA Tstg (1) (2) (3) (4) Internally limited 1.5 A See Dissipation Ratings Table –40 to 150 °C Operating ambient temperature range –40 to 85 °C Storage temperature range –60 to 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Input pins may be driven in this voltage range regardless of presence or absence of VM. Power dissipation and thermal limits must be observed. DISSIPATION RATINGS RθJA DERATING FACTOR ABOVE TA = 25°C TA < 25°C TA = 70°C TA = 85°C Low-K (1) 75.7°C/W 13.2 mW/°C 1.65 W 1.06 W 0.86 W Low-K (2) 32°C/W 31.3 mW/°C 3.91 W 2.50 W 2.03 W 30.3°C/W 33 mW/°C 4.13 W 2.48 W 2.15 W 22.3°C/W 44.8 mW/°C 5.61 W 3.59 W 2.91 W BOARD High-K (3) High-K (4) (1) (2) (3) (4) 4 PACKAGE DCA The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with no backside copper. The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with 25-cm2 2-oz copper on back side. The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with no backside copper and solid 1-oz internal ground plane. The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with 25-cm2 1-oz copper on back side and solid 1-oz internal ground plane. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DRV8821 DRV8821 www.ti.com.......................................................................................................................................... SLVS912B – JANUARY 2009 – REVISED SEPTEMBER 2009 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VM Motor power supply voltage range IMOT Continuous motor drive output current (1) VREF VREF input voltage (1) NOM 8 MAX UNIT 27 V 1.5 A 4 V TYP MAX UNIT 5 8 mA 2.5 µA 8 V 1 1 Power dissipation and thermal limits must be observed. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN POWER SUPPLIES IVM VM operating supply current VM = 24 V, no loads IVMSD VM shutdown supply current VM = 24 V, ABENBLn = CDENBLn = 1 VUVLO VM undervoltage lockout voltage VM rising 6.5 VCP Charge pump voltage Relative to VM 12 VV3P3 VV3P3 output voltage 3.20 3.30 V 3.40 V 0.7 V LOGIC-LEVEL INPUTS VIL Input low voltage VIH Input high voltage VHYS Input hysteresis IIN Input current (internal pulldown current) 2 0.3 V 0.45 VIN = 3.3 V 0.6 V 100 µA OVERTEMPERATURE PROTECTION tTSD Thermal shutdown temperature Die temperature 150 °C MOTOR DRIVER Rds(on) Motor #1 FET on resistance (each individual FET) VM = 24 V, IO = 0.8 A, TJ = 25°C 0.25 VM = 24 V, IO = 0.8 A, TJ = 85°C 0.31 Rds(on) Motor #2 FET on resistance (each individual FET) VM = 24 V, IO = 0.8 A, TJ = 25°C 0.30 VM = 24 V, IO = 0.8 A, TJ = 85°C 0.38 IOFF Off-state leakage current fPWM Motor PWM frequency (1) tBLANK ITRIP blanking time (2) tF Output fall time 50 300 ns tR Output rise time 50 300 ns IOCP Overcurrent protect level 1.5 4.5 A tOCP Overcurrent protect trip time tMD Mixed decay percentage 45 50 0.37 0.45 µA 55 kHz µs µs 2.5 Measured from beginning of PWM cycle Ω ±12 3.75 3 Ω 75 % VREF INPUT/CURRENT CONTROL ACCURACY IREF xVREF input current ΔICHOP (1) (2) Chopping current accuracy xVREF = 3.3 V –3 3 µA xVREF = 2.5 V, derived from V3P3; 71% to 100% current –5 5 % xVREF = 2.5 V, derived from V3P3; 20% to 56% current –10 10 % Factory option 100 kHz. Factory options for 2.5 µs, 5 µs or 6.25 µs. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DRV8821 5 DRV8821 SLVS912B – JANUARY 2009 – REVISED SEPTEMBER 2009.......................................................................................................................................... www.ti.com TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT 1 fSTEP Step frequency 2 tWH(STEP) Pulse duration, xSTEP high 200 3 tWL(STEP) 4 tSU(STEP) 5 6 kHz 2.5 µs Pulse duration, xSTEP low 2.5 µs Setup time, command to xSTEP rising 200 ns tH(STEP) Hold time, command to xSTEP rising 200 ns tWAKE Wakeup time, SLEEPn inactive to xSTEP 1 ms 1 2 3 xSTEP xDIR, xUSMx 4 5 ABENBLn & CDENBLn 6 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DRV8821 DRV8821 www.ti.com.......................................................................................................................................... SLVS912B – JANUARY 2009 – REVISED SEPTEMBER 2009 FUNCTIONAL DESCRIPTION PWM Motor Drivers The DRV8821 contains four H-bridge motor drivers with current-control PWM circuitry. A block diagram showing drivers A and B of the motor control circuitry (as typically used to drive a bipolar stepper motor) is shown below. Drivers C and D are the same as A and B (though the Rds(on) of the output FETs is different). VM OC P VM VC P, VGD A OU T1 From Indexer Logic Predrive AEN B L Step Motor APH A SE A OU T2 A BD EC A Y PW M OC P A I[2:0] 3 + A I[2:0] A IS EN A =5 DAC 3 A BVR EF VM OC P VM V CP, VGD BOU T1 Predrive B EN BL B OU T2 BPH A SE PW M OC P B ISEN + B I[2:0] A =5 DAC 3 Figure 1. Block Diagram Note that there are multiple VM motor power supply pins. All VM pins must be connected together to the motor supply voltage. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DRV8821 7 DRV8821 SLVS912B – JANUARY 2009 – REVISED SEPTEMBER 2009.......................................................................................................................................... www.ti.com Current Regulation The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input from the xVREF pin. The full-scale (100%) chopping current is calculated as follows: 5 (1) Example: If a 0.22-Ω sense resistor is used and the VREFx pin is 3.3 V, the full-scale (100%) chopping current is 3.3 V/(5 * 0.22 Ω) = 1.875 A. The reference voltage is also scaled by an internal DAC that allows torque control for fractional stepping of a bipolar stepper motor, as described in the "microstepping indexer" section below. Decay Mode During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 2 as case 1. The current flow direction shown indicates positive current flow in the step table below. Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay. In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast-decay mode is shown in Figure 2 as case 2. In slow-decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown in Figure 2 as case 3. VM 1 Drive current 1 xOUT2 xOUT1 3 2 Fast decay (reverse) 3 Slow decay (brake) 2 Figure 2. Decay Mode 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DRV8821 DRV8821 www.ti.com.......................................................................................................................................... SLVS912B – JANUARY 2009 – REVISED SEPTEMBER 2009 The DRV8821 also supports a mixed decay mode. Mixed decay mode begins as fast decay, but after a period of time (75% of the PWM cycle) switches to slow decay mode for the remainder of the fixed PWM period. Mixed decay mode is only active if the current through the winding is decreasing (per the indexer step table); if the current is increasing, then slow decay is always used. Slow or mixed decay mode is selected by the state of the xDECAY pins - logic low selects slow decay, and logic high selects mixed decay operation. Blanking Time After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 µs. Note that the blanking time also sets the minimum on time of the PWM. Microstepping Indexer Built-in indexer logic in the DRV8821 allows a number of different stepping configurations. The xUSM1 and xUSM0 pins are used to configure the stepping format as shown in the table below: xUSM1 xUSM0 STEP MODE 0 0 Full step (2-phase excitation) 0 1 step (1-2 phase excitation) 1 0 1/4 step (W1-2 phase excitation) 1 1 Eight microsteps/steps The following table shows the relative current and step directions for different settings of xUSM1 and xUSM0. At each rising edge of the xSTEP input, the indexer travels to the next state in the table. The direction is shown with the DIR pin high; if the xDIR pin is low the sequence is reversed. Positive current is defined as xOUT1 = positive with respect to xOUT2. Note that the home state is 45 degrees. This state is entered at power-up or application of xRESETn. Motor AB and motor CD act independently, and their indexer logic functions identically. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DRV8821 9 DRV8821 SLVS912B – JANUARY 2009 – REVISED SEPTEMBER 2009.......................................................................................................................................... www.ti.com FULL STEP xUSM = 00 1/4 STEP xUSM = 10 1/8 STEP xUSM = 11 1 1 1 100 0 0 2 98 20 11.25 3 92 38 22.5 4 83 56 33.75 5 71 71 45 (home state) 6 56 83 56.25 7 38 92 67.5 8 20 98 78.75 9 0 100 90 10 –20 98 101.25 11 –38 92 112.5 12 –56 83 123.75 13 –71 71 135 14 –83 56 146.25 15 –92 38 157.5 16 –98 20 168.75 17 –100 0 180 18 –98 –20 191.25 19 –92 –38 202.5 20 –83 –56 213.75 21 –71 –71 225 22 –56 –83 236.25 23 –38 –92 247.5 24 –20 –98 258.75 25 0 –100 270 26 20 –98 281.25 27 38 –92 292.5 28 56 –83 303.75 29 71 –71 315 30 83 –56 326.25 31 92 –38 337.5 32 98 –20 348.75 2 1 2 3 4 3 5 6 2 4 7 8 5 9 10 3 6 11 12 7 13 14 4 AOUTx BOUTx CURRENT CURRENT (% FULL-SCALE) (% FULL-SCALE) STEP xUSM = 01 8 15 16 STEP ANGLE (DEGREES) xRESETn and xENBLn Operation The xRESETn pin, when driven active low, resets the step table to the home position. It also disables the H-bridge drivers. The xSTEP input is ignored while xRESETn is active. Note that there is a separate xRESETn pin for each motor; each acts only on one of the two motor controllers. The xENABLEn pin is used to control the output drivers. When xENBLn is low, the output H-bridges are enabled. When xENBLn is high, the H-bridges are disabled and the outputs are in a high-impedance state.. Note that there is a separate xENBLn pin for each motor; each acts only on one of the two motor drivers. Note that when xENBLn is high, the input pins and control logic, including the indexer (xSTEP and xDIR pins) are still functional. Driving both ABENBLn and CDENBLn high will put the device into a low power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped, and all internal clocks are stopped. In this state all inputs are ignored until one or both of the xENBLn pits return active low. 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DRV8821 DRV8821 www.ti.com.......................................................................................................................................... SLVS912B – JANUARY 2009 – REVISED SEPTEMBER 2009 Protection Circuits The DRV8821 is fully protected against undervoltage, overcurrent and overtemperature events. Overcurrent Protection (OCP) All of the drivers in DRV8821 are protected with an OCP (Over-Current Protection) circuit. The OCP circuit includes an analog current limit circuit, which acts by removing the gate drive form each output FET if the current through it exceeds a preset level. This circuit will limit the current to a level that is safe to prevent damage to the FET. A digital circuit monitors the analog current limit circuits. If any analog current limit condition exists for longer than a preset period, all drivers in the device will be disabled. The device is re-enabled upon the removal and re-application of power at the VM pins. Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all drivers in the device will be shut down. The device will remain disabled until the die temperature has fallen to a safe level. After the temperature has fallen, the device may be re-enabled upon the removal and re-application of power at the VM pin. Undervoltage Lockout (UVLO) If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled. Operation will resume when VM rises above the UVLO threshold. The indexer logic will be reset to its initial condition in the event of an undervoltage lockout. Shoot-Through Current Prevention The gate drive to each FET in the H-bridge is controlled to prevent any cross-conduction (shoot through current) during transitions. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DRV8821 11 DRV8821 SLVS912B – JANUARY 2009 – REVISED SEPTEMBER 2009.......................................................................................................................................... www.ti.com THERMAL INFORMATION Thermal Protection The DRV8821 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. Power Dissipation Power dissipation in the DRV8821 is dominated by the power dissipated in the output FET resistance, or RDS(ON). Average power dissipation when running a stepper motor can be roughly estimated by Equation 2. PTOT = 4 · RDS(ON) · (IOUT(RMS)) 2 (2) where PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are conducting winding current for each winding (one high-side and one low-side). Remember that the DRV8821 has two stepper motor drivers, so the power dissipation of each must be added together to determine the total device power dissipation. The maximum amount of power that can be dissipated in the DRV8821 is dependent on ambient temperature and heatsinking. The thermal dissipation ratings table in the datasheet can be used to estimate the temperature rise for typical PCB constructions. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. Heatsinking The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, refer to TI application report SLMA002, "PowerPAD™ Thermally Enhanced Package" and TI application brief SLMA004, "PowerPAD™ Made Easy", available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated. Figure 3 shows thermal resistance vs. copper plane area for both a single-sided PCB with 2-oz copper heatsink area, and a 4-layer PCB with 1-oz copper and a solid ground plane. Both PCBs are 76 mm x 114 mm, and 1.6 mm thick. It can be seen that the heatsink effectiveness increases rapidly to about 20 cm2, then levels off somewhat for larger areas. Six pins on the center of each side of the package are also connected to the device ground. A copper area can be used on the PCB that connects to the PowerPAD™ as well as to all the ground pins on each side of the device. This is especially useful for single-layer PCB designs. 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DRV8821 DRV8821 www.ti.com.......................................................................................................................................... SLVS912B – JANUARY 2009 – REVISED SEPTEMBER 2009 70 65 Thermal Resistance (RqJA) - °C/W 60 55 50 45 Low-K PCB (2 layer) 40 35 30 High-K PCB (4 layer with ground plane) 25 20 0 10 20 30 40 50 60 70 80 90 2 Backside Copper Area - cm Figure 3. Thermal Resistance vs. Copper Plane Area Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DRV8821 13 PACKAGE OPTION ADDENDUM www.ti.com 22-Sep-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DRV8821DCA ACTIVE HTSSOP DCA 48 DRV8821DCAR ACTIVE HTSSOP DCA 48 40 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Sep-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8821DCAR Package Package Pins Type Drawing SPQ HTSSOP 2000 DCA 48 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.8 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Sep-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8821DCAR HTSSOP DCA 48 2000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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