AZM AZ100LVEL16VTNA

AZ100LVEL16VT
PECL/ECL Oscillator Gain Stage &
Buffer with Selectable Enable
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FEATURES
DESCRIPTION
• Minimizes External
Components
• High Bandwidth for ≥1GHz
• Similar Operation as
AZ100LVEL16VR except in
Disabled Condition, QHG is
High
• -147 dBc/Hz Typical Noise
Floor
The AZ100LVEL16VT is a specialized oscillator gain stage with a high
gain output buffer including an enable function. The QHG/Q
¯ HG outputs have
voltage gain several times greater than the Q
¯ output. It provides a QHG/Q
¯ HG
enable that allows continuous oscillator operation via the Q
¯ outputs.
The AZ100LVEL16VT also provides a 4mA internal pull-down current
source for Q
¯ outputs. Internal input biasing further reduces the number of
needed external components.
BLOCK DIAGRAM
APPLICATIONS
•
Crystal or saw oscillators that
require minimal external
components.
PACKAGE AVAILABILITY
•
MLP8
o Green/RoHS Compliant/Pb-Free
Order Number
Package
Marking
AZ100LVEL16VTNA+1
MLP8
P9+ <Date Code>2
AZ100LVEL16VTNB+1
MLP8
P8+ <Date Code>2
1
Tape & Reel - Add 'R1' at end of PN for 7in (1k parts), 'R2' (2.5k) for 13in
2
See www.azmicrotek.com for date code format
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1630 S Stapley Dr, Suite 127
Mesa, AZ 85204 USA
May 2012, Rev 2.0
Arizona Microtek, Inc.
AZ100LVEL16VT
PECL/ECL Oscillator Gain Stage
& Buffer with Selectable Enable
PIN DESCRIPTION AND CONFIGURATION
Table 1 - Pin Description AZ100LVEL16VTNA+
Pin
Name
Type
Function
1
D
Input
Data Input
2
D
¯
Input
Inverting Data Input
3
VBB
Output
Reference Voltage
4
EN
¯¯
Input
Output Enable
5
Q
¯ HG
Output
High Gain Inverting PECL Output
6
QHG
Output
High Gain PECL Output
7
VCC
Power
Positive Supply
8
Q
¯
Output
Inverting PECL Output
9
VEE
Power
Negative Supply
D
1
8
Q
D
2
7
VCC
VBB
3
6
QHG
EN
4
5
QHG
VEE
Figure 1 - Pin Configuration for
AZ100LVEL16VTNA+
Table 2 - Pin Description AZ100LVEL16VTNB+
Pin
Name
Type
Function
1
D
Input
Data Input
2
VBB
Output
Reference Voltage
3
EN
Input
Output Enable
4
VEE
Power
Negative Supply
5
Q
¯ HG
Output
High Gain Inverting PECL Output
6
QHG
Output
High Gain PECL Output
7
VCC
Power
Positive Supply
8
Q
¯
Output
Inverting PECL Output
9
NC
-
N/A
D
1
VBB
2
EN
3
VEE
4
Leave Pad
open or
connect to
VEE
8
Q
7
VCC
6
QHG
5
QHG
Figure 2 - Pin Configuration for
AZ100LVEL16VTNB+
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZ100LVEL16VT
PECL/ECL Oscillator Gain Stage
& Buffer with Selectable Enable
ENGINEERING NOTES
The AZ100LVEL16VT is a specialized oscillator gain stage with a high gain output buffer including an enable. The
QHG/Q
¯ HG outputs have a voltage gain several times greater than the Q
¯ output. When the EN
¯¯ input is LOW, the Q
¯ and
QHG/Q
¯ HG outputs follow the data inputs. When EN
¯¯ is HIGH, the QHG output is forced high and the Q
¯ HG output is forced
low.
For the AZ100LVEL16VTNA, both D and D
¯ inputs are brought out and tied to the VBB pin through 470Ω internal bias
resistors. In the AZ100LVEL16VTNB, the D
¯ input is internally tied directly to the VBB pin and the D input is tied to the
VBB pin through a 470Ω internal bias resistor. Bypassing VBB to ground with a 0.01 µF capacitor is recommended.
D
EN
Q
Q
QHG
QHG
Figure 3 -Timing Diagram
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May 2012, Rev 2.0
PECL/ECL Oscillator Gain Stage
& Buffer with Selectable Enable
0.9
0
0.88
-5
0.86
-10
0.84
-15
0.82
-20
0.8
-25
0.78
-30
0.76
-35
0.74
-40
0.72
-45
0.7
Phase
AZ100LVEL16VT
S11 MAG
8mA
S11 MAG
4mA
S11 PHASE
8mA
Phase
Magnitude
Arizona Microtek, Inc.
S12 MAG
8mA
S12 MAG
4mA
S12 PHASE
8mA
-50
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
Figure 4 - S11
200
0.02
180
0.015
160
Magnitude
0.025
0.01
140
0.005
120
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
100
1400
Frequency (MHz)
Figure 5 - S12
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May 2012, Rev 2.0
PECL/ECL Oscillator Gain Stage
& Buffer with Selectable Enable
30
180
25
150
20
120
15
90
10
60
5
30
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
Phase
AZ100LVEL16VT
S21 MAG
8mA
S21 MAG
4mA
S21 PHASE
8mA
Phase
Magnitude
Arizona Microtek, Inc.
S22 MAG
8mA
S22 MAG
4mA
S22 PHASE
8mA
0
1400
Frequency (MHz)
Magnitude
Figure 6 – S21
0.8
200
0.75
190
0.7
180
0.65
170
0.6
160
0.55
150
0.5
140
0.45
130
0.4
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
120
1400
Frequency (MHz)
Figure 7 – S22
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZ100LVEL16VT
PECL/ECL Oscillator Gain Stage
& Buffer with Selectable Enable
PERFORMANCE DATA
Table 3 – Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
Characteristic
Condition
Rating
Unit
VCC
PECL Power Supply
VEE = 0V
0 to + 6.0
V
VI
PECL Input Voltage
VEE = 0V
0 to + 6.0
V
VD/D¯
D/D
¯ Input Voltage
Referenced to VBB
±0.75
V
Continuous Q/Q
¯
25
Surge Q/Q
¯
50
Continuous QHG/Q
¯ HG
50
Surge QHG/Q
¯ HG
100
IOUT
Output Current
mA
TA
Operating Temperature Range
-
-40 to +85
°C
TSTG
Storage Temperature Range
-
-65 to +150
°C
ESDHBM
Human Body Model Electro Static Discharge
-
2500
V
ESDMM
Machine Model Electro Static Discharge
-
200
V
ESDCDM
Charged Device Model Electro Static Discharge
-
2000
V
Table 4 - 100K ECL DC Characteristics
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)
-40°C
Symbol
Characteristic
VOH
VOL
Output LOW Voltage
VBB
1.
0°C
25°C
85°C
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Output HIGH Voltage1
-1045
-835
-1025
-835
-1025
-835
-1025
-835
mV
1
-1925
-1555
-1900
-1620
-1900
-1620
-1900
-1620
mV
Reference Voltage
-1390
-1250
-1390
-1250
-1390
-1250
-1390
-1250
mV
VIH
Input HIGH Voltage D/D
¯ , EN
¯¯
-1165
-740
-1165
-740
-1165
-740
-1165
-740
mV
VIL
Input LOW Voltage D/D
¯ , EN
¯¯
-1900
-1475
-1900
-1475
-1900
-1475
-1900
-1475
mV
IIH
Input HIGH Current EN
¯¯
150
µA
IIL
Input LOW Current EN
¯¯
IEE
1
Power Supply Current
150
150
0.5
0.5
48
150
0.5
48
0.5
48
µA
54
mA
Specified with QHG/Q
¯ HG terminated through 50Ω resistors to VCC - 2V.
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZ100LVEL16VT
PECL/ECL Oscillator Gain Stage
& Buffer with Selectable Enable
Table 5 - 100K LVPECL DC Characteristics
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
-40°C
Symbol
Characteristic
VOH
VOL
Output LOW Voltage
VBB
Reference Voltage1
VIH
1.
2.
0°C
25°C
85°C
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Output HIGH Voltage1,2
2255
2465
2275
2465
2275
2465
2275
2465
mV
1,2
1375
1745
1400
1680
1400
1680
1400
1680
mV
-1390
-1250
-1390
-1250
-1390
-1250
-1390
-1250
mV
1
2135
2560
2135
2560
2135
2560
2135
2560
mV
1
1400
1825
1400
1825
1400
1825
1400
1825
mV
150
µA
Input HIGH Voltage D/D
¯ , EN
¯¯
VIL
Input LOW Voltage D/D
¯ , EN
¯¯
IIH
Input HIGH Current EN
¯¯
IIL
Input LOW Current EN
¯¯
IEE
2
150
150
0.5
0.5
Power Supply Current
150
0.5
48
0.5
48
µA
48
54
mA
For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.
¯ HG terminated through 50Ω resistors to VCC - 2V.
Specified with QHG/Q
Table 6 - 100K PECL DC Characteristics
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
-40°C
Symbol
Characteristic
VOH
VOL
Output LOW Voltage
VBB
1
1.
2.
0°C
25°C
85°C
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Output HIGH Voltage1,2
3955
4165
3975
4165
3975
4165
3975
4165
mV
1,2
3075
3445
3100
3380
3100
3380
3100
3380
mV
Reference Voltage
-1390
-1250
-1390
-1250
-1390
-1250
-1390
-1250
mV
VIH
Input HIGH Voltage D/D
¯ , EN
¯¯
1
3835
4260
3835
4260
3835
4260
3835
4260
mV
VIL
Input LOW Voltage D/D
¯ , EN
¯¯ 1
3100
3525
3100
3525
3100
3525
3100
3525
mV
IIH
Input HIGH Current EN
¯¯
150
µA
IIL
Input LOW Current EN
¯¯
IEE
2
Power Supply Current
150
150
0.5
0.5
48
150
0.5
48
0.5
48
µA
54
mA
For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
¯ HG terminated through 50Ω resistors to VCC - 2V.
Specified with QHG/Q
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZ100LVEL16VT
PECL/ECL Oscillator Gain Stage
& Buffer with Selectable Enable
Table 7 - AC Characteristics
AC Characteristics (VEE = -3.0V to -5.5V; VCC=GND or VEE=GND; VCC = +3.0V to +5.5V)
Symbol
-40°C
Characteristic
Min
Typ
0°C
Max
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
Propagation Delay
tPLH/tPHL
D to Q/Q
¯1
2
D to QHG/Q
¯ HG
tSKEW
3
Duty Cycle Skew
5
350
350
350
350
ps
450
450
450
450
ps
20
ps
20
5
20
5
20
5
4
Input Swing
Vpp (AC)
tr/tf
1.
2.
3.
4.
Differential
80
1000
80
1000
80
1000
80
1000
mV
Single Ended
150
2000
150
2000
150
2000
150
2000
mV
Output Rise/Fall1,2
(20%-80%)
100
240
100
240
100
240
100
240
ps
Q
¯ output specified with 50Ω termination to VCC - 2V.
QHG/Q
¯ HG terminated through 50Ω resistors to VCC - 2V.
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
The peak-to-peak input swing is the range for which AC parameters are guaranteed. D and D
¯ must remain within the range of ±
¯ outputs and a voltage gain of ≈ 100 to the QHG/Q
¯ HG
750 mV with respect to VBB. The device has a voltage gain of ≈ 20 to the Q
outputs.
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZ100LVEL16VT
PECL/ECL Oscillator Gain Stage
& Buffer with Selectable Enable
PACKAGE DIAGRAM
MLP8
Green/RoHS compliant/Pb-Free
MSL=1
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice.
Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for
any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of
any product or circuit and specifically disclaims any and all liability, including without limitation special,
consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of
others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc.
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona
Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
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May 2012, Rev 2.0