AZ100LVEL16VV - Arizona Microtek

AZ100LVEL16VV
Dual Frequency PECL/ECL Oscillator
Gain Stage & Buffer with Enable
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FEATURES
DESCRIPTION
• Minimizes External
Components
• High Bandwidth for ≥1GHz
• Similar Operation as
AZ100LVEL16VR except
with selectable data input
pairs
• -147 dBc/Hz Typical Noise
Floor
The AZ100LVEL16VV is a specialized oscillator gain stage with two
selectable data input pairs and a high gain output buffer including an
enable. Selectable data input pairs permit switching between two different
oscillator frequencies. The QHG/Q
¯ HG outputs have a voltage gain several
times greater than the Q/Q
¯ outputs. An enable allows continuous oscillator
operation by only controlling the QHG /Q
¯ HG outputs.
The AZ100LVEL16VV also provides a reference voltage (VBB) with
internal biasing resistors to each input to minimize external components.
BLOCK DIAGRAM
APPLICATIONS
•
•
4mA EA.
Q
Q
D0
EN
D0
QHG
D1
QHG
PACKAGE AVAILABILITY
•
D1
Dual frequency oscillators
Crystal or saw oscillators that
require minimal external
components.
MLP16
o Green/RoHS Compliant/Pb-Free
470 Ω
VBB
VEE
SEL
Order Number
Package
Marking
AZ100LVEL16VVL+1
MLP16
AZM+16K <Date Code>2
1
Tape & Reel - Add 'R1' at end of PN for 7in (1k parts), 'R2' (2.5k) for 13in
2
See www.azmicrotek.com for date code format
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1630 S Stapley Dr, Suite 127
Mesa, AZ 85204 USA
May 2012, Rev 2.0
Arizona Microtek, Inc.
AZ100LVEL16VV
Dual Frequency PECL/ECL Oscillator
Gain Stage & Buffer with Enable
PIN DESCRIPTION AND CONFIGURATION
Table 1 - Pin Description AZ100LVEL16VTNA+
Pin
Name
Type
Function
1
D0
Input
Data Input
2
D0
¯¯
Input
Inverting Data Input
3
D1
Input
Data Input
4
D1
¯¯
Input
Inverting Data Input
5
VBB
Output
Reference Voltage
6
NC
-
N/A
7
VEE
Power
Negative Supply
8
NC
-
N/A
9
EN
Input
Output Enable
10
Q
¯ HG
Output
High Gain Inverting PECL Output
11
QHG
Output
High Gain PECL Output
12
SEL
Input
Data Input Select
13
VCC
Power
Positive Supply
14
NC
-
N/A
15
Q
Output
PECL Output
16
Q
¯
Output
Inverting PECL Output
D0
1
D0
2
D1
3
D1
4
Q
Q
NC
VCC
16
15
14
13
12 SEL
Leave Pad
Open or
Connect to
VEE
11 QHG
10 QHG
9
5
6
7
8
VBB
NC
VEE
NC
EN
Figure 1 - Pin Configuration
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZ100LVEL16VV
Dual Frequency PECL/ECL Oscillator
Gain Stage & Buffer with Enable
ENGINEERING NOTES
The AZ100LVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain output
buffer including an enable. The QHG/Q
¯ HG outputs have a voltage gain several times greater than the Q/Q
¯ outputs.
The AZ100LVEL16VV provides two selectable data input pairs that permit switching between two different oscillator
frequencies. When the select pin (SEL) is LOW or open (NC) data from the D0/D0
¯¯ is selected. When the SEL pin is
HIGH data from the D1/D1
¯¯ is selected. Allowing continuous oscillator operation, the (EN) enable works with either data
input pair. When EN is HIGH or open (NC), input data is passed to both sets of outputs. When EN is LOW, the QHG/Q
¯ HG
outputs will be forced LOW/HIGH respectively, while input data will continue to be passed to the Q/Q
¯ outputs. The EN
and SEL inputs can be driven with an ECL/PECL signal or a full supply swing CMOS type logic signal.
The AZ100LVEL16VV also provides a VBB with a 1.5mA sink/source current. Each data input is separately connected to
VBB with a 470Ω internal bias resistor. Bypassing VBB to ground with a 0.01 µF capacitor is recommended.
Each Q/Q
¯ output has a 4 mA on-chip pull-down current source. External resistors may also be used to increase pull-down
current of the Q/Q
¯ to a maximum of 25mA each (includes a 4 mA on-chip current source).
Table 2 - Truth Table
EN
CS-SEL
Q
Q
¯
QHG
Q
¯ HG
High/Open
High/Open
Low
Low
Low/Open
High
Low/Open
High
D0/D0
¯¯
D1/D1
¯¯
D0/D0
¯¯
D1/D1
¯¯
D0/D0
¯¯
D1/D1
¯¯
D0/D0
¯¯
D1/D1
¯¯
D0/D0
¯¯
D1/D1
¯¯
Low
Low
D0/D0
¯¯
D1/D1
¯¯
High
High
D0
D1
EN
SEL
Q
Q
QHG
QHG
Figure 2 - Timing Diagram
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZ100LVEL16VV
Dual Frequency PECL/ECL Oscillator
Gain Stage & Buffer with Enable
0.00
0.95
-5.00
0.9
-10.00
0.85
-15.00
0.8
-20.00
0.75
-25.00
0.7
Phase
Magnitude
1
S11 MAG
S11 PHASE
-30.00
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
0.02
250.00
0.0175
225.00
0.015
200.00
0.0125
175.00
0.01
150.00
0.0075
125.00
0.005
100.00
0.0025
75.00
Phase
Magnitude
Figure 3 - S11
S12 MAG
S12 PHASE
50.00
0
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
Figure 4 - S12
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May 2012, Rev 2.0
AZ100LVEL16VV
Dual Frequency PECL/ECL Oscillator
Gain Stage & Buffer with Enable
30
200.00
25
150.00
20
100.00
15
50.00
10
Phase
Magnitude
Arizona Microtek, Inc.
S21 MAG
S21 PHASE
0.00
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
0.8
30.00
0.7
25.00
0.6
20.00
0.5
15.00
0.4
10.00
0.3
5.00
0.2
Phase
Magnitude
Figure 5 – S21
S22 MAG
S22 PHASE
0.00
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
Figure 6 – S22
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZ100LVEL16VV
Dual Frequency PECL/ECL Oscillator
Gain Stage & Buffer with Enable
PERFORMANCE DATA
Table 3 – Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
Characteristic
Condition
Rating
Unit
VCC
PECL Power Supply
VEE = 0V
0 to + 6.0
V
VD_PECL
PECL D Input Voltage
Referenced to VBB
V
VEN_PECL
PECL D Input Voltage
VEE = 0V
±0.75
0 to + 6.0
VEE
ECL Power Supply
VCC = 0V
-6.0 to 0
V
VD_ECL
ECL D Input Voltage
Referenced to VBB
V
VEN_ECL
ECL D Input Voltage
VCC = 0V
±0.75
-6.0 to 0
Continuous Q
25
Surge Q
50
Continuous QHG
50
Surge QHG
100
IOUT
Output Current
V
V
mA
TA
Operating Temperature Range
-
-40 to +85
°C
TSTG
Storage Temperature Range
-
-65 to +150
°C
ESDHBM
Human Body Model Electro Static Discharge
-
2500
V
ESDMM
Machine Model Electro Static Discharge
-
200
V
ESDCDM
Charged Device Model Electro Static Discharge
-
2000
V
Table 4 - ECL DC Characteristics
ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)
Symbol
Characteristic
VOH
VOL
-40°C
0°C
25°C
85°C
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Output HIGH Voltage1
-1045
-835
-1025
-835
-1025
-835
-1025
-835
mV
1
-1925
-1555
-1900
-1620
-1900
-1620
-1900
-1620
mV
Input HIGH Voltage D
-1165
-740
-1165
-740
-1165
-740
-1165
-740
mV
Input HIGH Voltage EN,SEL
-1165
VCC
-1165
VCC
-1165
VCC
-1165
VCC
Input LOW Voltage D
-1900
-1475
-1900
-1475
-1900
-1475
-1900
-1475
Input LOW Voltage EN,SEL
VEE
-1475
VEE
-1475
VEE
-1475
VEE
-1475
VBB
Reference Voltage
-1390
-1250
-1390
-1250
-1390
-1250
-1390
-1250
mV
IIH
Input HIGH Current EN,SEL
150
µA
IIL
Input LOW Current EN,SEL
Output LOW Voltage
VIH
VIL
1
IEE
Power Supply Current
1
150
-100
150
-100
47
150
-100
47
-100
47
mV
µA
51
mA
Specified with each output terminated through 50Ω resistors to VCC - 2V.
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZ100LVEL16VV
Dual Frequency PECL/ECL Oscillator
Gain Stage & Buffer with Enable
Table 5 - LVPECL DC Characteristics
LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
Symbol
Characteristic
VOH
VOL
-40°C
VIL
85°C
Unit
Max
Min
Max
Min
Max
Min
Max
Output HIGH Voltage1,2
2255
2465
2275
2465
2275
2465
2275
2465
mV
1,2
1375
1745
1400
1680
1400
1680
1400
1680
mV
Input HIGH Voltage D
2135
2560
2135
2560
2135
2560
2135
2560
mV
Input HIGH Voltage EN,SEL
2135
VCC
2135
VCC
2135
VCC
2135
VCC
Input LOW Voltage D
1050
1825
1400
1825
1400
1825
1400
1825
Input LOW Voltage EN,SEL
VEE
1825
VEE
1825
VEE
1825
VEE
1825
1910
2050
1910
2050
1910
2050
1910
2050
mV
150
µA
1
VBB
Reference Voltage
IIH
Input HIGH Current EN
IIL
3
Input LOW Current EN
150
-400
150
-400
2
IEE
25°C
Min
Output LOW Voltage
VIH
0°C
Power Supply Current
150
-400
47
-400
47
1
Voltage levels vary 1:1 with VCC
2
Specified with each output terminated through 50Ω resistors to VCC - 2V.
3
Specified with EN and SEL forced to VEE
mV
µA
47
51
mA
Table 6 - PECL DC Characteristics
PECL DC Characteristics (VEE = GND, VCC = +5.0V)
Symbol
Characteristic
VOH
-40°C
0°C
25°C
85°C
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Output HIGH Voltage1,2
3955
4165
3975
4165
3975
4165
3975
4165
mV
VOL
Output LOW Voltage
1,2
3075
3445
3100
3380
3100
3380
3100
3380
mV
VIH
Input HIGH Voltage D
3835
4260
3835
4260
3835
4260
3835
4260
mV
Input HIGH Voltage EN,SEL
3835
VCC
3835
VCC
3835
VCC
3835
VCC
Input LOW Voltage D
3100
3525
3100
3525
3100
3525
3100
3525
mV
Input LOW Voltage EN,SEL
VEE
3750
3610
3750
3610
3750
3610
3750
mV
150
µA
VIL
1
VBB
Reference Voltage
IIH
Input HIGH Current EN
3610
IIL
Input LOW Current EN
IEE
2
150
-1000
Power Supply Current
150
-1000
47
-1000
47
1
Voltage levels vary 1:1 with VCC
2
Specified with each output terminated through 50Ω resistors to VCC - 2V.
3
Specified with EN and SEL forced to VEE
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150
-1000
47
µA
51
mA
7
May 2012, Rev 2.0
Arizona Microtek, Inc.
AZ100LVEL16VV
Dual Frequency PECL/ECL Oscillator
Gain Stage & Buffer with Enable
Table 7 - AC Characteristics
AC Characteristics (VEE = -3.0V to -5.5V; VCC=GND or VEE=GND; VCC = +3.0V to +5.5V)
Symbol
Characteristic
-40°C
Min
Typ
0°C
Max
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
Propagation
Delay
tPLH/tPHL
D to Q/Qb
400
400
400
400
ps
550
550
550
550
ps
tSKEW
20
ps
Vpp (AC)
D to QHG/QbHG
Duty Cycle
Skew1
Input Swing2
tr/tf
Output Rise/Fall
(20% - 80%)
1
5
20
5
20
5
20
5
80
1000
80
1000
80
1000
80
1000
mV
100
260
100
260
100
260
100
260
ps
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
2
VPP is the peak-to-peak differential input swing for which AC parameters are guaranteed. The device has a voltage gain of
≈20 to Q/ outputs and a voltage gain of ≈100 to QHG/HG outputs.
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZ100LVEL16VV
Dual Frequency PECL/ECL Oscillator
Gain Stage & Buffer with Enable
PACKAGE DIAGRAM
MLP16
Green/RoHS compliant/Pb-Free
MSL=1
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice.
Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for
any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of
any product or circuit and specifically disclaims any and all liability, including without limitation special,
consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of
others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc.
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona
Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
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May 2012, Rev 2.0