Ultra Low Power/High Speed CMOS SRAM 1M X 16 bit BH616UV1611 Pb-Free and Green package materials are compliant to RoHS FEATURES DESCRIPTION y Wide VCC low operation voltage : 1.65V ~ 3.6V The BH616UV1611 is a high performance, ultra low power CMOS y Ultra low power consumption : Static Random Access Memory organized as 1,048,576 by 16 bits VCC = 3.6V Operation current : 12mA (Max.)at 55ns and operates in a wide range of 1.65V to 3.6V supply voltage. 2mA (Max.) at 1MHz Advanced CMOS technology and circuit techniques provide both O high speed and low power features with maximum standby current of Data retention current : 15uA(Max.) at 85 C 39uA at 3.6V/85 C and maximum access time of 55/70ns at Standby current : 30uA (Max.) at 3.6V/85 C VCC = 1.2V O O y High speed access time : -55/-70 3.0V/1.8V. 55ns (Max.) at VCC=3.0V Easy memory expansion is provided by an active LOW chip enable 70ns (Max.) at VCC=1.8V (CE1), an active HIGH chip enable (CE2) and active LOW output y Automatic power down when chip is deselected enable (OE) and three-state output drivers. y Easy expansion with CE1, CE2 and OE options The BH616UV1611 has an automatic power down feature, reducing y I/O Configuration x8/x16 selectable by LB and UB pin. the power consumption significantly when chip is deselected. y Three state outputs and TTL compatible The BH616UV1611 is made with two chips of 8Mbit SRAM by y Fully static operation, no clock, no refresh stacked multi-chip-package. y Data retention supply voltage as low as 1.0V The BH616UV1611 is available in 48-ball BGA package. POWER CONSUMPTION POWER DISSIPATION PRODUCT FAMILY OPERATING TEMPERATURE Industrial O O -40 C to +85 C BH616UV1611AI STANDBY Operating (ICCSB1, Max) VCC=3.6V VCC=1.8V 30uA 25uA 1MHz fMax. 2mA 6mA 12mA A LB 2 OE 3 A0 1MHz VCC=1.8V 10MHz fMax. 1.5mA 5mA 8mA BGA-48-0608 BLOCK DIAGRAM PIN CONFIGURATIONS 1 PKG TYPE (ICC, Max) VCC=3.6V 10MHz 4 A1 5 A2 6 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 CE2 B DQ8 UB A3 A4 CE1 DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSS DQ11 A17 A7 DQ3 VCC Address 1024 10 Input Row Buffer Decoder Memory Array 1024 x 16384 16384 E VCC DQ12 NC A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE DQ7 H A18 A8 A9 A10 A11 DQ0 . . . . . . . . . . . . 16 16 Data Output Buffer NC Write Driver Sense Amp 16 1024 Column Decoder DQ15 CE2, CE1 WE OE UB LB 16 Data Input Buffer Column I/O 10 Control Address Input Buffer A19 A18 A17 A15 A14 A13 A16 A2 A1 A0 VCC VSS 48-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice. Detailed product characteristic test report is available upon request and being accepted. R0201-BH616UV1611 1 Revision 1.1 Oct. 2008 BH616UV1611 PIN DESCRIPTIONS Name Function A0-A19 Address Input These 20 address inputs select one of the 1,048,576 x 16 bit in the RAM CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. DQ0-DQ15 Data Input/Output Ports VCC 16 bi-directional ports are used to read data from or write data into the RAM. VSS Ground Power Supply TRUTH TABLE MODE Chip De-selected (Power Down) Output Disabled Read Write CE1 CE2 WE OE LB UB H X X X X X High Z High Z ICCSB, ICCSB1 X L X X X X High Z High Z ICCSB, ICCSB1 X X X X H H High Z High Z ICCSB, ICCSB1 L H H H L X High Z High Z ICC L H H H X L High Z High Z ICC L L DOUT DOUT ICC H L High Z DOUT ICC L H DOUT High Z ICC L L DIN DIN ICC H L X DIN ICC L H DIN X ICC L L H H H L L X DQ0~DQ7 DQ8~DQ15 VCC CURRENT NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state) R0201-BH616UV1611 2 Revision 1.1 Oct. 2008 BH616UV1611 ABSOLUTE MAXIMUM RATINGS (1) SYMBOL VTERM TBIAS TSTG PARAMETER OPERATING RANGE RATING Terminal Voltage with Respect to GND Temperature Under Bias (2) -0.5 Storage Temperature UNITS RANG AMBIENT TEMPERATURE V Industrial -40 C to + 85 C to 4.6V -40 to +125 O C -60 to +150 O C PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA O VCC O 1.65V ~ 3.6V CAPACITANCE (1) (TA = 25OC, f = 1.0MHz) SYMBOL PAMAMETER CONDITIONS MAX. UNITS Input Capacitance Input/Output Capacitance CIN 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. –2.0V in case of AC pulse width less than 30 ns CIO VIN = 0V 10 pF VI/O = 0V 15 pF 1. This parameter is guaranteed and not 100% tested. DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC) PARAMETER NAME PARAMETER VCC Power Supply VIL Input Low Voltage VIH Input High Voltage IIL Input Leakage Current ILO Output Leakage Current TEST CONDITIONS VCC=1.8V VCC=3.6V MIN. TYP.(1) MAX. UNITS 1.65 -- 3.6 V (2) -0.3 VCC=1.8V 1.4 VCC=3.6V 2.2 VIN = 0V to VCC, CE1 = VIH or CE2 = VIL -- -- 0.4 V 0.8 VCC+0.3 (3) V -- -- 1 uA -- -- 1 uA -- -- VI/O = 0V to VCC, CE1 = VIH or CE2 = VIL or OE = VIH or UB = LB = VIH VOL Output Low Voltage VOH Output High Voltage ICC Operating Power Supply Current ICC1 Operating Power Supply Current ICCSB Standby Current – TTL ICCSB1 Standby Current – CMOS VCC = Max, IOL = 0.2mA VCC=1.8V VCC = Max, IOL = 2.0mA VCC=3.6V VCC = Min, IOH = -0.1mA VCC=1.8V VCC-0.2 VCC = Min, IOH = -1.0mA VCC=3.6V 2.4 CE1 = VIL and CE2 = VIH, VCC=1.8V IDQ = 0mA, f = FMAX (4) VCC=3.6V CE1 = VIL and CE2 = VIH, VCC=1.8V IDQ = 0mA, f = 1MHz VCC=3.6V CE1 = VIH, or CE2 = VIL, VCC=1.8V IDQ = 0mA VCC=3.6V CE1≧VCC-0.2V or CE2≦0.2V, VCC=1.8V VIN ≧VCC-0.2V or V IN ≦0.2V VCC=3.6V -- -- -- -- -- 0.2 0.4 -- V 6 8 8 12 1.0 1.5 1.5 2.0 -5.0 5.0 (5) mA 0.5 1.0 25 30 V mA mA uA O 1. Typical characteristics are at TA=25 C and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 4. FMAX=1/tRC. 5. VCC=3.0V R0201-BH616UV1611 3 Revision 1.1 Oct. 2008 BH616UV1611 DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC) SYMBOL PARAMETER TEST CONDITIONS VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time CE1≧VCC-0.2V or CE2≦0.2V, VIN≧VCC-0.2V or VIN≦0.2V CE1≧VCC-0.2V or CE2≦0.2V, VIN≧VCC-0.2V or VIN≦0.2V VCC=1.2V MIN. TYP. (1) MAX. UNITS 1.0 -- -- V -- 2.5 15 uA 0 -- -- ns -- -- ns See Retention Waveform tR Operation Recovery Time tRC (2) O 1. Typical characteristics are at TA=25 C and not 100% tested. 2. tRC = Read Cycle Time. LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled) Data Retention Mode VCC VDR≧1.0V VCC tCDR tR CE1≧VCC - 0.2V VIH CE1 VCC VIH LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled) Data Retention Mode VDR≧1.0V VCC VCC tCDR CE2 VCC tR CE2≦0.2V VIL VIL AC TEST CONDITIONS KEY TO SWITCHING WAVEFORMS (Test Load and Input/Output Reference) Input Pulse Levels VCC / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1, tCHZ2, tBDO, tOHZ, tWHZ, tOW Output Load WAVEFORM 0.5Vcc CL = 5pF+1TTL Others Output (1) OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM “H” TO “L” WILL BE CHANGE FROM “H” TO “L” MAY CHANGE FROM “L” TO “H” WILL BE CHANGE FROM “L” TO “H” DON’T CARE ANY CHANGE PERMITTED CHANGE : STATE UNKNOW DOES NOT APPLY CENTER LINE IS HIGH INPEDANCE “OFF” STATE CL = 30pF+1TTL ALL INPUT PULSES 1 TTL INPUTS VCC GND CL 90% 10% → ← Rise Time: 1V/ns 90% 10% → ← Fall Time: 1V/ns 1. Including jig and scope capacitance. R0201-BH616UV1611 4 Revision 1.1 Oct. 2008 BH616UV1611 AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC) READ CYCLE JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION CYCLE TIME : 55ns (Vcc=3.0V) CYCLE TIME : 70ns (Vcc=1.8V) MIN. TYP. MAX. MIN. TYP. MAX. UNITS tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns tAVQX tAA Address Access Time -- -- 55 -- -- 70 ns tE1LQV tACS1 Chip Select Access Time (CE1) -- -- 55 -- -- 70 ns tE2LQV tACS2 Chip Select Access Time (CE2) -- -- 55 -- -- 70 ns tBLQV tBA Data Byte Control Access Time (LB, UB) -- -- 55 -- -- 70 ns tGLQV tOE Output Enable to Output Valid -- -- 30 -- -- 35 ns tE1LQX tCLZ1 Chip Select to Output Low Z (CE1) 10 -- -- 10 -- -- ns tE2LQX tCLZ2 Chip Select to Output Low Z (CE2) 10 -- -- 10 -- -- ns tBLQX tBE Data Byte Control to Output Low Z (LB, UB) 10 -- -- 10 -- -- ns tGLQX tOLZ Output Enable to Output Low Z 5 -- -- 5 -- -- ns tE1HQZ tCHZ1 Chip Deselect to Output High Z (CE1) -- -- 25 -- -- 35 ns tE2HQZ tCHZ2 Chip Deselect to Output High Z (CE2) -- -- 25 -- -- 35 ns tBHQZ tBDO Data Byte Control to Output High Z (LB, UB) -- -- 25 -- -- 35 ns tGHQZ tOHZ Output Disable to Output High Z -- -- 25 -- -- 30 ns tAVQX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) tRC ADDRESS tOH tAA tOH DOUT R0201-BH616UV1611 5 Revision 1.1 Oct. 2008 BH616UV1611 READ CYCLE 2 (1,3,4) CE1 tACS1 CE2 DOUT tACS2(6) tCLZ tCHZ(5, 6) (5,6) READ CYCLE 3 (1, 4) tRC ADDRESS tAA OE tOE tOH tOLZ CE1 tACS1 tCLZ1(5) CE2 tCLZ2(5) tACS2 tOHZ(5) tCHZ(1,5) tCHZ2(2,5) tBA LB, UB tBE tBDO DOUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL. 5. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. R0201-BH616UV1611 6 Revision 1.1 Oct. 2008 BH616UV1611 AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC) WRITE CYCLE JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION CYCLE TIME : 55ns (Vcc=3.0V) CYCLE TIME : 70ns (Vcc=1.8V) MIN. TYP. MAX. MIN. TYP. MAX. UNITS tAVAX tWC Write Cycle Time 55 -- -- 70 -- -- ns tAVWL tAS Address Set up Time 0 -- -- 0 -- -- ns tAVWH tAW Address Valid to End of Write 45 -- -- 60 -- -- ns tELWH tCW Chip Select to End of Write 45 -- -- 60 -- -- ns tBLWH tBW Data Byte Control to End of Write 45 -- -- 60 -- -- ns tWLWH tWP Write Pulse Width 30 -- -- 35 -- -- ns tWHAX tWR1 Write Recovery Time (CE1, WE) 0 -- -- 0 -- -- ns tE2LAX tWR2 Write Recovery Time (CE2) 0 -- -- 0 -- -- ns tWLQZ tWHZ Write to Output High Z -- -- 20 -- -- 30 ns tDVWH tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns tWHQX tOW End of Write to Output Active 5 -- -- 5 -- -- ns (LB, UB) SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) tWC ADDRESS OE tCW CE1 (5) CE2 (5) tWR1(3) (11) tCW(11) tWR2(3) tBW LB, UB tAW WE tWP(2) tAS tOHZ(4,10) DOUT tDH tDW DIN R0201-BH616UV1611 7 Revision 1.1 Oct. 2008 BH616UV1611 WRITE CYCLE 2 (1,6) tWC ADDRESS CE1 tCW(11) (5) CE2 (5) tCW(11) tBW (12) LB, UB tAW WE tAS tWR(3) tWP(2) tWHZ(4,10) tOW (7) (8) DOUT tDW tDH (8,9) DIN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10.Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11.tCW is measured from the later of CE1 going low or CE2 going high to the end of write. R0201-BH616UV1611 8 Revision 1.1 Oct. 2008 BH616UV1611 ORDERING INFORMATION BH616UV1611 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE o o I: -40 C ~ +85 C PACKAGE A: BGA-48-0608 Note: Brilliance Semiconductor Inc. (BSI) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 1.4 Max. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. BALL PITCH e = 0.75 D E N D1 E1 8.0 6.0 48 5.25 3.75 E1 e D1 VIEW A 48 mini-BGA (6 x 8) R0201-BH616UV1611 9 Revision 1.1 Oct. 2008 BH616UV1611 Revision History Revision No. History Draft Date Remark 1.0 Initial Production Version - E3 pin is NC pin May 10,2006 Initial 1.1 Change -55 55ns(Max.) at VCC=1.65~3.6V to 55ns(Max.) at VCC=3.0V and 70ns(Max.) at VCC=1.8V Oct. 31, 2008 Typical value of standby current is replaced by maximum value in Featues section Remove “-: Normal” (Leaded) PKG Material in ordering information R0201-BH616UV1611 10 Revision 1.1 Oct. 2008