FMP3216DAx CMOS LPRAM Document Title 2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM Revision History Revision No. History Draft date Remark Preliminary y 0.0 Initial Draft Apr. p 10,, 2010 0.1 Removed Page Write Operation Jul. 14, 2010 1 Revision 0.1 Jul. 2010 FMP3216DAx CMOS LPRAM 2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM FEATURES • Process Technology : Full CMOS •Package Type : 48-FBGA-6.00x8.00 mm2 FMP3216DAx-HxxX : Pb-Free & Halogen Free • Low Power & Page Modes • Organization : 2M x 16 • Power Supply Voltage 2.7V ~ 3.3V • Three state output and TTL Compatible • Separated I/O power(VCCQ) & Core power(VCC) • Operating Temperature Ranges: FMP3216DA1 : support the PASR/DPD function FMP3216DA2 : support the Direct DPD function FMP3216DA4 : support the PASR/DPD/PAGE function FMP3216DA5 : support the Direct DPD/PAGE function • Page read operation by 16 words Special (-10’C to +60’C) Commercial (0’C to +70’C) E t d d ((-25’C Extended 25’C tto +85’C) 85’C) Industrial (-40’C to +85’C) (FMP3216DA4, FMP3216DA5) • DPD mode by using MRS only (FMP3216DA1, FMP3216DA4) • Direct DPD mode when /ZZ goes low (FMP3216DA2, FMP3216DA5) PRODUCT FAMILY Power Dissipation Operating Voltage (V) ICC1 Speed Product Family f = 1MHz Min. Typ. Max. FMP3216DAx-H60E FMP3216DAx-H70E 2.7 3.0 Typ. 60ns 70ns 3.3 1.5mA ISB1 (CMOS Standby Current) ICC2 f = fmax Max. Typ. Max. Typ. Max. 3mA 15mA 12mA 20mA 90uA 120uA 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C. 2. H=FBGA(Pb-Free & Halogen Free), W=WAFER 3. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C) PIN DESCRIPTION 1 2 3 4 5 6 A /LB /OE A0 A1 A2 /ZZ B I/O9 /UB A3 A4 /CS I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 A17 A7 I/O4 VCC E VCCQ I/O13 DNU A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 A19 A12 A13 WE I/O8 H A18 A8 A9 A10 A11 A20 FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. VCC VSS Row Addresses I/O1~I/O8 Row select Data cont Memory array I/O Circuit Column select Data cont I/O9~I/O16 Data cont 48 FBGA : Top View(Ball Down) 48-FBGA Column Addresses Name Function Name Function /ZZ Low Power Modes VCC Core Power /CS Chip Select Input VCCQ I/O Power /CS /OE Output Enable Input VSS Ground /OE /WE Write Enable Input /UB Upper Byte(I/O9~16) /UB /LB /WE A0 A20 A0~A20 Add Address IInputs t /LB L Lower B Byte(I/O t (I/O 1~8) 1 8) I/O1~I/O16 Data Inputs/Outputs DNU Do Not Use Control Logic /ZZ 2 Revision 0.1 Jul. 2010 FMP3216DAx CMOS LPRAM PRODUCT LIST Part Name Function FMP3216DAx-H60E FMP3216DAx-H70E 60ns, VCC=3.0V, VCCQ=3.0V 70ns, VCC=3.0V, VCCQ=3.0V 1. H=FBGA(Pb-Free & Halogen Free), W=WAFER 2. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C) FUNCTIONAL DESCRIPTION /CS /ZZ /OE /WE /LB /UB I/O1 8 I/O1-8 I/O9 16 I/O9-16 Mode Po er Power H H X1) X1) X1) X1) High-Z High-Z Deselected Standby X1) L X1) X1) X1) X1) High-Z High-Z Deselected Direct DPD2) H L X1) X1) X1) X1) High-Z High-Z Deselected Low Power Modes3) L H H H X1) X1) High-Z High-Z Output Disabled Active H H High-Z High-Z Output Disabled Active L H Dout High-Z Lower Byte Read Active H L High-Z Dout Upper Byte Read Active L L Dout Dout Word Read Active High-Z High-Z Write-abort4) Active L L H H X1) L H H L H Din High-Z Lower Byte Write Active H L High-Z Din Upper Byte Write Active L L Din Din Word Write Active Symbol Ratings Unit VIN, VOUT -0.5 to VCC+0.3V V VCC -0.2 to 3.6 V PD 1.0 W TSTG -65 to 150 ’C 1. X means don’t care.(Must be low or high state) 2. In case of FMP3216DA2 & FMP3216DA5 p product 3. In case of FMP3216DA1 & FMP3216DA4 product 4. Write data can’t be written to the memory cell. ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Power Dissipation Storage temperature 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS FMP3216DAx Item Supply voltage I/O operating voltage (VCCQ ≤ VCC) Symbol Unit Min Typ Max VCC 2.7 3.0 3.3 V VCCQ 2.7 3.0 3.3 V Ground VSS 0 0 0 V Input high voltage VIH 0.8VCCQ VCCQ VCC+0.21) V VIL -0.22) 0 0.2VCCQ V Input low voltage Note : 1. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 2. Undershoot : -1.0V in case of pulse width≤20ns. 3. Overshoot and undershoot are sampled, not 100% tested. 3 Revision 0.1 Jul. 2010 FMP3216DAx CAPACITANCE1) CMOS LPRAM (f=1MHz , TA=25’C) S b l Symbol T t Condition Test C diti Mi Min M Max U it Unit Input capacitance It Item CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled, not 100% tested. DC AND OPERATING CHARACTERISTICS Min Max Unit Input leakage current Item Symbol ILI VIN=V VSS to VCC -1 1 1 uA Output leakage current ILO /CS=VIH, /ZZ=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC -1 1 uA ICC1 Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, /ZZ=VIH, VIN≤0.2V or VIN≥VCC-0.2V - 3 mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, /ZZ=VIH, VIN=VIL or VIH - 20 mA Output low voltage VOL IOL=0.5mA 0.2VCCQ V Output high voltage VOH IOH=-0.5mA St db C Standby Current(TTL) t(TTL) ISB /CS VIH, /ZZ=V /CS=V /ZZ VIH, Other Oth inputs=V i t VIH or VIL - 03 0.3 mA A Standby Current(CMOS) ISB1 /CS≥VCC-0.2V, /ZZ≥VCC-0.2V, Other inputs=0~VCC - 120 uA ISB0 /ZZ≤0.2V, Other inputs=0~VCC, No refresh(DPD) - 10 uA ISB0a /ZZ≤0.2V, Other inputs=0~VCC, ¼ refresh area selection - 90 uA ISB0b /ZZ≤0.2V, Other inputs=0~VCC, ½ refresh area selection - 100 uA ISB0c /ZZ≤0.2V, Other inputs=0~VCC, All refresh area selection - 120 uA Average operating current Low Power Modes Test Conditions 0.8VCCQ V Operating Range Device Range Ambient Temperature FMP3216DAx-XxxS Special -10℃ to +60℃ FMP3216DAx-XxxC Commercial 0℃ to +70℃ FMP3216DAx-XxxE Extended -25℃ to +85℃ FMP3216DAx-XxxI Industrial -40℃ to +85℃ VCC VCCQ 2.7V to 3.3V 2.7V to VCC AC Input/Output Reference Waveform VCCQ Input1 VCCQ/2 2 VCCQ/23 Output Test Points VSS NOTE: 1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Inp 2 Inputt timing begins at VCCQ/2. VCCQ/2 3. Output timing ends at VCCQ/2. AC Output Load Circuit Test Point 50& DUT VCCQ/2 30pF 4 Revision 0.1 Jul. 2010 FMP3216DAx CMOS LPRAM AC CHARACTERISTICS(VCC=2.7V~3.3V) 2.7V 3.3V) Speed Bins Parameter List Read Write Page Symbol 60ns 70ns Units Min Max Min Max tRC 60 20k 70 20k ns tAA - 60 - 70 ns Read Cycle Time Address Access Time Chip Select to Output tCO - 60 - 70 ns Output Enable to Valid Output tOE - 25 - 25 ns /UB, /LB Access Time tBA - 25 - 25 ns Chip Select to Low-Z Output tLZ 10 - 10 - ns /UB, /LB Enable to Low-Z Output tBLZ 10 - 10 - ns Output Enable to Low-Z Output tOLZ 5 - 5 - ns Chip Disable to High- Z Output tHZ 0 5 0 5 ns g Z Output p /UB, /LB Disable to High- tBHZ 0 5 0 5 ns Output Disable to High- Z Output tOHZ 0 5 0 5 ns Output Hold from Address Change tOH 5 - 5 - ns Write Cycle Time tWC 60 20k 70 20k ns Chip Select to End of Write tCW 50 - 60 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 50 - 60 - ns /UB /LB Valid /UB, V lid tto E End d off W Write it tBW 50 - 60 - ns Write Pulse Width tWP 50 - 50 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 5 0 5 ns Data to Write Time Overlap tDW 15 - 15 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 5 - 5 - ns Page Mode Cycle Time tPC 20 - 25 - ns Page Mode Address Access Time tPAA - 20 - 25 ns Maximum Cycle Time tMRC - 20k - 20k ns /CS High Pulse Width tCP 10 - 10 - ns 1. /CS High Pulse Width is defined by /CS. 5 Revision 0.1 Jul. 2010 FMP3216DAx CMOS LPRAM Power Up p Sequence q 1. Apply Power 2. Maintain stable power for a minimum of 150us with /CS=/ZZ=VIH Standby Mode State machines Power On /CS=/ZZ=VIH Wait 150us /CS=VIH, /ZZ=VIH Initial State /CS=VIL, /ZZ=VIH /CS=VIH, /ZZ=VIL Active Mode /CS=VIL /ZZ=VIH /CS=VIH /ZZ=VIL /CS=VIH /ZZ=VIH /CS=VIH, /ZZ=VIL Standby Mode /CS=VIL /ZZ=VIH Low Power Modes 1 ((32M/16M/4M bits)) Low Power Modes 2 (Data Invalid) /CS=VIH, /ZZ=VIL Standby Mode Characteristics Mode Memory Cell Data Standby Current(uA) Wait Time(us) Standby Valid 120 (ISB1) 0 Invalid 10 (ISB0) 150 ¼ valid 90 (ISB0a) 0 ½ valid 100 (ISB0b) 0 valid 120 (ISB0c) 0 Low Power Modes 6 Revision 0.1 Jul. 2010 FMP3216DAx READ CYCLE (1) CMOS LPRAM (Address controlled,/CS=/OE=VIL, /ZZ=/WE=VIH, /UB or/and /LB=VIL) tRC Address tOH Data Out READ CYCLE ((2)) tAA Previous Data Valid Data Valid (/ZZ=/WE=VIH) tRC Address tOH tAA tCO /CS tHZ tBA /UB, /LB tBHZ tOE /OE tOLZ High-Z Data Out tOHZ tBLZ tLZ Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3 D 3. Do nott access d device i with ith cycle l ti timing i shorter h t th than tRC(tWC) ffor continuous ti periods i d > 20 20us. PAGE READ CYCLE (/ZZ=/WE=VIH, 16 words access) tMRC tRC tPC tPC tPC tPC tPC tPC tPC A0~A3 tAA A4~A20 tOH tCO /CS tHZ tBA /UB, /LB tBHZ tOE /OE tOLZ tBLZ Data Out High-Z tLZ tPAA tPAA Data Valid Data Valid tPAA Data Valid tPAA Data Valid tPAA Data Valid tPAA Data Valid tPAA Data Valid tOHZ Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to de device ce interconnection. te co ect o 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 4. In case page address skew is over 3ns, tPAA will be out of spec. 7 Revision 0.1 Jul. 2010 FMP3216DAx WRITE CYCLE (1) CMOS LPRAM (/WE controlled, /ZZ=VIH) tWC Address tCW(2) tWR(4) /CS tAW tBW /UB, /LB tWP(1) /WE tAS(3) tDW Data in tWHZ Data Out WRITE CYCLE (2) tDH Data Valid High-Z High-Z tOW Data Undefined (/CS controlled, /ZZ=/WE=VIH) tWC Address tAS(3) tWR(4) tCW(2) /CS tAW tBW /UB, /LB tWP(1) /WE tDW Data Out WRITE CYCLE (3) tDH Data Valid Data in High-Z High-Z (/UB, /LB controlled, /ZZ=VIH) tWC Address tWR(4) tCW(2) /CS tAW tBW /UB, /LB tAS(3) tWP(1) /WE tDW Data Out tDH Data Valid Data in High-Z High-Z 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. g g of write. 3. tAS is measured from the address valid to the beginning 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 8 Revision 0.1 Jul. 2010 FMP3216DAx CMOS LPRAM LOW POWER MODES 1. Mode Register Set A20 ~ A5 0 A4 A3 A2 ZZ Array On/Off on /ZZ Half Selection Enable/Disable /ZZ Enable/Disable A1 A0 Array Refresh Area Array On/Off on /ZZ A4 Type A3 Type 0 Deep Power Down Enable 0 Partial Array Refresh Mode (Default) 1 DPD Disable (Default) 1 Reduced Memory Size Mode N t If the Note: th register i t is i written itt to t enable bl the th Deep D Power Down, the part will go into Deep Power Down during the following time that /ZZ is driven low and there is no MRS update. When /ZZ is driven high, all of the register settings will return to default state for the part (i.e. full array refresh, Deep Power Down Disabled). Half Selection (Top / Bottom) Note: N t The Th RMS(Reduced RMS(R d d Memory M Size) Si ) mode d is i enabled bl d after ft /ZZ goes high and remains enabled after /ZZ goes high. To change to a different mode, the mode register will have to be rewritten. Array Refresh Area A2 Type A1 A0 Type 0 Bottom (Default) 0 0 Full Array (Default) 1 Top 0 1 RFU 1 0 ½ Array 1 1 ¼ Array 2. MRS Update tWC Address tAS(3) tCW(2) tWR(4) /CS tAW tBW /UB, /LB tWP(1) /WE /ZZ tZZWE Register Write Start Register Write Complete Register Update Complete The register update take place on the rising eDAe of /ZZ. Once the register is updated, the next time /ZZ goes low, without any updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a don’t care When /ZZ is low during the register updates. 9 Revision 0.1 Jul. 2010 FMP3216DAx CMOS LPRAM 3 D 3. Deep P Power D Down M Mode d E Entry/Exit t /E it tWC A4 tAS(3) tWR(4) tCW(2) /CS tAW tBW /UB, /LB tWP(1) /WE tZZWE tR Next Cycle tZZmin /ZZ Register Write(DPD) Deep Power down exit Deep Power down start Parameter Description Min Max Units tZZWE ZZ low to Write Enable Low 0 1 us tR(Deep Power Down Mode only) Operation Recovery Time 150 - us tZZmin Low Power Mode Time 10 - us 4. Address Information Partial Array Refresh Mode (A3=0, A4=1) A2 A1,A0 Refresh Section Address Size Density 0 11 1/4 000000h-7FFFFh 512Kbx16 8Mb 0 10 1/2 000000h-FFFFFh 1Mbx16 16Mb X 00 F ll Full 000000h 1FFFFFh 000000h-1FFFFFh 2Mb 16 2Mbx16 32Mb 1 11 1/4 180000h-1FFFFFh 512Kbx16 8Mb 1 10 1/2 100000h-1FFFFFh 1Mbx16 16Mb Reduced Memory Size Mode (A3=1, A4=1) A2 A1,A0 Refresh Section Address Size Density 0 11 1/4 000000h-7FFFFh 512Kbx16 8Mb 0 10 1/2 000000h-FFFFFh 1Mbx16 16Mb 1 11 1/4 180000h-1FFFFFh 512Kbx16 8Mb 1 10 1/2 100000h-1FFFFFh 1Mbx16 16Mb 10 Revision 0.1 Jul. 2010 FMP3216DAx CMOS LPRAM PACKAGE DIMENSION Unit : millimeters 48 BALL FINE PITCH BGA(0 BGA(0.75mm 75mm ball pitch) Top View Bottom View B A1 INDEX MARK B1 B 0.05 0.05 6 5 4 3 2 1 A B C #A1 C C C1 D C1 1/2 E F G H B/2 0.25/Typ. E2 D A Y 0.85/Typ. E Detail A E1 0.30 Side View C - Min Typ A - 0.75 Max - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5 25 5.25 - D 0.30 0.35 0.40 E - 1.10 1.20 E1 - 0.85 - E2 0.20 0.25 0.30 Y - - 0.08 11 NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are +/-0.050 unless otherwise specified. 4. Typ : Typical 5 Y is coplanarity : 0 5. 0.08(Max) 08(Max) Revision 0.1 Jul. 2010