A64E06161 Preliminary 1M X 16 Bit Low Voltage Super RAM Document Title 1M X 16 Bit Low Voltage Super RAM Revision History History Issue Date Remark 0.0 Initial issue October 12, 2003 Preliminary 0.1 Change VCC range and VCCQ range November 30, 2004 Rev. No. Change page access time from 20ns to 25ns Change operation current (ICC1) from 25mA to 15mA(-70) Change operation current (ICC1) from 20mA to 12mA(-85) Change standby current (ISB1) from 80uA to 100uA Delete reduce memory size 16M, partial array refresh 16M Change operation current (ICC2) form 5mA to 3mA(-70, -85) Change PAR current 12Mb=90uA, 8Mb=80uA, 4Mb=70uA Change TCR current +85°C=100uA +70°C=90uA Change TCR current +45°C=85uA +15°C=75uA PRELIMINARY (November, 2004, Version 0.1) AMIC Technology, Corp. A64E06161 Preliminary 1M X 16 Bit Low Voltage Super RAM Features Support 4 distinct operation modes for reducing standby power : Deep Power Down (DPD) mode Reduce Memory Size (RMS) mode (4M, 8M, 12M) Partial Array Refresh (PAR) mode (4M,8M,12M) Temperature Compensated Refresh (TCR) mode Industrial operating temperature range: -25°C to +85°C for – I Available in 48-ball Mini BGA (6X8) package. Operating voltage: VCC: 1.7V to 1.95V VCCQ: 1.7V to VCC Access times: tAA = 70ns (max.) Page Access times: tPAA = 25ns (max) Current: A64E06161 series: Operating Current (Icc1) : 15mA (max.) Standby Current (Isb1) : 100uA (max) Deep Power Down Standby Current (IZZ) : 10µA (max.) 4-word page length General Description The A64E06161 is a low operating current 16,777,216-bit super RAM organized as 1,048,576 word by 16bit and operated on low power supply voltage from 1.7V to 1.95V. It is built using AMIC’s high performance CMOS DRAM process. Using hidden refresh technique, the A64E06161 provides a compatible asynchronous interface and data can be read in 4-word page mode for fast access times. The A64E06161 has an internal register named the Configuration Register (CR) that controls the operation. The A64E06161 is designed for reducing current consumption during hidden self refresh and operating through following mode: Deep Power Down (DPD) mode, Reduce Memory Size (RMS) mode, Partial Array Refresh (PAR) mode and Temperature Compensated refresh (TCR) mode. This A64E06161 is suited for low power application such as mobile phone and PDA or other battery-operated handheld device. Pin Configuration Mini BGA (6X8) Top View 1 2 3 4 5 6 A LB OE A0 A1 A2 ZZ B I/O8 HB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSSQ I/O11 A17 A7 I/O3 VCC E VCCQ I/O12 NC A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC A64E06161G PRELIMINARY (November, 2004, Version 0.1) 1 AMIC Technology, Corp. A64E06161 Block Diagram VCC A0 VSS DECODER A18 16,777,216 VCCQ MEMORY ARRAY VSSQ A19 I/O8 I/O0 INPUT COLUMN I/O INPUT DATA CIRCUIT DATA CIRCUIT I/O15 I/O7 CE ZZ LB HB OE WE CONTROL CIRCUIT Pin Description Symbol A0 - A19 CE ZZ I/O0 - I/O15 Description Address Inputs Chip Enable Input Sleep Enable Input (When ZZ is low, the CR register can be loaded or the device can enter DPD mode or PAR mode). Data Input/Outputs WE Write Enable Input LB Byte Enable Input (I/O0 to I/O7) HB Byte Enable Input (I/O8 to I/O15) OE Output Enable Input VCC Power VSS Ground VCCQ Provide isolated power to I/O for improved noise immunity VSSQ Provide isolated / Ground to I/O for improved noise immunity NC PRELIMINARY No Connection or VSSQ (November, 2004, Version 0.1) 2 AMIC Technology, Corp. A64E06161 Recommended DC Operating Conditions (TA = 0°C to + 70°C or -25°C to 85°C) Symbol Parameter Min. Max. Unit 1.7 1.95 V 0 0 V 1.7 VCC V 0 0 V VCC Supply Voltage VSS Ground VCCQ Supply Voltage I/O only VSSQ Ground I/O only VIH Input High Voltage 1.4 VCCQ + 0.2 V VIL Input Low Voltage -0.2 +0.4 V CL Output Load - 30 pF Absolute Maximum Ratings* *Comments VCC to VSS . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V VCCQ to VSSQ . . . . . . . . . . . . . . . -0.3V to VCCQ+0.3V IN, IN/OUT Volt to GND . . . . . . . . -0.3V to VCCQ + 0.3V Storage Temperature, Tstg . . . . . . . . -55°C to +125°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W Soldering Temp. & Time . . . . . . . . . . . . 260°C, 10 sec Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol (TA = 0°C to + 70°C or -25°C to 85°C, VCC = 1.7V to 1.95V, VCCQ = 1.7V to VCC GND = 0V) -70 Parameter ⎜ILI⎥ Input Leakage Current ⎜ILO⎥ Output Leakage Current ICC1 -85 Unit Min. Max. Min. Max. - 1 - 1 µA VIN = GND to VCCQ - 1 - 1 µA CE = VIH or ZZ = VIL or OE = VIH or WE = VIL VI/O = GND to VCCQ - 15 - 12 mA - 3 - 3 mA CE = VIL, ZZ = VIH = VCCQ, VIL = 0V, f = 1MHz, II/O = 0mA Dynamic Operating Current ICC2 Conditions Min. Cycle, Duty = 100% VIH CE = VIL, ZZ = VIH = VCCQ, VIL = 0V, II/O = 0mA ISB1 Standby Power Supply Current - 100 - 100 µA CE ≥ VCCQ - 0.2V ZZ ≥ VCCQ - 0.2V VIN ≥ 0V VOL Output Low Voltage - 0.2 - 0.2 V IOL = 0.2 mA VOH Output High Voltage VCCQ-0.2 - VCCQ-0.2 - V IOH = -0.2mA PRELIMINARY (November, 2004, Version 0.1) 3 VIH AMIC Technology, Corp. A64E06161 Deep Power Down Specifications and Conditions Symbol Description Conditions Typ. IZZ Deep Power-Down VIN = VCCQ or 0V; +25°C ZZ = LOW CR[4] = 0 Max. Units 10 µA Partial Array Refresh Specifications Conditions Symbol Conditions Density Array Partition VIN = VCCQ or 0V ZZ = LOW CR[4] = 1 12Mb Description IPAR Partial Array Refresh Current Typ. Max. Units 3/4 90 µA 8Mb 1/2 80 µA 4Mb 1/4 70 µA Max. Units Note: IPAR (MAX) values measured with TCR set to 85°C Temperature Compensated Refresh Specifications Conditions Symbol Conditions Density Max Case Temperatures VIN = VCCQ or 0V Chip Disabled 16Mb +85°C 100 µA +70°C 90 µA +45°C 80 µA +15°C 70 µA Description ITCR Temperature Compensated Refresh Standby Current Typ. Note: 1. ITCR (MAX) values measured with FULL ARRAY refresh. 2. This device assumes a standby mode if the chip is disabled ( CE HIGH). Truth Table I/O0 to I/O7 Mode I/O8 to I/O15 Mode VCC Current CE ZZ OE WE LB HB H H X X X X Not selected Not selected ISB1 H L X X X X Not selected Not selected IZZ*2 H L X X X X Not selected Not selected IPAR*2 L L X L X X Not selected Not selected Load CR Register L L Read Read ICC1, ICC2 L H Read High - Z ICC1, ICC2 H L High - Z Read ICC1, ICC2 L L Write Write ICC1, ICC2 L H Write Not Write/Hi - Z ICC1, ICC2 H L Not Write/Hi - Z Write ICC1, ICC2 X X High - Z High - Z ICC1, ICC2 L L L H H H L X H H L H Note: 1. X = H or L 2. DPD is enable when CR register A4 is “0”; otherwise, PAR is enable PRELIMINARY (November, 2004, Version 0.1) 4 AMIC Technology, Corp. A64E06161 Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance - 6 pF VIN = 0V CI/O* Input/Output Capacitance - 6 pF VI/O = 0V * These parameters are sampled and not 100% tested. Initialization The A64E06161 is initialized in the power-on sequence according to the following. 1. To stabilize internal circuits, after turning on the power, a 200µs or longer wait time must precede any signal toggling. 2. After the wait time, it can be normal operation. Power on Chart VCC(min) VCC CE 200us Wait Time ZZ Normal Operation Notes: 1. Following power application, make CE high level during the wait time 200us interval. 2. After power on sequence, the normal operating ZZ must keep at high. Standby Mode State Machines Power On CE = VIH Wait 200us CE = VIH, ZZ = VIH Initial State CE = VIL, ZZ = VIH HB or/and LB = V IL CE = VIH, ZZ = VIL Active Mode CE = VIL ZZ = VIH Standny Mode CE = VIH ZZ = VIH CE = VIH ZZ = VIL CE = VIH, ZZ = VIH CE = VIL ZZ = VIH PAR Mode (12M/8M/4M bits) DPD Mode (Data Invalid) CE = VIH, ZZ = VIL CE = VIH, ZZ = VIL Note: DPD is enable when CR register A4 is “0”; otherwise, PAR is enable. PRELIMINARY (November, 2004, Version 0.1) 5 AMIC Technology, Corp. A64E06161 Configuration Register The configuration register (CR) defines how the A64E06161 operates and whether page mode read accesses are permitted. The register is automatically loaded with default setting during power on and can be updated anytime while the device is operating in a normal state. CR Register Description Reserved PAGE A19 - A8 A7 TCR A6 A5 Bit(s) A19 - A8 7 ZZ Enable Deep Sleep Array On/Off on ZZ A4 PAR Top/Bottom Selection A3 Name A2 PAR Memory Selection A1 A0 Deserved Reserved Reserved, All must be set to “0” Page Mode on/off 0 - Page Mode Disabled (Default) 1 - Page Mode Enabled 6, 5 4 3 2 1-0 PRELIMINARY Temperature Compensated Register Section ZZ Enable Deep Sleep Array On/Off on ZZ PAR Top/Bottom Half Selection PAR Memory Selection (November, 2004, Version 0.1) 11 - +85°C (Default) 00 - +70°C 01 - +45°C 10 - +15°C 0 - DPD Mode Enabled 1 - DPD Mode Disabled (Default) 0 - PAR Mode (Default) 1 - RMS Mode 0 - Bottom (Default) 1 - Top 01 - 3/4 Array (12M) 10 - 1/2 Array (8M) 11 - 1/4 Array (4M) 6 AMIC Technology, Corp. A64E06161 CR Register Update – Timing Waveform tWC Address Eight Lower-order address bits (A7-A0) Define PAR Register tCW CE tZZCE tAW tWR tAS tWP WE ZZ tZZWE tZZMIN Figure 1: CR register update–Timing waveform Notes: 1. VIH(MAX) = VCCQ + 0.2V for pulse durations less than 20ns. 2. VIL(MIN) = -1V for pulse duration less than 20ns. 3. Overshoot and undershoot specifications are characterized and are not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.) and TA = 25°C. 5. The timing values for the CR Register Update are shown in the “Partial Array Mode Timing” table and “AC Characteristics” table. PRELIMINARY (November, 2004, Version 0.1) 7 AMIC Technology, Corp. A64E06161 Page Mode Description to a ” 0”. The device stays in the Deep Power Down (DPD) The Page Mode operation takes advantage of the fact that adjacent address can be read in shorter period of time than random addresses. Write operations do not support comparable page mode functionality. The Page Mode operation can be enabled and disabled in the CR register. If the CR register bit A7 is set to a “1”, Page Mode operation is enabled. mode until ZZ is driven High. If the A4 register bit is set equal to “1”, Deep Power Down (DPD) mode will not be activated. Once the A64E06161 exits the Deep Power Down (DPD) mode, the content of the CR register is destroyed and the CR register would go into the default state upon normal operation. 2. Reduce Memory Size (RMS) mode The A64E06161 provides following operation mode for reducing power: 1. Deep Power Down (DPD) mode 2. Reduce Memory Size (RMS) mode 3. Partial Array Refresh (PAR) mode 4. Temperature Compensated Refresh (TCR) mode In this mode, the A64E06161 can be operated as a reduced size device. For example, one can operate the 16M A64E06161 as a 4M or 8M memory block. Reduce Memory Size (RMS) mode can be enabled by having the appropriate setting in the CR register. The mode is effective once ZZ goes high and remains in the Reduce Memory Size (RMS) mode until full array restored by setting the CR register again. At power on, all four section of the device are activated and the A64E06161 enter into its default state of full memory size and refresh space. 1. Deep Power Down (DPD) mode In this mode, the internal refresh is turned off and all data integrity of the array is lost. Deep Power Down (DPD) mode is entered by ZZ low and keep 10us with A4 register bit set Variable Address Space – Address Patterns A2 0 0 0 A1, A0 Refresh Section 11 One-fourth of the Die 10 Half of the Die 01 Three-fourths of the Die 00000h - BFFFFh (A19 : A18 ≠ 11) C0000h - FFFFh (A19 = A18 = 1) 80000h - FFFFFh (A19 = 1) 1 1 1 11 10 01 0 0 0 11 10 01 40000h - FFFFFh (A19: A18 ≠ 00) Reduced Memory Size Mode (A3 = 1, A4 = 1) One-fourth of the Die 00000h - 3FFFFh (A19 = A18 = 0) Half of the Die 00000h - 7FFFFh (A19 = 0) Three-fourths of the Die 00000h - BFFFFh (A19 : A18 ≠ 11) 1 1 1 11 10 01 One-fourth of the Die Half of the Die Three-fourths of the Die PRELIMINARY One-fourth of the Die Half of the Die Three-fourths of the Die Partial Array Refresh Mode (A3 =0, A4 = 1) Address 00000h - 3FFFFh (A19 = A18 = 0) 00000h - 7FFFFh (A19 = 0) C0000h - FFFFh (A19 = A18 = 1) 80000h - FFFFFh (A19 = 1) 40000h - FFFFFh (A19 : A18 ≠ 00) (November, 2004, Version 0.1) 8 Size 256K × 16 512K × 16 768K × 16 Density 4M 8M 12M 256K × 16 512K × 16 768K × 16 4M 8M 12M 256K × 16 512K × 16 768K × 16 4M 8M 12M 256K × 16 512K × 16 768K × 16 4M 8M 12M AMIC Technology, Corp. A64E06161 Memory Block Spilt Bottom Address Range 0 1 0 1 0 0 1 1 1/4 Address Space Refresh Active Address Space: A0-A17 A<18,19> = <0,0> 0 1 0 1 0 0 1/2 Address Space Refresh Active Address Space: A0-A18 A<19> = <0> 1 1 Full Address Space Refresh Active Address Space: A0-A19 A<18,19> = <X, X> 3/4 Address Space Refresh Active Address Space: A0-A19 A<18,19> = <0,0>,<1,0>,<0,1> Top Address Range 0 1 0 1 0 0 1/2 Address Space Refresh Active Address Space: A0-A18 A<19> = <1> 0 1 0 1 0 0 1 1 1/4 Address Space Refresh Active Address Space: A0-A17 A<18,19> = <1,1> PRELIMINARY (November, 2004, Version 0.1) 1 1 Full Address Space Refresh Active Address Space: A0-A19 A<18,19> = <X, X> 3/4 Address Space Refresh Active Address Space: A0-A19 A<18,19> = <1,0>,<0,1>,<1,1> 9 AMIC Technology, Corp. A64E06161 3. Partial Array Refresh (PAR) mode In this mode, customers can turn off section of A64E06161 in stand-by mode to save standby current. The A64E06161 is divided into four 4M sections allowing certain section to be active. The array partition to be refreshed is determined by the respective bit in the CR register. When ZZ is active low, only the portion of the array that is set in the CR register is refreshed and the data is keep at a certain section of memory. The Partial Array Refresh (PAR) mode is only available during standby time ( ZZ low). Once ZZ is turned high, the A64E06161 goes back to operating in full array refresh. For Partial Array Refresh (PAR) mode to be activated, the register bit, A4 must be set to a “1” value. To change the address space of the Partial Array Refresh (PAR) mode, the CR register must be updated using the CR register description. If the CR register is not updated after power on, the A64E06161 will be in its default state and the whole memory array will be refreshed. Partial Array Refresh – Entry/Exit ZZ Partial Array Mode/ Deep Power Down Mode 1us suspend tCDR tR CE or UB / LB Figure 2: Partial Array refresh – Entry/Exit Partial Array Mode Timings Parameter tZZWE tCDR tR tZZMIN tZZCE tZZBE Description Min. ZZ LOW to WE LOW Chip Deselect to ZZ LOW Operation Recovery Time (Deep Power Down Mode only) Deep Power Down Mode Time ZZ LOW to CE LOW ZZ LOW to UB / LD LOW Max. 1 0 Unit µs µs 10 0 200 1 µs µs µs 0 1 µs Notes: 1. OE and the data pins are in a “don’t care” state while the device is in Partial Array Mode. 2. All other timing parameters are as shown in the switching characteristics section. 3. tR applies only in the Deep Power Down Mode. 4. Temperature Compensated Refresh (TCR) mode In this mode, the hidden refresh rate can be optimized for the operating temperature. At higher temperature, the DRAM cell must be refreshed more often than at lower temperature. By setting the temperature of operation in CR register, the refresh rate can be optimized to meet the low standby PRELIMINARY (November, 2004, Version 0.1) current at given operating temperature. There are four selections (+15°C, +45°C, +70°C, +85°C) in the CR register description. 10 AMIC Technology, Corp. A64E06161 Avoid Timing Following Figure 3 is show you an abnormal timing which is not supported on Super RAM. CE WE Less than 30ns Address Note: Address = A0 ~ A19 Under CR register A7 = 0 Address = A2 ~ A19 Under CR register A7 = 1 Figure 3 Operation When Page Mode is Enabled The maximum CE pulse width should not exceed 10µs to accommodate orderly scheduling of refresh (Figure 4). CE tCEM ≤ 10us Note: Timing constraints when page mode is enabled. Figure 4: Timing constraint for tCEM PRELIMINARY (November, 2004, Version 0.1) 11 AMIC Technology, Corp. A64E06161 AC Characteristics Symbol (TA = 0°C to + 70°C or -25°C to 85°C, VCC = 1.7V to 1.95V, VCCQ = 1.7V to VCC GND = 0V) Parameter -70 -85 Unit Min. Max. Min. Max. Address Setup to CE Low 70 5 5 5 0 0 0 10 0 10000 10 70 70 35 35 14 14 14 - 85 5 5 5 0 0 0 10 0 10000 10 85 85 45 45 14 14 14 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns tAHC Address Hold Time from CE High 0 - 0 - ns tCEH CE High Pulse With Page Read Cycle Time Page access Time Normal to Page Read Cycle Time 10 - 10 - ns 25 - 25 10 25 - 25 10 ns ns µs 10000 10 14 - 85 85 70 0 85 60 0 35 0 5 0 10000 10 14 - ns ns ns ns ns ns ns ns ns ns ns ns ns Read Cycle tRC tSKEW tAA tACE tBE tOE tCLZ tBLZ tOLZ tCHZ tBHZ tOHZ tOH tASC tPC tPAA tNPPC Write Cycle tWC tSKEW tCW tBW tAS tAW tWP tWR tWHZ tDW tDH tOW tASC Read Cycle Time Address Skew Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Byte Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Byte Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change Write Cycle Time Address Skew Chip Enable to End of Write Byte Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write Address Setup to CE Low 70 70 60 0 70 50 0 30 0 5 0 tAHC Address Hold Time from CE High 0 - 0 - ns tCEH CE High Pulse With 10 - 10 - ns tWEH WE High Pulse With 10 - 10 - ns tCEM Maximum CE Pulse width - 10 - 10 µs Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. PRELIMINARY (November, 2004, Version 0.1) 12 AMIC Technology, Corp. A64E06161 Timing Waveforms Read Cycle 1(1, 2, 4, 6) tSKEW tRC tSKEW tRC Address tAA tOH tAA tOH DOUT tASC CE Read Cycle 2-1(1, 3, 6) tSKEW tRC tSKEW tRC Address tASC tAHC tASC tAHC tAA tAA tCEH CE tACE tCLZ5 HB , LB tCHZ5 tBE tBLZ5 tACE tCLZ5 tCHZ5 tBE tBHZ5 tBLZ5 tBHZ5 OE tOE tOLZ5 tOE tOLZ5 tOHZ5 tOHZ5 DOUT PRELIMINARY (November, 2004, Version 0.1) 13 AMIC Technology, Corp. A64E06161 Read Cycle 2-2(1, 3, 6) tSKEW tSKEW tRC tSKEW tRC Address tASC tAHC tAA tAA CE tACE tCLZ5 tCHZ5 tBE tBE HB , LB tBLZ5 tBHZ5 tBLZ5 tBHZ5 OE tOE tOLZ5 tOE tOLZ5 tOHZ5 tOHZ5 DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. ZZ is high for Read Cycle. Timing Waveforms Words Page Read Cycle Timing Chart tNPPC tRC tSKEW tPC Address A2~A19 tPC AN+1 AN tSKEW tPC AN+2 AN+3 Page Address (A0~A1) tASC tAHC CE tCHZ tACE tPAA tOH I/O (Output) OE, HB, LB PRELIMINARY QN tPAA tOH tOH QN+1 QN+2 tOH QN+3 tOHZ tBHZ tOE tBE (November, 2004, Version 0.1) tPAA 14 AMIC Technology, Corp. A64E06161 Timing Waveforms (continued) Write Cycle 1-1(6) (Write Enable Controlled) tSKEW tWC tSKEW tWC Address tASC tAHC tASC tAHC tAW tAW tCW tCEH tCW CE tBW tBW HB , LB tWR3 tAS1 tWR3 tAS1 tWP2 tWP2 WE tDW tDH tDW tDH Data In tWHZ4 tWHZ4 tOW tOW Data Out Write Cycle 1-2(6) (Write Enable Controlled) tSKEW tSKEW tWC tSKEW tWC Address tASC tAHC CE tBW tBW HB , LB tWR3 tAS1 tWR3 tAS1 tWP2 tWP2 WE tWEH tDW tDH tDW tDH Data In tWHZ4 tWHZ4 tOW tOW Data Out PRELIMINARY (November, 2004, Version 0.1) 15 AMIC Technology, Corp. A64E06161 Timing Waveforms (continued) Write Cycle 2-1(6) (Chip Enable Controlled) tSKEW tWC tSKEW tWC Address tAHC tAW tAHC tAW tASC tASC tCW2 tCEH tCW2 CE tWR3 tBW tWR3 tBW HB , LB tWP tWP WE tDW tDH tDW tDH Data In tWHZ4 tWHZ4 tOW tOW Data Out Timing Waveforms Write Cycle 3-1(6) (Byte Enable Controlled) tSKEW tWC tSKEW tWC Address tAHC tAW tAHC tAW tASC tASC tCW tAS1 tBW2 tCEH tCW CE tWR3 tAS1 tWR3 tBW2 HB , LB tWP tWP WE tDW tDH tDW tDH Data In tWHZ4 tWHZ4 tOW tOW Data Out PRELIMINARY (November, 2004, Version 0.1) 16 AMIC Technology, Corp. A64E06161 Write Cycle 3-2(6) (Byte Enable Controlled) tSKEW tSKEW tWC tSKEW tWC Address tAHC tAW tASC CE tAS1 tWR3 tBW2 tAS1 tWR3 tBW2 HB , LB tWP tWP WE tDW tDH tDW tDH Data In tWHZ4 tWHZ4 tOW tOW Data Out Notes: 1. 2. 3. 4. 5. 6. tAS is measured from the address valid to the beginning of Write. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and, or LB ). tWR is measured from the earliest of CE or WE or ( HB and, or LB ) going high to the end of the Write cycle. OE level is high or low. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. ZZ is high for Write Cycle. AC Test Conditions Input Pulse Levels VCCQ * 0.2 to VCCQ * 0.8 Input Rise And Fall Time 2 ns (10% to90%) Input and Output Timing Reference Levels 0.5 * VCCQ Output Load See Figures 5 VCCQ 2.7KΩ OUT Test Point 2.7KΩ 30pF Figure 5. Output Load Circuit PRELIMINARY (November, 2004, Version 0.1) 17 AMIC Technology, Corp. A64E06161 Ordering Information Access Time (ns) Operating Current Max. (mA) Deep Power Down Mode Standby Current Max. (µA) Package A64E06161G-70 70 15 10 48B Mini BGA A64E06161G-85 85 12 10 48B Mini BGA A64E06161G-70I 70 15 10 48B Mini BGA A64E06161G-85I 85 12 10 48B Mini BGA Part No. Note: -I is for industrial operating temperature range PRELIMINARY (November, 2004, Version 0.1) 18 AMIC Technology, Corp. A64E06161 Package Information unit: mm 48LD CSP (6 x 8 mm) Outline Dimensions (48TFBGA) TOP VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER b (48X) 6 5 4 3 2 1 1 2 3 4 5 6 A B C D E E1 e A B C D E F G E F G H H B A 0.10 C SIDE VIEW D 0.20(4X) Symbol A A1 D E D1 E1 e b A SEATING PLANE A1 C e D1 Dimensions in mm MIN. NOM. MAX. --0.20 5.90 7.90 ------0.30 --0.25 6.00 8.00 3.75 5.25 0.75 0.35 1.20 0.30 6.10 8.10 ------0.40 Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 4. BALL PAD OPENING OF SUBSTRATE IS Φ 0.3mm (SMD) SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.3mm (NSMD) PRELIMINARY (November, 2004, Version 0.1) 19 AMIC Technology, Corp.