TI TPS3307

TPS3307-18-Q1
TRIPLE PROCESSOR SUPERVISORS
SGLS136 – NOVEMBER 2002
D Qualification in Accordance With
D
D
D
D
D
D Temperature-Compensated Voltage
AEC-Q100†
Qualified for Automotive Applications
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Triple Supervisory Circuits for DSP and
Processor-Based Systems
Power-On Reset Generator with Fixed
Delay Time of 200 ms, No External
Capacitor Needed
D
D
D
D
D
Reference
Maximum Supply Current of 40 µA
Supply Voltage Range . . . 2 V to 6 V
Defined RESET Output from VDD ≥ 1.1 V
SO-8 Package
Temperature Range . . . –40°C to 125°C
D PACKAGE
(TOP VIEW)
SENSE1
SENSE2
SENSE3
GND
† Contact factory for details. Q100 qualification data available on
request.
1
8
2
7
3
6
4
5
VDD
MR
RESET
RESET
typical applications
Figure 1 lists some of the typical applications for the TPS3307 family, and a schematic diagram for a
processor-based system application. This application uses TI part numbers TPS3307–18 and TMS470R1Vxxx.
2.5 V
3.3 V
1.8 V
VDD
100 nF
SENSE 1
SENSE 2
470 kΩ
TMS470R1Vxxx
RESET
RESET
TPS3307-18
GND
SENSE 3
620 kΩ
VDD
•
•
•
•
Automotive applications using DSPs,
Microcontrollers or Microprocessors
Industrial Equipment
Programmable Controls
Automotive Systems
GND
Figure 1. Applications Using the TPS3307-18
description
The TPS3307-18 is a micropower supply voltage supervisor designed for circuit initialization primarily in
automotive DSP and processor-based systems, which require more than one supply voltage.
The TPS3307-18 is designed for monitoring three independent supply voltages: 3.3 V/1.8 V/adj,. The adjustable
SENSE input allows the monitoring of any supply voltage >1.25 V.
The various supply voltage supervisors are designed to monitor the nominal supply voltage as shown in the
following supply voltage monitoring table.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TPS3307-18-Q1
TRIPLE PROCESSOR SUPERVISORS
SGLS136 – NOVEMBER 2002
description (continued)
SUPPLY VOLTAGE MONITORING
NOMINAL SUPERVISED VOLTAGE
DEVICE
SENSE1
SENSE2
THRESHOLD VOLTAGE (TYP)
SENSE3
SENSE1
SENSE2
SENSE3
1.25 V†
TPS3307-18
3.3 V
1.8 V
User defined
2.93 V
1.68 V
† The actual sense voltage has to be adjusted by an external resistor divider according to the application requirements.
During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supply voltage supervisor monitors the SENSEn inputs and keeps RESET active as long as SENSEn remain
below the threshold voltage VIT+.
An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset.
The delay time, td typ = 200 ms, starts after all SENSEn inputs have risen above the threshold voltage VIT+. When
the voltage at any SENSE input drops below the threshold voltage VIT–, the RESET output becomes active (low)
again.
The TPS3307-18 incorporates a manual reset input, MR. A low level at MR causes RESET to become active.
In addition to the active-low RESET output, the TPS3307-18 includes an active-high RESET output.
The device is available in a standard 8-pin SO package, and is characterized for operation over a temperature
range of –40°C to 125°C.
ORDERING INFORMATION
PACKAGE‡
TA
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 125°C
Small Outline (D) Tape and Reel TPS3307-18QDRQ1
30718Q
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION/TRUTH TABLES
MR
SENSE1>VIT1
X
SENSE2>VIT2
X
SENSE3>VIT3
X
RESET
RESET
L
L
H
H
0
0
0
L
H
H
0
0
1
L
H
H
0
1
0
L
H
H
0
1
1
L
H
H
1
0
0
L
H
H
1
0
1
L
H
H
1
1
0
L
H
H
1
1
1
H
L
X = Don’t care
PowerPAD is a trademark of Texas Instruments Incorporated.
2
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TPS3307-18-Q1
TRIPLE PROCESSOR SUPERVISORS
SGLS136 – NOVEMBER 2002
functional block diagram
VDD
TPS3307
14 kΩ
MR
R1
+
_
SENSE 1
R2
R3
SENSE 2
R4
+
_
RESET
RESET
Logic + Timer
RESET
GND
Reference
Voltage
of 1.25 V
_
Oscillator
+
SENSE 3
timing diagram
SENSEn
V(nom)
VIT–
t
MR
1
0
t
RESET
1
t
0
td
td
td
RESET Because of SENSE Below VIT
RESET Because of MR
RESET Because of SENSE Below VIT–
RESET Because of SENSE Below VIT–
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3
TPS3307-18-Q1
TRIPLE PROCESSOR SUPERVISORS
SGLS136 – NOVEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 mA
Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t = 1000 h
continuously.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
377 mW
145 mW
recommended operating conditions at specified temperature range
MAX
UNIT
Supply voltage, VDD
MIN
2
6
V
Input voltage at MR and SENSE3, VI
0
0
VDD+0.3
(VDD+0.3)VIT/1.25V
V
Input voltage at SENSE1 and SENSE2, VI
High-level input voltage at MR, VIH
0.7xVDD
Low-level input voltage at MR, VIL
Input transition rise and fall rate at MR, ∆t/∆V
Operating free-air temperature range, TA
4
–40
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V
V
0.3×VDD
50
ns/V
V
125
°C
TPS3307-18-Q1
TRIPLE PROCESSOR SUPERVISORS
SGLS136 – NOVEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
VDD = 2 V to 6 V,
VDD = 3.3 V,
High-level
High
level out
output
ut voltage
VDD = 6 V,
VDD = 2 V to 6 V,
VOL
VDD = 3.3 V,
VDD = 6 V,
Low-level
Low
level out
output
ut voltage
VDD ≥ 1.1 V,
Power-up reset voltage (see Note 2)
IOH = –20 µA
IOH = –2 mA
IOH = –3 mA
IOL = 20 µA
Vhys
Negative-going
Negative
going input threshold voltage
(see Note 3)
VSENSE2
VSENSE1
MR
IH
High level input current
High-level
IL
Low level input current
Low-level
IDD
Ci
Supply current
VDD = 2 V to 6 V,
V
TA = –40°C
40°C to 125°C
VIT– = 1.25 V
VIT– = 1.68 V
VIT– = 2.93 V
Hysteresis at VSENSEn in
input
ut
TYP
V
0.4
SENSE2
VSENSE2 = VDD = 6 V
SENSE3
VSENSE3 = VDD
MR
MR = 0 V,
SENSEn
VSENSE1,2,3 = 0 V
V
0.4
0.4
V
V
1.2
1.25
1.29
1.6
1.68
1.73
2.8
2.93
3.02
2
10
30
2
15
40
3
SENSE1
UNIT
0.2
MR = 0.7 × VDD,
VDD = 6 V
VSENSE1 = VDD = 6 V
MAX
VDD– 0.4V
IOL = 2 mA
IOL = 3 mA
IOL = 20 µA
VSENSE3
VIT–
MIN
VDD– 0.2V
VDD– 0.4V
30
60
–130
–180
5
8
6
9
–430
–600
–1
VDD = 6 V
–1
V
mV
µA
A
1
1
40
µA
A
µΑ
Input capacitance
VI = 0 V to VDD
10
pF
NOTES: 2. The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 µF) should be placed close to the supply terminals.
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TPS3307-18-Q1
TRIPLE PROCESSOR SUPERVISORS
SGLS136 – NOVEMBER 2002
timing requirements at VDD = 2 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
tw
Pulse width
SENSEn
MR
TEST CONDITIONS
VSENSEnL = VIT– –0.2 V,
VIH = 0.7 × VDD,
VSENSEnH = VIT+ +0.2 V
VIL = 0.3 × VDD
MIN
TYP
6
10
MAX
UNIT
µs
100
150
ns
switching characteristics at VDD = 2 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
td
Delay time
tPHL
Propagation (delay) time,
high-to-low level output
MR to RESET
MR to RESET
tPLH
Propagation (delay) time,
low-to-high level output
MR to RESET
MR to RESET
tPHL
Propagation (delay) time,
high-to-low level output
SENSEn to RESET
tPLH
Propagation (delay) time,
low-to-high level output
SENSEn to RESET
6
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI(SENSEn) ≥ VIT+ + 0.2 V,
MR ≥ 0.7 × VDD, See timing diagram
140
200
280
ms
200
600
ns
1
5
µss
VI(SENSEn) ≥ VIT+ +0.2 V,
VIH = 0.7 × VDD, VIL = 0.3 × VDD
VIH = VIT+ +0.2 V, VIL = VIT– –0.2
0.2 V,
MR ≥ 0.7 × VDD
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TPS3307-18-Q1
TRIPLE PROCESSOR SUPERVISORS
SGLS136 – NOVEMBER 2002
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
NORMALIZED SENSE THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE AT VDD
18
1.005
VDD = 2 V
MR = Open
1.004
16
14
1.003
12
I DD – Supply Current – µ A
Normalized Input Threshold Voltage – VIT(TA), VIT(25 °C)
TYPICAL CHARACTERISTICS
1.002
1.001
1
0.999
0.998
0.997
TPS3307–33
10
8
6
4
2
0
–2
–4
SENSEn = VDD
MR = Open
TA = 25°C
–6
0.996
0.995
–40
60
–15
10
35
TA – Free-Air Temperature – °C
–8
–10
–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
85
VDD – Supply Voltage – V
Figure 3
Figure 2
INPUT CURRENT
vs
INPUT VOLTAGE AT MR
MINIMUM PULSE DURATION AT SENSE
vs
THRESHOLD OVERDRIVE
100
tw – Minimum Pulse Duration at Vsense – µ s
0
10
VDD = 6 V
TA = 25°C
I I – Input Current – µ A
–100
–200
–300
–400
–500
–600
–700
–800
–900
–1 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
VI – Input Voltage at MR – V
VDD = 6 V
MR = Open
9
8
7
6
5
4
3
2
1
0
0
100 200 300 400 500 600 700 800 900 1000
SENSE – Threshold Overdrive – mV
Figure 4
Figure 5
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TPS3307-18-Q1
TRIPLE PROCESSOR SUPERVISORS
SGLS136 – NOVEMBER 2002
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
2.5
6.5
VDD = 6 V
MR = Open
6
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
VDD = 2 V
MR = Open
2
1.5
–40°C
1
85°C
0.5
5.5
5
4.5
4
–40°C
3.5
3
85°C
2.5
2
1.5
1
0.5
0
0
0 –0.5 –1 –1.5 –2 –2.5 –3 –3.5 –4 –4.5 –5 –5.5 –6
IOH – High-Level Output Current – mA
0
–5
Figure 6
Figure 7
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
2.5
6.5
VDD = 2 V
MR = Open
2
1.5
1
VDD = 6 V
MR = Open
6
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
–10 –15 –20 –25 –30 –35 –40 –45 –50
IOH – High-Level Output Current – mA
85°C
0.5
–40°C
5.5
5
4.5
4
3.5
3
85°C
2.5
2
1.5
–40°C
1
0.5
0
0
0.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
IOL – Low-Level Output Current – mA
1
6
0
0
5
Figure 8
8
10 15 20 25 30 35 40 45 50 55 60
IOL – Low-Level Output Current – mA
Figure 9
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TPS3307-18-Q1
TRIPLE PROCESSOR SUPERVISORS
SGLS136 – NOVEMBER 2002
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–ā8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
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9
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TPS3307-18QDRQ1
ACTIVE
SOIC
D
Pins Package Eco Plan (2)
Qty
8
2500
None
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-1-220C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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