ICS448-16 Networking Clock Synthesizer Description Features The ICS448-16 generates four high-quality, high-frequency clock outputs. It is designed to replace multiple crystals and crystal oscillators in networking applications. Using ICS’ patented Phase-Locked Loop (PLL) techniques, the device runs from a 25 MHz crystal or clock input. • • • • • • Packaged in 16-pin TSSOP Replaces multiple crystals and oscillators Input crystal or clock frequency of 25 MHz Zero ppm frequency synthesis error Fixed output frequencies of 25 MHz and 48 MHz Selectable output frequencies of 24 MHz, 48 MHz, 50 MHz and 66.6666 MHz • Duty cycle of 45/55 • Operating voltage of 3.3 V • Advanced, low power CMOS process Block Diagram VDD 3 SEL X1 Crystal Oscillator/ Clock Buffer 25 MHz clock or crystal input X2 CLK1 PLL2 CLK2 PLL3 48M 25M 4 External capacitors may be required. PDTS (all outputs and PLLs) GND 1 MDS 448-16 E I n t e gra te d C i r c u i t S y s t e m s PLL1 ● 5 25 Race Stre et, San Jo se, CA 9 5126 Revision 031605 ● te l (40 8) 2 97-12 01 ● w w w. i c st . c o m ICS448-16 Networking Clock Synthesizer Pin Assignment Output Select Table (MHz) X1 1 16 X2 GND 2 15 VDD S0 3 14 PDTS CLK1 4 13 S1 VDD 5 12 VDD GND 6 11 GND 48M 7 10 25M CLK2 8 9 VDD S1 S0 CLK1 CLK2 0 0 50 48 0 1 66.6666 48 1 0 50 24 1 1 66.6666 24 16-pin (173 mil) TSSOP Pin Descriptions Pin Number Pin Name Pin Type 1 X1 XI 2 GND Power Connect to ground. 3 S0 Input Select pin 0. Internal pull-up resistor. 4 CLK1 Output Selectable output clock. See table above. Weak internal pull-down when tri-state. 5 VDD Power Connect to voltage supply. 6 GND Power Connect to ground. 7 48M Output 48 MHz output clock. Weak internal pull-down when tri-state. 8 CLK2 Output Selectable output clock. See table above. Weak internal pull-down when tri-state. 9 VDD Power Connect to voltage supply. 10 25M Output 25 MHz output clock. Weak internal pull-down when tri-state. 11 GND Power Connect to ground. 12 VDD Power Connect to voltage supply. 13 S1 Input Select pin 1. Internal pull-up resistor. 14 PDTS Input Power down tri-state. Powers down entire chip and tri-states outputs when low. Internal pull-up resistor. 15 VDD Power Connect to voltage supply. 16 X2 XO Crystal input. Connect this pin to a crystal or external clock source. Crystal output. Connect this pin to a crystal. Float for clock input. 2 MDS 448-16 E In te grated Circuit Systems Pin Description ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 031605 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS448-16 Networking Clock Synthesizer External Components PCB Layout Recommendations Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS448-16 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between each VDD and the PCB ground plane. Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS448-16. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20. 3 MDS 448-16 E In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 031605 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS448-16 Networking Clock Synthesizer Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS448-16. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 240°C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Typ. Max. Units +70 °C +3.465 V 0 Power Supply Voltage (measured in respect to GND) +3.135 +3.3 DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70°C Parameter Symbol Conditions Min. Typ. Max. Units 3.135 3.3 3.465 V Operating Voltatge VDD Supply Current IDD No load, PDTS=1 30 mA IDDPD No load, PDTS=0 50 µA Power Down Current Input High Voltage VIH Input Low Voltage VIL Output High Voltage VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA Short Circuit Current IOS Clock outputs Input Capacitance, Inputs 2 V 0.8 0.4 V V ±70 mA CIN 5 pF Nominal Output Impedance ZOUT 20 Ω Internal Pull-down Resistor RPD Clock outputs 500 kΩ Internal Pull-up Resistor RPU S1, S0, PDTS pins 360 kΩ 4 MDS 448-16 E In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 031605 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS448-16 Networking Clock Synthesizer AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70°C Parameter Symbol Input Frequency fIN Output Rise Time tOR Output Fall Time tOF Conditions Min. Typ. Max. Units 25 MHz 20% to 80%, Note 1 1 ns 80% to 20%, Note 1 1 ns Output Clock Duty Cycle at VDD/2, Note 1 Absolute Clock Period Jitter Note 1 Frequency Synthesis Error All clock outputs 45 Startup Time 50 55 % ±150 ps 0 ppm 1 2 ms Output Enable Time tOE PDTS high to output locked to ±1% 20 µs Output Disable Time tOD PDTS low to tri-state 2 ns Note 1: Measured with a 15 pF load. Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Min. Typ. Max. Units θJA Still air 78 °C/W θJA 1 m/s air flow 70 °C/W θJA 3 m/s air flow 68 °C/W 37 °C/W θJC Marking Diagram 16 9 448R-16 ###### YYWW 1 8 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 5 MDS 448-16 E In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 031605 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS448-16 Networking Clock Synthesizer Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol Index Area E1 E IN D EX AR EA 1 E A A1 A2 b C D E E1 e L α aaa H 2 Pin 1 DD A 2 Min Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 A A 1 c A -C - a c e e b b S E A T IN G P LA N E L L aaa C Ordering Information Part / Order Number ICS448G-16 ICS448G-16T Marking Shipping Packaging Package Temperature See page 5 Tubes Tape and Reel 16-pin TSSOP 16-pin TSSOP 0 to +70° C 0 to +70° C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 6 MDS 448-16 E In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 031605 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS448-16 Networking Clock Synthesizer Revision History Rev. Originator Date Description of Change C P.Griffith 09/23/04 Added “weak internal pull-down when tri-state” to pins 4 and 8; removed “Ambient Operating Temperture” from Max Ratings; removed “Operating Voltage” from DC chars; updated Supply/PowerDown current and internal pul-down resistor values in DC chars; updated Output rise/fall and enable/disable times and Startup time from AC chars. D R. Wei 10/19/04 Changed package designator on Part Number Ordering info from “R” to “G”. E P.Griffith 03/16/05 Released to Final and from custom to standard, general purpose device. 7 MDS 448-16 E In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 031605 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m