PRELIMINARY INFORMATION ICS348-22 Quad PLL Field Programmable VersaClock Synthesizer Description Features The ICS348-22 field programmable clock synthesizer generates up to 9 high-quality, high-frequency clock outputs including multiple reference clocks from a low frequency crystal or clock input. The ICS348-22 has four independent on-chip PLLs and is designed to replace crystals and crystal oscillators in most electronic systems. • • • • • • • • • • TM Using ICS’ VersaClock software to configure PLLs and outputs, the ICS348-22 contains a One-Time Programmable (OTP) ROM to allow field programmability. Programming features include eight selectable configuration registers, up to two sets of four low-skew outputs. Packaged as 20-pin SSOP (QSOP) Eight addressable registers Replaces multiple crystals and oscillators Output frequencies up to 189 MHz at 3.3 V Input crystal frequency of 25 MHz Up to nine reference outputs Up to two sets of four low-skew outputs Operating voltages of 3.3 V Advanced, low power CMOS process Available in Pb (lead) free packaging Using Phase-Locked Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. Block Diagram VDD S2:S0 3 3 CLK1 PLL1 OTP ROM with PLL Values CLK2 PLL2 CLK3 Divide Logic and Output Enable Control PLL3 25 MHz crystal input CLK4 CLK5 CLK6 CLK7 PLL4 X1 CLK8 Crystal Oscillator CLK9 X2 GND External capacitors are required with a crystal input. PDTS 1 MDS 348-22 A Integrated Circuit Systems, Inc. 2 ● 525 Race Street, San Jose, CA 95126 Revision 120704 ● tel (408) 297-1201 ● www.icst.com PRELIMINARY INFORMATION ICS348-22 Quad PLL Field Programmable VersaClock Synthesizer Pin Assignment X1 1 20 X2 S0 2 19 VDD S1 3 18 PDTS CLK9 4 17 S2 VDD 5 16 VDD GND 6 15 GND CLK1 7 14 CLK5 CLK2 8 13 CLK6 CLK3 9 12 CLK7 CLK4 10 11 CLK8 20-pin (150 mil) SSOP (QSOP) Output Configuration Table S2 S1 S0 Outputs 0 0 0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz 0 0 1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz 0 1 0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz 0 1 1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz 1 0 0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz 1 0 1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz 1 1 0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz 1 1 1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=OFF, CLK8=189 MHz, CLK9=127 MHz 2 MDS 348-22 A Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 120704 ● tel (408) 297-1201 ● www.icst.com PRELIMINARY INFORMATION ICS348-22 Quad PLL Field Programmable VersaClock Synthesizer Pin Descriptions Pin Number Pin Name Pin Type 1 X1 XI 2 S0 Input Pin Description Crystal Input. Connect this pin to a 25 MHz crystal. Select pin 0. Internal pull-up resistor. 3 S1 Input 4 CLK9 Output 5 VDD Power 127 MHz output clock. Weak internal pull-down when tri-state. Connect to +3.3 V. 6 GND Power Connect to ground. 7 CLK1 Output 127 MHz output clock. Weak internal pull-down when tri-state. 8 CLK2 Output 127 MHz output clock. Weak internal pull-down when tri-state. 9 CLK3 Output 127 MHz output clock. Weak internal pull-down when tri-state. 10 CLK4 Output 127 MHz output clock. Weak internal pull-down when tri-state. 11 CLK8 Output 189 MHz output clock. Weak internal pull-down when tri-state. 12 CLK7 Output 187 MHz output clock. Weak internal pull-down when tri-state. 13 CLK6 Output 187 MHz output clock. Weak internal pull-down when tri-state. 14 CLK5 Output 127 MHz output clock. Weak internal pull-down when tri-state. 15 GND Power 16 VDD Power Connect to ground. Connect to +3.3 V. 17 S2 Input Select pin 2. Internal pull-up resistor. 18 PDTS Input 19 VDD Power 20 X2 XO Power down tri-state. Powers down entire chip and tri-states clock outputs when low. Internal pull-up resistor. Connect to +3.3 V. Crystal Output. Connect this pin to a fundamental crystal. Float for clock input. 3 MDS 348-22 A Integrated Circuit Systems, Inc. Select pin 1. Internal pull-up resistor. ● 525 Race Street, San Jose, CA 95126 Revision 120704 ● tel (408) 297-1201 ● www.icst.com PRELIMINARY INFORMATION ICS348-22 Quad PLL Field Programmable VersaClock Synthesizer External Components Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Decoupling Capacitors As with any high-performance mixed-signal IC, the ICS348-22 must be isolated from system power supply noise to perform optimally. spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33Ω series termination resistor, if needed, should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers ICS348 Configuration Capabilities Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. The architecture of the ICS348-22 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. Crystal Load Capacitors The frequency multiplier PLL provides a high degree of precision. The M/N values (the multiplier/divide values available to generate the target VCO frequency) can be set within the range of M = 1 to 2048 and N = 1 to 1024. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum Each output frequency can be represented as: OutputFreq = REFFreq -------------------------------------OutputDivide ----⋅M N ICS VersaClock Software ICS applies years of PLL optimization experience into a user friendly software that accepts the user’s target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. The user does not need to have prior PLL experience or determine the optimal VCO frequency to support multiple output frequencies. VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate output accuracy, performance trade-off scenarios in seconds. 4 MDS 348-22 A Integrated Circuit Systems, Inc. The ICS348-22 also provides separate output divide values, from 2 through 20, to allow the two output clock banks to support widely differing frequency values from the same PLL. ● 525 Race Street, San Jose, CA 95126 Revision 120704 ● tel (408) 297-1201 ● www.icst.com PRELIMINARY INFORMATION ICS348-22 Quad PLL Field Programmable VersaClock Synthesizer Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS348-22. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Parameter Condition Min. Supply Voltage, VDD Referenced to GND Inputs Referenced to GND Clock Outputs Referenced to GND Storage Temperature Soldering Temperature Typ. Max. Units 7 V -0.5 VDD+0.5 V -0.5 VDD+0.5 V -65 150 °C 260 °C 125 °C Max 10 seconds Junction Temperature Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Typ. 0 Power Supply Voltage (measured in respect to GND) +3.15 +3.3 Power Supply Ramp Time Units +70 °C +3.45 V 4 ms 5 MDS 348-22 A Integrated Circuit Systems, Inc. Max. ● 525 Race Street, San Jose, CA 95126 Revision 120704 ● tel (408) 297-1201 ● www.icst.com PRELIMINARY INFORMATION ICS348-22 Quad PLL Field Programmable VersaClock Synthesizer DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70°C Parameter Symbol Operating Voltage Conditions Min. VDD Typ. Max. Units 3.45 V 3.15 Configuration Dependent - See VersaClockTM Estimates Operating Supply Current Input High Voltage IDD mA Nine 33.3333 MHz outs, PDTS = 1, no load, Note 1 23 mA 20 µA V Input High Voltage VIH PDTS = 0, no load S2:S0 Input Low Voltage VIL S2:S0 Input High Voltage, PDTS VIH Input Low Voltage, PDTS VIL Input High Voltage VIH ICLK Input Low Voltage VIL ICLK Output High Voltage (CMOS High) VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA Short Circuit Current IOS ±70 mA Nominal Output Impedance ZO 20 Ω 2 0.4 V VDD-0.5 V 0.4 V VDD/2+1 V VDD/2-1 V 0.4 V Internal Pull-up Resistor RPUS S2:S0, PDTS 250 kΩ Internal Pull-down Resistor RPD CLK outputs 525 kΩ Input Capacitance CIN Inputs 4 pF Note 1: Example with 25 MHz crystal input with nine outputs of 33.3 MHz, no load, and VDD = 3.3 V. 6 MDS 348-22 A Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 120704 ● tel (408) 297-1201 ● www.icst.com PRELIMINARY INFORMATION ICS348-22 Quad PLL Field Programmable VersaClock Synthesizer AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C Parameter Symbol Input Frequency Conditions FIN Min. Fundamental Crystal Output Frequency Typ. Max. Units 25 VDD=3.3 V MHz 0.25 189 MHz Output Rise Time tOR 20% to 80%, Note 1 1 ns Output Fall Time tOF 80% to 20%, Note 1 1 ns Duty Cycle Note 2 Power-up time PLL lock-time from power-up, Note 3 One Sigma Clock Period Jitter Maximum Absolute Jitter tja Pin-to-Pin Skew 40 49-51 60 % 3 10 ms PDTS goes high until stable CLK output, Note 3 0.2 2 ms Configuration Dependent 50 ps Deviation from Mean. Configuration Dependent +200 ps Low Skew Outputs -250 250 ps Note 1: Measured with 15 pF load. Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%. Note 3: ICS test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS transition high on select address change. Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 135 °C/W θJA 1 m/s air flow 93 °C/W θJA 3 m/s air flow 78 °C/W Thermal Resistance Junction to Case θJC 60 °C/W 7 MDS 348-22 A Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 120704 ● tel (408) 297-1201 ● www.icst.com PRELIMINARY INFORMATION ICS348-22 Quad PLL Field Programmable VersaClock Synthesizer Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Wide Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 20 Symbol E1 E INDEX AREA 1 2 D A A2 Min A A1 A2 b c D E E1 e L α aaa Max 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 .635 Basic 0.40 1.27 0° 8° -0.10 Inches Min Max 0.053 0.069 0.004 0.010 -0.059 0.008 0.012 0.007 0.010 0.337 0.344 0.228 0.244 0.150 0.157 .025 Basic 0.016 0.050 0° 8° -0.004 A1 c -Ce SEATING PLANE b L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICS348R-22 ICS348R-22 Tubes 20-pin SSOP 0 to +70° C ICS348R-22T ICS348R-22 Tape and Reel 20-pin SSOP 0 to +70° C ICS348R-22LF ICS348R22LF Tubes 20-pin SSOP 0 to +70° C ICS348R-22LFT ICS348R22LF Tape and Reel 20-pin SSOP 0 to +70° C “LF” denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8 MDS 348-22 A Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 120704 ● tel (408) 297-1201 ● www.icst.com