ICS650-44 P R E L I M I N A R Y I N F O R M AT I O N Spread Spectrum Clock Synthesizer Description Features The ICS650-44 is a spread spectrum clock synthesizer intended for video projector and digital TV applications. It generates three copies of an EMI optimized 50 MHz clock signal (EMI peak reduction of 7 to 14 dB on 3rd through 19th harmonics) through the use of Spread Spectrum techniques from a 25 MHz crystal or clock input. The modulation rate is 50 kHz. • • • • • • • • • Packaged in 16-pin TSSOP (173 mil) Supply voltages: VDD = 3.3 V, VDDO = 2.5 V Peak-to-peak jitter: ±125 ps typ Output duty cycle 45/55% (worst case) 25 MHz crystal or reference clock input Zero (0) ppm frequency error on all output clocks Advanced, low-power CMOS process Industrial temperature range (-40 to +85°C) Available in Pb (lead) free package Block Diagram VDD VDDO 3 25 MHz crystal or clock input 50M X1/CLKIN Crystal OSC X2 PLL with Spread Spectrum External capacitors are required with a crystal input. 50M Control Logic FS3:0 50M GND 2 PDTS 1 MDS 650-44 C Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 080305 ● tel (408) 297-1201 ● www.icst.com P R E L I M I N A R Y I N F O R M AT I O N ICS650-44 Spread Spectrum Clock Synthesizer Pin Assignment Spread Spectrum and Output Configuration Table X1/ CLKIN 1 16 X2 FS0 2 15 VDD FS1 3 14 PDTS 0 50M 4 13 FS2 VDD 5 12 VDD GND 6 11 GND FS3 7 10 VDDO 50M 8 9 FS3 FS2 0 0 50M 16-pin ( 173 mil) TSSOP FS0 0 Spread Type Center SS Out ±0.25 0 0 1 Center ±0.50 0 0 1 0 Center ±0.75 0 0 1 1 Center ±1.00 0 1 0 0 Center ±1.25 0 1 0 1 Center ±1.50 0 1 1 0 Center ±1.75 0 1 1 1 Center ±2.00 1 0 0 0 Down -0.5 1 0 0 1 Down -0.75 1 0 1 0 Down -1.0 1 0 1 1 Down -1.25 1 1 0 0 Down -1.5 1 1 0 1 Down -1.75 1 1 1 0 Down -2.0 1 1 1 1 Off Off 2 MDS 650-44 C Integrated Circuit Systems, Inc. FS1 0 ● 525 Race Street, San Jose, CA 95126 Revision 080305 ● tel (408) 297-1201 ● www.icst.com P R E L I M I N A R Y I N F O R M AT I O N ICS650-44 Spread Spectrum Clock Synthesizer Pin Descriptions Pin Number 1 X1/CLKIN Pin Type Input 2 3 4 5 6 7 8 9 10 11 12 13 14 FS0 FS1 50M VDD GND FS3 50M 50M VDDO GND VDD FS2 PDTS Input Input Output Power Power Input Output Output Power Power Power Input Input 15 16 VDD X2 Power Output Pin Name Pin Description Crystal input. Connect this pin to a 25 MHz crystal or external input clock. Select pin 0. Internal pull-up resistor. See table on page 2. Select pin 1. Internal pull-up resistor. See table on page 2. Spread Spectrum output. Weak internal pull-down when tri-stated. Connect to +3.3 V. Connect to ground. Select pin 3. Internal pull-up resistor. See table on page 2. Spread Spectrum output. Weak internal pull-down when tri-stated. Spread Spectrum output. Weak internal pull-down when tri-stated. Connect to +2.5 V. Connect to ground. Connect to +3.3 V. Select pin 2. Internal pull-up resistor. See table on page 2. Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up. Connect to +3.3 V. Crystal Output. Connect this pin to a 25 MHz crystal. Do not connect if clock input is used. External Components Decoupling Capacitor Crystal Load Capacitors As with any high-performance mixed-signal IC, the ICS650-44 must be isolated from system power supply noise to perform optimally. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. A decoupling capacitor of 0.01µF must be connected between each VDD and the PCB ground plane. Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. 3 MDS 650-44 C Integrated Circuit Systems, Inc. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20. ● 525 Race Street, San Jose, CA 95126 Revision 080305 ● tel (408) 297-1201 ● www.icst.com P R E L I M I N A R Y I N F O R M AT I O N ICS650-44 Spread Spectrum Clock Synthesizer PCB Layout Recommendations should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces 3) To minimize EMI, the 33Ω series termination resistor should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS650-44. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS650-44. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 5V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature (max. of 10 seconds) 260°C Recommended Operation Conditions Parameter Min. Typ. Max. Units -40 – +85 °C Power Supply Voltage (VDD, with respect to GND) +3.135 +3.3 +3.465 V Power Supply Voltage (VDDO) +2.375 +2.5 +2.625 V 4 ms Ambient Operating Temperature Power Supply Ramp Time, Figure 4 4 MDS 650-44 C Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 080305 ● tel (408) 297-1201 ● www.icst.com P R E L I M I N A R Y I N F O R M AT I O N ICS650-44 Spread Spectrum Clock Synthesizer DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, VDDO = 2.5 V ±5% , Ambient Temperature -40 to +85°C Parameter Symbol Conditions Min. Typ. Max. Units no load 27 mA PDTS = 0, no load 40 uA no load 4 mA PDTS = 0, no load 1 uA IDD Operating Supply Current IDDO Input High Voltage VIH FS3:0, PDTS Input Low Voltage VIL FS3:0, PDTS Input High Voltage VIH X1/CLKIN Input Low Voltage VIL X1/CLKIN Output High Voltage VOH IOH = -4 mA Output Low Voltage VOL IOL = 4 mA Short Circuit Current IOS ±50 mA Nominal Output Impedance ZO 20 Ω Internal Pull-up Resistor RPU 360 kΩ 1 uA 900 kΩ 4 pF Input Leakage Current II 0.7 x VDD CLK outputs Input Capacitance CIN Inputs 1.8 ● 525 Race Street, San Jose, CA 95126 V V 0.6 5 MDS 650-44 C V V 0.3 x VDD FS3:0, PDTS, VIN=VDD RPD V 0.8 FS3:0, PDTS Internal Pull-down Resistor Integrated Circuit Systems, Inc. 2 V Revision 080305 ● tel (408) 297-1201 ● www.icst.com P R E L I M I N A R Y I N F O R M AT I O N ICS650-44 Spread Spectrum Clock Synthesizer AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, VDDO = 2.5 V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Input Frequency Conditions FIN Min. Crystal or clock input Spread Spectrum Modulation Frequency t2/t1 Duty Cycle At VDD/2, Note 1 and Figures 1 and 2 45 Typ. Max. Units 25 MHz 50 kHz 50 55 % Output Fall Time t3 80% to 20%, Note 1 and Figures 1 & 3 1.5 ns Output Rise Time t4 20% to 80%, Note 1 and Figures 1 & 3 1.5 ns Note 1 30 ps ps One Sigma Clock Period Jitter Absolute Jitter, Peak-to-Peak tja Deviation from mean, Note1 & Figures 1 and 6 ±125 Output Enable Time tEN PDTS high to PLL locked to within 1% of final value, Figure 5 2.5 Output Disable Time tDIS PDTS low to tri-state, Figure 5 20 ns ±180 ps Output-to-Output Skew PLL lock-time from power-up to 1% of final value, Figure 4 tP Power-up Time 5 6 10 ms ms Note 1: Measured with 5 pF load. 6 MDS 650-44 C Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 080305 ● tel (408) 297-1201 ● www.icst.com P R E L I M I N A R Y I N F O R M AT I O N ICS650-44 Spread Spectrum Clock Synthesizer Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 78 °C/W θJA 1 m/s air flow 70 °C/W θJA 3 m/s air flow 68 °C/W Thermal Resistance Junction to Case θJC 37 °C/W Marking Diagram 16 9 650GI-44 ###### YYWW 1 8 Marking Diagram (Pb free) 16 9 650GI44L ###### YYWW 1 8 Notes: 1. ###### is the lot number. 2. YYWW is the last two digits of the year and the week number that the part was assembled. 3. “I” designates industrial temperature range. 4. “L” designates Pb (lead) free package. 5. Bottom marking: (origin) Origin = country of origin of not USA. 7 MDS 650-44 C Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 080305 ● tel (408) 297-1201 ● www.icst.com P R E L I M I N A R Y I N F O R M AT I O N ICS650-44 Spread Spectrum Clock Synthesizer Timing Diagrams VDDs t1 Outputs 0.01µF t2 VDDO C LOAD DUT 50% of VD D O C lo c k 0V GND Figure 1: Test and Measurement Setup Figure 2: Duty Cycle Definitions Power Up Tim e PLL Locked VDD t4 t3 VCO Ram p Tim e VDDO 80% of VDDO 0V VDD 20% of VDDO 0V Clock Output 0V 0 ms Figure 3: Rise and Fall Time Definitions PDTS 10 m s Figure 4: Power Up and PLL Lock Timing 1 .2 5 V 1.25 V 1% 4 ms t D IS t EN C LK O utputs VOH Mean value Absolute jitter (p - p) 0V Figure 5: PDTS to Stable Clock Output Timing Figure 6: Short Term Jitter Definition 8 MDS 650-44 C Integrated Circuit Systems, Inc. tJA ● 525 Race Street, San Jose, CA 95126 Revision 080305 ● tel (408) 297-1201 ● www.icst.com P R E L I M I N A R Y I N F O R M AT I O N ICS650-44 Spread Spectrum Clock Synthesizer Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E1 Min A A1 A2 b C D E E1 e L α aaa E INDEX AREA 1 2 D Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 A A2 A1 c -Ce SEATING PLANE b L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICS650GI-44 see page 7 Tubes 16-pin TSSOP -40 to +85° C ICS650GI-44T ICS650GI-44LF Tape and Reel 16-pin TSSOP -40 to +85° C Tubes 16-pin TSSOP -40 to +85° C Tape and Reel 16-pin TSSOP -40 to +85° C see page 7 ICS650GI-44LFT Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 9 MDS 650-44 C Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 080305 ● tel (408) 297-1201 ● www.icst.com P R E L I M I N A R Y I N F O R M AT I O N ICS650-44 Spread Spectrum Clock Synthesizer Revision History Rev. Originator Date Description of Change - P. Griffith 05/13/05 New proposal. A P. Griffith 05/24/05 Move from Advance (proposal) to Preliminary. Added ICS part number and LF. B P. Griffith 06/14/05 Added “Output-to-Output skew” psec of ±180 ps. C P. Griffith 08/03/05 Removed references to SS_EN. 10 MDS 650-44 C Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 080305 ● tel (408) 297-1201 ● www.icst.com