ICS8304I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8304I is a low skew, 1-to-4 Fanout Buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8304I is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output operating supply modes (VDDO). Guaranteed output and part-to-part skew characteristics make the ICS8304I ideal for those clock distribution applications demanding well defined performance and repeatability. • 4 LVCMOS / LVTTL outputs ,&6 • LVCMOS clock input • CLK can accept the following input levels: LVCMOS, LVTTL • Maximum output frequency: 166MHz • Output skew: 60ps (maximum) • Part-to-part skew: 650ps (maximum) • Small 8 lead SOIC package saves board space • 3.3V input, outputs may be either 3.3V or 2.5V supply modes • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT Q0 VDDO VDD CLK GND Q1 1 2 3 4 8 7 6 5 Q3 Q2 Q1 Q0 CLK ICS8304I Q2 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View Q3 8304AMI www.icst.com/products/hiperclocks.html 1 REV. B APRIL 4, 2002 ICS8304I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDO Power Type Description Output supply pin. Connect to 3.3V or 2.5V. 2 VDD Power 3 CLK Input 4 GND Power Power supply ground. Connect to ground. 5 Q0 Output Single clock output. LVCMOS / LVTTL interface levels. 6 Q1 Output Single clock output. LVCMOS / LVTTL interface levels. 7 Q2 Output Single clock output. LVCMOS / LVTTL interface levels. 8 Q3 Output Single clock output. LVCMOS / LVTTL interface levels. Positive supply pin. Connect to 3.3V. Pulldown LVCMOS / LVTTL clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Test Conditions Minimum Typical Maximum Units 4 pF 15 pF RPULLUP Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ ROUT Output Impedance 7 Ω C PD 8304AMI VDD, VDDO = 3.465V www.icst.com/products/hiperclocks.html 2 REV. B APRIL 4, 2002 ICS8304I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDDx Inputs, VI 4.6V -0.5V to VDD+ 0.5V Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG -0.5V to VDDO + 0.5V 112.7°C/W (0 lfpm) -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VDD VDDO IDD IDDO Test Conditions Minimum Typical Maximum Units Power Supply Voltage 3.135 3.3 3.465 V Output Power Supply Voltage 3.135 3.3 3.465 V Power Supply Current 18 mA Output Supply Current 11 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage Test Conditions Minimum 2 Maximum Units VDD + 0.3 V VIL Input Low Voltage IIH Input High Current VDD = VIN = 3.465V IIL Input Low Current VDD = 3.465V, VIN = 0V -5 µA Refer to NOTE 1 2.6 V VOH Output High Voltage IOH = -16mA 2.9 V IOH = -100uA 3 VOL Output Low Voltage -0.3 Typical 1.3 V 150 µA V Refer to NOTE 1 0.5 V IOL = 16mA 0.25 V IOL = 100uA 0.15 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Section, "3.3V Output Load Test Circuit". 8304AMI www.icst.com/products/hiperclocks.html 3 REV. B APRIL 4, 2002 ICS8304I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions fMAX Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 ƒ≤ 166MHz tsk(o) Output Skew; NOTE 2, 4 f = 133MHz tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 Minimum Typical Maximum Units 166 MHz 3.3 ns 50 ps 600 ps 2 tR Output Rise Time 30% to 70% 250 500 ps tF Output Fall Time 30% to 70% 250 500 ps 60 % odc Output Duty Cycle 40 All parameters measured at 166MHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Positive Supply Voltage Test Conditions 3.135 3.3 3.465 V 2.375 2.5 VDDO Output Supply Voltage 2.625 V IDD Power Supply Current 18 mA IDDO Output Supply Current 11 mA TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Maximum Units VIH Input High Voltage Test Conditions 2 VDD + 0.3 V VIL Input Low Voltage -0.3 1.3 V 150 µA IIH Input High Current VDD = VIN = 3.465V IIL Input Low Current VDD = 3.465V, VIN = 0V VOH Output High Voltage; NOTE 1 Minimum -5 µA 2.1 Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Section, "3.3V/2.5V Output Load Test Circuit". 8304AMI Typical www.icst.com/products/hiperclocks.html 4 V 0.5 V REV. B APRIL 4, 2002 ICS8304I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions fMAX Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 ƒ≤ 166MHz tsk(o) Output Skew; NOTE 2, 4 f = 133MHz tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR Output Rise Time 30% to 70% tF Output Fall Time 30% to 70% Minimum Typical 2.3 www.icst.com/products/hiperclocks.html 5 Units 166 MHz 3.7 ns 60 ps 650 ps 250 500 ps 250 500 ps 60 % odc Output Duty Cycle 40 All parameters measured at 166MHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8304AMI Maximum REV. B APRIL 4, 2002 ICS8304I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% SCOPE VDD, VDDO Qx LVCMOS GND -1.65V±5% 3.3V OUTPUT LOAD TEST CIRCUIT 2.05V±5% 1.25V±5% SCOPE V DD VDDO Qx LVCMOS GND -1.25V±5% 3.3V/2.5V OUTPUT LOAD TEST CIRCUIT 8304AMI www.icst.com/products/hiperclocks.html 6 REV. B APRIL 4, 2002 ICS8304I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER VDDO 2 Qx VDDO 2 Qy tsk(o) OUTPUT SKEW VDDO 2 PART 1 Qx VDDO 2 PART 2 Qy tsk(pp) PART-TO-PART SKEW 70% 70% 30% 30% Clock Inputs and Outputs t INPUT 8304AMI t R AND OUTPUT RISE AND F FALL TIME www.icst.com/products/hiperclocks.html 7 REV. B APRIL 4, 2002 ICS8304I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER V DD CLK 2 V DDO 2 Q0:Q3 t PD PROPAGATION DELAY V V DDO Q0 :Q3 DDO 2 2 t t t DDO 2 PW t odc = V PERIOD PW PERIOD tPW & tPERIOD 8304AMI www.icst.com/products/hiperclocks.html 8 REV. B APRIL 4, 2002 ICS8304I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER TABLE 5. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 112.7°C/W 200 500 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8304I is: 416 8304AMI www.icst.com/products/hiperclocks.html 9 REV. B APRIL 4, 2002 ICS8304I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER PACKAGE OUTLINE - SUFFIX M TABLE 6. PACKAGE DIMENSIONS - SUFFIX M SYMBOL Millimeters MINIMUN N MAXIMUM 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 e H 4.00 1.27 BASIC 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 8304AMI www.icst.com/products/hiperclocks.html 10 REV. B APRIL 4, 2002 ICS8304I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package ICS8304AMI 8304AMI 8 lead SOIC ICS8304AMIT 8304AMI 8 lead SOIC on Tape and Reel Count 96 per tube 2500 Temperature -40°C to 85°C -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8304AMI www.icst.com/products/hiperclocks.html 11 REV. B APRIL 4, 2002 ICS8304I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER REVISION HISTORY SHEET Rev B 8304AMI Table 3B Page 3 Description of Change LVCMOS/LVTTL DC Characteristics Table, added IOH and IOL Test Conditions to VOH and VOL rows. www.icst.com/products/hiperclocks.html 12 Date 4/4/02 REV. B APRIL 4, 2002