SEMICONDUCTOR KUSB50QN TECHNICAL DATA HIGH-SPEED USB2.0 DPDT SWITCH HIGH-SPEED(480Mbps) USB2.0 DPDT SWITCH F DESCRIPTION E The KUSB50QN is a High-Speed(480Mbps) USB2.0 signal switch. Configured as a double-pole double-throw (DPDT) switch, it is optimized for switching between 2 Hi-Speed sources or a Hi-Speed(480Mbps) and Full-Speed(12Mbps) source. Its wide Bandwidth (720MHz) is wide enough to pass High-Speed USB2.0 differential signals. Industry-leading advantages include a propagation delay of less than 250ps, resulting from its low channel resistance and low on capacitance. It is bidirectional and offers little or no attenuation of the High-Speed signal at the outputs. Its high channel-to-channel crosstalk rejection results in minimal noise interference. The switch is designed to minimize current consumption even when the control voltage applied to the S pin, is lower than the VCC. The KUSB50QN also offers over-voltage protection per the USB2.0 Specification. With the chip powered ON or OFF, all data I/O pins can withstand a short to Vbus(5.25V). CO.1 G B Pin 1 D H C A BOTTOM VIEW TOP VIEW J SIDE VIEW 1 K I SIDE VIEW 2 DIM A B C D E F G H I J K MILLIMETERS _ 0.05 1.80 + _ 0.05 1.40 + _ 0.05 0.20 + _ 0.10 0.40 + 0.20 REF 0.40 REF 0.80 REF _ 0.10 0.50 + 0.05 Max 0.20 REF _ 0.05 0.85 + QFN-10 FEATURES ・USB2.0 compliant (High-speed and Full-speed). ・Low On Resistance, 5.5Ω(Typ) @ VCC=3V . ・Channel On Capacitance, 6.5㎊(Typ) @ f=1㎒. ・Low Power Consumption (Max :1㎂) Marking : 10㎂Maximum ICCT over an Expanded Voltage Range (VIN=1.8V, VCC=4.3V). ・Wide-3dB bandwidth, >720MHz. ・High ESD Protection. :Data Pin ESD Rating : 8.0kV(HBM) Control Pin ESD Rating : 8.0kV(HBM) Power/GND ESD Rating : > 20kV(HBM) All pins ESD Rating : 300V(MM). ・Power Off protection U 2 0 A : When VCC =0V, D+/D -can tolerate up to 5.25V APPLICATIONS ・Routes signals for USB2.0 ・Differential Signal Data Routing ・Hand-held devices 2010. 2. 10 Revision No : 0 1/10 KUSB50QN Block Diagram 8 HSD1- OE HSD1+ Pin Configuration 7 6 HSD1+ D+ 5 HSD2+ VCC 9 4 HSD2- S 10 3 GND 2 HSD1D- D- D+ 1 HSD2+ HSD2- Top View S OE Control Truth Table S OE Diretion X HIGH Disconnect HIGH LOW D+, D- = HSD1x LOW LOW D+, D- = HSD2x Pin Descriptions PIN 1 NAME Function D+ Data Port Dx 2 D- Data Port 3 GND 4 HSD2- 5 HSD2+ Ground Data Port Data Port HSDnx 2010. 2. 10 6 HSD1- Data Port 7 HSD1+ Data Port 8 OE (OE-) 9 VCC 10 S Revision No : 0 Bus Switch Enable Control Supply Voltage Select Input Control 2/10 KUSB50QN Absolute Maximum Ratings CHARACTERISTIC SYMBOL RATING UNIT Supply Voltage VCC -0.5 ~ 4.6 V Control Port Input Voltage (S, OE-) VIN -0.5 ~ 4.6 V Switch Input Voltage (HSDnx, Dx) VSW HSDnx -0.5 ~ VCC+0.5 Dx @VCC>0 -0.5 ~ VCC+0.5 Dx @VCC=0 5.25 V Data Port Output Current IOD 120 mA Power Dissipation PD 0.5 W Operating Ambient Temperature Ta -40 ~ +85 ℃ Storage Temperature Range Tstg -65 ~ +150 ℃ DC Electrical Characteristics⑴ (VCC=3.0~4.3V, Ta = -40~85℃) PARAMETER SYMBOL VIH Input HIGH Voltage VIL Input LOW Voltage TEST CONDITIONS MIN TYP MAX UNITS VCC=4.3V 1.7 - - V VCC=3.0V 1.3 - - V VCC=4.3V - - 0.7 V VCC=3.0V - - 0.5 V - -0.7 -1.2 V Clamp Diode Voltage VIK VCC=Max, IIN=-18mA Control Input Leakage IIN VCC=Max, 0≤VIN≤VCC -1.0 - 1.0 μA OFF State Leakage IOZ VCC=VOE-=Max, 0≤VSW≤VCC -2.0 - 2.0 μA Power OFF Leakage Current (D+, D-) IOFF VCC=0V, 0≤VSW≤4.3V -2.0 - 2.0 μA Quiescent Supply Current ICC VCC=Max, VIN=0V or VCC - - 1.0 μA Increase in ICC per Control Voltage ICCT VCC=Max, VIN=1.8V - - 10.0 μA Switch ON Resistance RON VCC=Min, 0V≤VSW≤1.0V, ION=-40mA - 5.5 6.5 Ω ON Resistance Flatness RFLAT(ON) VCC=Min, 0V≤VSW≤1.0V, ION=-40mA - 1.5 - Ω VCC=Min, VSW=1.0V, ION=-40mA - 0.2 0.35 Ω ON Resistance Match from Center Port to any other port ΔRON Note(1) : All typical values are at VCC=3.3V(unless otherwise noted), Ta=25℃ Capacitance Characteristics⑴ (Ta =-40~85℃, f=1㎒) PARAMETER SYMBOL HSDnx, Dnx, Switch ON Capacitance CON HSDnx, Switch OFF Capacitance Control Pin Input Capacitance 2010. 2. 10 MIN TYP MAX VCC=3.3V, VOE-=0V - 6.5 - pF 6 COFF VCC=3.3V, VOE-=3.3V - 3.0 - pF 7 CIN VCC=0V - 3.6 - pF 7 Revision No : 0 TEST CONDITIONS UNITS FIGURE NO. 3/10 KUSB50QN AC Electrical Characteristics⑴ (Ta = -40~85℃) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS FIGURE NO. Propagation Delay(2) tPD VCC=3.3V, RL=50Ω, CL=5pF - 0.25 - ns Turn-On Time tON 3.0≤VCC≤3.6V, VSW=0.8V, RL=50Ω, CL=5pF - 13.0 30.0 ns Turn-Off Time tOFF 3.0≤VCC≤3.6V, VSW=0.8V, RL=50Ω, CL=5pF - 12.0 25.0 ns Break-Before-Make tBBM 3.0≤VCC≤3.6V, VSW=0.8V, RL=50Ω, CL=5pF 2.0 - 6.5 ns 11 -3dB Bandwidth BW 3.0≤VCC≤3.6V, RT=50Ω CL=0pF - 720 - CL=5pF - 550 - ㎒ 13 Off Isolation (Non-Adjacent) OIRR 3.0≤VCC≤3.6V, RT=50Ω, f=240㎒ - -30.0 - dB 14 XTALK 3.0≤VCC≤3.6V, RT=50Ω, f=240㎒ - -45.0 - dB 15 MIN TYP MAX Channel Crosstalk (Non-Adjacent) 9 10 Note(2) : Guaranteed by characterization. AC Electrical Characteristics For USB2.0 High-Speed Switching ⑴ (Ta = -40~85℃) PARAMETER SYMBOL Skew of Opposite Transitions of the Same Output(2) tSK(P) 3.0≤VCC≤3.6V, RL=50Ω, CL=5pF - 20 - ps Channel-to-Channel Skew(2) tSK(O) 3.0≤VCC≤3.6V, RL=50Ω, CL=5pF - 50 - ps 3.0≤VCC≤3.6V, RL=50Ω, CL=5pF tR=tF=500ps at 480Mbps - 200 - ps Total Jitter(2) 2010. 2. 10 tJ(2) TEST CONDITIONS Revision No : 0 UNITS FIGURE NO. 12 - 4/10 KUSB50QN Application Information VCC KUSB50QN HSD1+ USB2.0 Controller D+ HSD1- Set Top Box (STB) CPU or DSP Processor USB Connector D- DVR or Mass Storage Controller HSD2+ Control HSD2S OE 1.4 1.6 Fig. 1 Application Diagram 0.5 0.4 Differential Signal (V) 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.8 2.0 Time ( x 10-9)(s) Measurement Name Minimum Maximum Mean RMS STATUS Eye Diagram Test - - - - PASS Signal Rate (Mbps) 442.4563 527.4987 480.0518 481.5582 PASS - 16.56572 - PASS EOP Width (Bits) Rise Time (ns) 788.3502 2.399811 1.222390 1.304253 PASS Fall Time (ns) 798.1337 2.396142 1.214730 1.287723 PASS Consecutive Jitter Range -157.9ps to 139.6ps RMS Jitter 59.29ps PASS KJ Paired Jitter Range -135.6ps to 138.3ps RMS Jitter 53.00ps PASS JK Paired Jitter Range -110.1ps to 155.5ps RMS Jitter 49.48ps PASS Fig. 2 High-Speed Eye Diagram 2010. 2. 10 Revision No : 0 5/10 KUSB50QN 4.0 3.5 Differential Signal (V) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Time ( x 10-8)(s) Measurement Name Minimum Maximum Mean RMS STATUS Eye Diagram Test - - - - PASS Signal Rate (Mbps) 11.98705 12.02102 12.00205 12.00283 PASS Crossover Voltage 1.622501 1.735276 1.678898 - PASS - 167.017 - PASS EOP Width (Bits) Rise Time (ns) 7.2297 7.5460 7.3464 7.3472 PASS Fall Time (ns) 7.1852 7.6988 7.4212 7.4230 PASS Consecutive Jitter Range -188.3988ps to 140.1242ps RMS Jitter 91.71091ps PASS KJ Paired Jitter Range -178.1923ps to 110.7530ps RMS Jitter 137.6440ps PASS JK Paired Jitter Range -116.2675ps to 86.31155ps RMS Jitter 78.24693ps PASS Fig. 3 Full-Speed Eye Diagram 2010. 2. 10 Revision No : 0 6/10 KUSB50QN Test Diagram (Continued) VCC KUSB50QN HSDn VOUT D VIN RON = VON / ION VON = VIN -VOUT ION GND S VS VS = VIL or VIH GND GND Fig. 4 Switch On Resistance VCC KUSB50QN NC D IOZ or IOFF A IOFF = (VCC = 0V) VIN S OE- VS VOE- GND IOZ (VOE- =VCC) VS = VIL or VIH Each Data Ports is tested separately GND Fig. 5 OFF Leakage VCC VCC KUSB50QN KUSB50QN D D S Capacitance Meter VS = 0V or VCC Freq=1MHz Freq=1MHz HSDn VS = 0V or VCC HSDn GND Fig. 6 Channel On Capacitance 2010. 2. 10 Capacitance Meter Revision No : 0 S GND Fig. 7 Channel OFF Capacitance 7/10 KUSB50QN VCC KUSB50QN HSD1 or 2 VIN D+, D- HSD2 or 1 GND VS GND CL S OEVOE- 1. RL and CL are functions of application environment. VOUT RL 2. CL includes test jig and probe capacitance. GND GND GND Fig. 8 AC Test Circuit tRISE=500ps tFALL=500ps 800mV 90% 90% 50% Input : HSDn 400mV 50% 10% 10% VOH Output : D 50% VOL 50% tPHL tPLH Fig. 9 Propagation Delay Time tRISE=2.5ns tFALL=2.5ns VCC 90% VCC/2 Input : S, OEGND VOH Output : D VOL 90% VCC/2 10% 10% 90% 90% tON tOFF Fig. 10 Turn-On / Turn-Off Time 2010. 2. 10 Revision No : 0 8/10 KUSB50QN VCC KUSB50QN HSD1 or 2 VIN VCC VOUT D+, D- HSD2 or 1 GND S Control Input GND RL CL* GND GND Control Input 50% 0V tR=tF=2.5ns (10-90%) VOUT 0.9 VOUT tD GND *CL includes test jig and probe capacitance. Fig. 11 Break-Before-Make tFALL=500ps tRISE=500ps 800mV 90% Input : D tFALL=500ps tRISE=500ps 90% Input : HSDn 90% 50% Output1 : HSD1 50% 10% VOL 10% 10% 50% 50% tPHL1 tPLH1 VOH 50% VOL 10% 400mV VOH Output : D 50% VOH 800mV 400mV 90% 50% tPLH 50% Output2 : HSD2 tPHL 50% 50% VOL tPLH2 tPHL2 TSK(P) = tPHL - tPLH TSK(O) = tPHL1 - tPLH2 Pulse Skew, TSK(P) Output Skew, TSK(OUT) or tPHL1 - tPLH2 Fig. 12 Skew Tests 2010. 2. 10 Revision No : 0 9/10 KUSB50QN VCC KUSB50QN Network Analyzer RS D GND VS Signal Source VIN HSDn GND RT GND GND VOUT GND BW = 20Log(VOUT/VIN) RS and RT are functions of the application environment Signal Source Direction can be reversed Fig. 13 Bandwidth VCC KUSB50QN Network Analyzer RS D RT GND Signal Source VIN GND GND VS HSDn VOUT GND RT GND GND GND OIRR = 20Log(VOUT/VIN) RS and RT are functions of the application environment Signal Source Direction can be reversed Fig. 14 Channel OFF Isolation VCC KUSB50QN Network Analyzer HSD1+ (HSD2+) VS RS D-(NC) D+ GND Signal Source VIN GND RT GND GND GND HSD1(HSD2-) GND RT VOUT GND XTALK = 20Log(VOUT/VIN) RS and RT are functions of the application environment Signal Source Direction can be reversed Fig. 15 Non-adjacent Channel-to-Channel Crosstalk 2010. 2. 10 Revision No : 0 10/10