REG113 SBVS031D – MARCH 2001 – REVISED SEPTEMBER 2005 DMOS 400mA Low-Dropout Regulator FEATURES DESCRIPTION ● CAP-FREE DMOS TOPOLOGY: Ultra Low Dropout Voltage: 250mV typ at 400mA Output Capacitor not Required for Stability ● UP TO 500mA PEAK, TYPICAL ● FAST TRANSIENT RESPONSE ● VERY LOW NOISE: 28µVrms ● HIGH ACCURACY: ±1.5% max ● HIGH EFFICIENCY: IGND = 850µA at IOUT = 400mA Not Enabled: IGND = 0.01µA ● 2.5V, 2.85V, 3.0V, 3.3V, AND 5.0V OUTPUT VERSIONS ● OTHER OUTPUT VOLTAGES AVAILABLE UPON REQUEST ● FOLDBACK CURRENT LIMIT ● THERMAL PROTECTION ● SMALL SURFACE-MOUNT PACKAGES: SOT23-5 and MSOP-8 The REG113 is a family of low-noise, low-dropout linear regulators with low ground pin current. Its new DMOS topology provides significant improvement over previous designs, including low-dropout voltage (only 250mV typ at full load), and better transient performance. In addition, no output capacitor is required for stability, unlike conventional lowdropout regulators that are difficult to compensate and require expensive low ESR capacitors greater than 1µF. APPLICATIONS ● ● ● ● ● ● PORTABLE COMMUNICATION DEVICES BATTERY-POWERED EQUIPMENT PERSONAL DIGITAL ASSISTANTS MODEMS BAR-CODE SCANNERS BACKUP POWER SUPPLIES Typical ground pin current is only 850µA (at IOUT = 400mA) and drops to 10nA when not enabled. Unlike regulators with PNP pass devices, quiescent current remains relatively constant over load variations and under dropout conditions. The REG113 has very low output noise (typically 28µVrms for VOUT = 3.3V with CNR = 0.01µF), making it ideal for use in portable communications equipment. Accuracy is maintained over temperature, line, and load variations. Key parameters are tested over the specified temperature range (–40°C to +85°C). The REG113 is well protected—internal circuitry provides a current limit which protects the load from damage, furthermore, thermal protection circuitry keeps the chip from being damaged by excessive temperature. The REG113 is available in SOT23-5 and MSOP-8 packages. Enable VOUT VIN + 0.1µF NR(2) REG113 + COUT(1) GND NOTES: (1) Optional. (2) NR = Noise Reduction. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2001-2005, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) Supply Input Voltage, VIN ....................................................... –0.3V to 12V Enable Input Voltage, VEN ....................................................... –0.3V to VIN NR Pin Voltage, VNR ............................................................. –0.3V to 6.0V Output Short-Circuit Duration ...................................................... Indefinite Operating Temperature Range (TJ) ................................ –55°C to +125°C Storage Temperature Range (TA) ................................... –65°C to +150°C Lead Temperature (soldering, 3s) .................................................. +240°C NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) VOUT(2) PRODUCT REG113xx-yyyy/zzz XX is package designator. YYYY is typical output voltage (5 = 5.0V, 2.85 = 2.85V, A = Adjustable). ZZZ is package quantity. (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) Output voltages from 2.5V to 5.1V in 50mV increments are available; minimum order quantities apply. Contact factory for details and availability. PIN CONFIGURATIONS Top View MSOP SOT VIN 1 GND 2 Enable 3 5 4 VOUT NR Enable 1 8 GND VIN 2 7 GND VOUT 3 6 GND NR 4 5 GND (N Package) (E Package) NOTE: Leads 5 through 8 are fused to the lead frame and can be used for improved thermal dissipation. 2 REG113 www.ti.com SBVS031D ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range, TJ = –40°C to +85°C. At TJ = +25°C, VIN = VOUT + 1V, VENABLE = 1.8V, IOUT = 5mA, CNR = 0.01µF, and COUT = 0.1µF(1), unless otherwise noted. REG113NA REG113EA PARAMETER OUTPUT VOLTAGE Output Voltage Range REG113-2.5 REG113-2.85 REG113-3 REG113-3.3 REG113-5 Accuracy Over Temperature vs Temperature vs Line and Load Over Temperature DC DROPOUT VOLTAGE(2) For all models Over Temperature VOLTAGE NOISE f = 10Hz to 100kHz Without CNR With CNR OUTPUT CURRENT Current Limit(3) Over Temperature Short-Circuit Current Limit CONDITION MIN 2.5 2.85 3.0 3.3 5.0 ±0.5 dVOUT/dT 50 ±1 IOUT = 5mA to 400mA, VIN = (VOUT + 0.4V) to 10V IOUT = 5mA to 400mA, VIN = (VOUT + 0.6V) to 10V VDROP IOUT = 5mA IOUT = 400mA IOUT = 400mA 4 250 CNR = 0, COUT = 0 CNR = 0.01µF, COUT = 10µF 23µVrms/V • VOUT 7µVrms/V • VOUT ICL 425 ISC VENABLE IENABLE TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance SOT23-5 Surface-Mount MSOP-8 Surface-Mount ±1.5 ±3.0 V V V V V % % ppm/°C % % 10 325 410 mV mV mV ±2.3 ±2.3 ±2.3 500 200 mA mA mA 65 dB 1.8 –0.2 VENABLE = 1.8V to VIN, VIN = 1.8V to VENABLE = 0V to 0.5V COUT = 1.0µF, RLOAD = 13Ω COUT = 1.0µF, RLOAD = 13Ω 6.5(4) µVrms µVrms 1 2 50 1.5 575 600 VIN 0.5 100 100 IGND V V nA nA µs ms °C °C 160 140 Enable Pin LOW INPUT VOLTAGE Operating Input Voltage Range(5) Specified Input Voltage Range Over Temperature UNITS Vn THERMAL SHUTDOWN Junction Temperature Shutdown Reset from Shutdown GROUND PIN CURRENT Ground Pin Current MAX VOUT RIPPLE REJECTION f = 120Hz ENABLE CONTROL VENABLE HIGH (output enabled) VENABLE LOW (output disabled) IENABLE HIGH (output enabled) IENABLE LOW (output disabled) Output Disable Time Output Enable Softstart Time TYP 500 1000 0.2 µA µA µA 1.8 VOUT + 0.4 VOUT + 0.6 10 10 10 V V V –40 –55 –65 +85 +125 +150 °C °C °C IOUT = 5mA IOUT = 400mA VENABLE ≤ 0.5V 400 850 0.01 VIN VIN > 1.8V VIN > 1.8V TJ TJ TA θJA θJC θJA Junction-to-Ambient Junction-to-Case Junction-to-Ambient 200 35(6) 160(6) °C/W °C/W °C/W NOTES: (1) The REG113 does not require a minimum output capacitor for stability. However, transient response can be improved with proper capacitor selection. (2) Dropout voltage is defined as the input voltage minus the output voltage that produces a 2% change in the output voltage from the value at VIN = VOUT + 1V at fixed load. (3) Current limit is the output current that produces a 10% change in output voltage from VIN = VOUT + 1V and IOUT = 5mA. (4) For VENABLE > 6.5V, see typical characteristic IENABLE vs VENABLE. (5) The REG113 no longer regulates when VIN < VOUT + VDROP (MAX). In dropout, the impedance from VIN to VOUT is typically less than 1Ω at TJ = +25°C. (6) See Figure 7. REG113 SBVS031D www.ti.com 3 TYPICAL CHARACTERISTICS For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted. OUTPUT VOLTAGE CHANGE vs IOUT (Referred to IOUT = 200mA at +25°C) LOAD REGULATION vs TEMPERATURE (VIN = VOUT + 1V) 1.0 0 –55°C +25°C +125°C 0.6 –0.2 0.4 0.2 0 –0.2 –0.4 –0.3 –0.4 –0.5 –0.6 –0.6 –0.7 –0.8 –0.8 –1.0 0 50 100 150 200 250 300 350 IOUT = 40mA to 400mA IOUT = 5mA to 400mA –0.1 Ouput Change (%) Ouput Voltage Change (%) 0.8 –0.9 –50 400 –25 0 Output Current (mA) LINE REGULATION (Referred to VIN = VOUT + 1V at IO = 200mA) 75 100 125 LINE REGULATION vs TEMPERATURE 30 IOUT = 200mA, (VOUT + 1V) < VIN < 10 IOUT = 200mA, (VOUT + 0.4V) < VIN < 10 –0.05 –0.10 20 10 0 –10 –20 –0.15 –0.20 –0.25 IOUT = 400mA, (VOUT + 1V) < VIN < 10 IOUT = 400mA, (VOUT + 0.4V) < VIN < 10 –0.30 –0.35 –0.40 –30 –0.45 –40 0 1 2 3 4 5 6 –0.50 –50 7 –25 0 VIN – VOUT (V) 350 350 DC Dropout Voltage (mV) 400 300 250 200 150 100 –55°C +25°C +125°C 50 100 150 200 250 75 100 125 300 350 IOUT = 400mA 300 250 200 150 100 50 0 50 50 DC DROPOUT VOLTAGE vs TEMPERATURE 400 0 25 Temperature (°C) DC DROPOUT VOLTAGE vs OUTPUT CURRENT DC Dropout Voltage (mV) 50 0 5mA 200mA 400mA Ouput Change (%) Ouput Voltage Change (mV) 40 0 –50 400 –25 0 25 50 75 100 125 Junction Temperature (°C) Output Current (mA) 4 25 Temperature (°C) REG113 www.ti.com SBVS031D TYPICAL CHARACTERISTICS (Cont.) For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted. OUTPUT VOLTAGE DRIFT HISTOGRAM OUTPUT VOLTAGE ACCURACY HISTOGRAM 30 18 25 Percentage of Units (%) Percentage of Units (%) 16 14 12 10 8 6 4 20 15 10 5 2 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 1.0 Error (%) VOUT Drift (ppm/°C) OUTPUT VOLTAGE vs TEMPERATURE (Referred to IOUT = 200mA at +25°C) GROUND PIN CURRENT, NOT ENABLED vs TEMPERATURE 0.8 1µ IOUT = 5mA IOUT = 200mA IOUT = 400mA 0.6 VENABLE = 0.5V VIN = VOUT + 1V 100n 0.4 0.2 IGND (A) Output Voltage Change (%) 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 0 10n –0.2 1n –0.4 –0.6 –0.8 –50 –25 0 25 50 75 100 100p –50 125 –25 0 Temperature (°C) 50 75 100 125 GROUND CURRENT vs TEMPERATURE GROUND CURRENT vs LOAD CURRENT 1000 1000 VOUT = 2.5V VOUT = 3.3V VOUT = 5.0V 900 800 IOUT = 400mA VOUT = 2.5V VOUT = 3.3V VOUT = 5.0V 950 700 900 600 IGND (µA) IGND (µA) 25 Temperature (°C) 500 400 850 800 300 200 750 100 0 0 50 100 150 200 250 300 350 700 –50 400 REG113 SBVS031D –25 0 25 50 75 100 125 Temperature (°C) Load Current (mA) www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted. RIPPLE REJECTION vs FREQUENCY RIPPLE REJECTION vs (VIN – VOUT) 80 30 IOUT = 2mA 25 IOUT = 2mA COUT = 10µF 60 Ripple Rejection (dB) Ripple Rejection (dB) 70 IOUT = 100mA COUT = 10µF 50 IOUT = 100mA 40 30 20 COUT = 0µF 10 20 15 10 Frequency = 100kHz COUT = 10µF VOUT = 3.3V IOUT = 100mA 5 0 0 10 100 1k 10k 100k 1M 10M 1.0 0.9 0.8 0.7 Frequency (Hz) 0.6 REG113-5.0 100 Noise Voltage (µVrms) Noise Voltage (µVrms) 40 REG113-3.3 30 20 REG113-2.5 COUT = 0.01µF 10Hz < BW < 100kHz 0.1 0 80 70 60 50 REG113-2.5 40 COUT = 0µF 10Hz < BW < 100kHz 30 20 1 1 10 10 1 COUT = 1µF COUT = 0µF IOUT = 100mA CNR = 0.01µF 1 COUT = 1µF 0.1 COUT = 0µF COUT = 10µF 0.01 COUT = 10µF 0.01 10 100 1k 10k 1k NOISE SPECTRAL DENSITY 10 IOUT = 100mA CNR = 0µF 0.1 100 CNR (pF) eN (µV/√Hz) eN (µV/√Hz) 0.1 REG113-3.3 NOISE SPECTRAL DENSITY 10k 100k Frequency (Hz) 6 0.2 REG113-5.0 90 COUT (µF) 10 0.3 110 50 0 0.4 RMS NOISE VOLTAGE vs CNR RMS NOISE VOLTAGE vs COUT 60 10 0.5 VIN – VOUT (V) 10 100 1k 10k 100k Frequency (Hz) REG113 www.ti.com SBVS031D TYPICAL CHARACTERISTICS (Cont.) For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted. CURRENT LIMIT vs TEMPERATURE CURRENT LIMIT FOLDBACK 600 3.5 550 3.0 500 Output Current (mA) ICL 2.0 1.5 1.0 ISC 450 ICL (Current Limit) ISC (Short-Circuit Current) 400 350 300 250 200 0.5 150 100 –50 0 0 50 100 150 200 250 300 350 400 450 500 550 0 25 50 100 LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE REG113-3.3 VIN = 4.3V VOUT COUT = 10µF VOUT 125 REG113-3.3 IOUT = 400mA COUT = 0 VOUT COUT = 10µF VOUT 5.3V 400mA 40mA IOUT 4.3V VIN 10µs/div 50µs/div TURN-ON TURN-OFF 1V/div COUT = 10µF RLOAD = 13Ω REG113-3.3 VIN = VOUT + 1V CNR = 0.01µF VOUT 1V/div COUT = 0µF RLOAD = 13Ω COUT = 10µF RLOAD = 13Ω COUT = 1.0µF RLOAD = 13Ω COUT = 0µF RLOAD = 660Ω VENABLE 1V/div 1V/div COUT = 0µF RLOAD = 660Ω VOUT VENABLE REG113-3.3 250µs/div 200µs/div REG113 SBVS031D 75 Temperature (°C) COUT = 0 500mV/div –25 Output Current Limit (mA) 25mV/div Output Voltage (V) VOUT = 3.3V 2.5 www.ti.com 7 TYPICAL CHARACTERISTICS (Cont.) For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted. IENABLE vs VENABLE POWER-UP/POWER-DOWN 10µ VOUT = 3.0V RLOAD = 12Ω 500mV/div IENABLE (A) 1.0µ 100n T = +25°C T = +125°C 10n T = –55°C 1n 6 7 8 9 10 1s/div VENABLE (V) BASIC OPERATION The REG113 series of LDO (low dropout) linear regulators offers a wide selection of fixed output voltage versions and an adjustable output version. The REG113 belongs to a family of new generation LDO regulators that use a DMOS pass transistor to achieve ultra low-dropout performance and freedom from output capacitor constraints. Ground pin current remains under 1mA over all line, load, and temperature conditions. All versions have thermal and over-current protection, including foldback current limit. VIN REG113 In 0.1µF Gnd VOUT Out NR COUT CNR 0.01µF Optional FIGURE 1. Fixed Voltage Nominal Circuit for the REG113. CURRENT LIMIT FOLDBACK 3.5 3.0 VOUT = 3.3V Output Voltage (V) The REG113 does not require an output capacitor for regulator stability and is stable over most output currents and with almost any value and type of output capacitor up to 10µF or more. For applications where the regulator output current drops below several milliamps, stability can be enhanced by adding a 1kΩ to 2kΩ load resistor, using capacitance values smaller than 10µF, or keeping the effective series resistance greater than 0.05Ω including the capacitor ESR and parasitic resistance in printed circuit board traces, solder joints, and sockets. Enable 2.5 ICL 2.0 1.5 Although an input capacitor is not required, it is a good standard analog design practice to connect a 0.1µF low ESR capacitor across the input supply voltage; this is recommended to counteract reactive input sources and improve ripple rejection by reducing input voltage ripple. Figure 1 shows the basic circuit connections for the fixed voltage models. FIGURE 2. Foldback Current Limit of the REG113-3.3 at 25°C. INTERNAL CURRENT LIMIT ENABLE The REG113 internal current limit has a typical value of 500mA. A foldback feature limits the short-circuit current to a typical short-circuit value of 200mA. A curve of VOUT versus IOUT is given in Figure 2, and in the Typical Characteristics section. The Enable pin is active high and compatible with standard TTL-CMOS levels. Inputs below 0.5V (max) turn the regulator off and all circuitry is disabled. Under this condition, ground pin current drops to approximately 10nA. When not used, the Enable pin can be connected to VIN. 8 1.0 ISC 0.5 0 0 50 100 150 200 250 300 350 400 450 500 550 Output Current Limit (mA) REG113 www.ti.com SBVS031D OUTPUT NOISE RMS NOISE VOLTAGE vs CNR A precision bandgap reference is used to generate the internal reference voltage, VREF. This reference is the dominant noise source within the REG113 and generates approximately 29µVrms in the 10Hz to 100kHz bandwidth at the reference output. The regulator control loop gains up the reference noise, so that the noise voltage of the regulator is approximately given by: V R1 + R2 = 29µVrms • OUT R2 VREF 100 Noise Voltage (Vrms) VN = 29µVrms 110 (1) REG113-5.0 80 REG113-3.3 70 REG113-2.5 60 50 40 COUT = 0µF 10Hz < BW < 100kHz 30 Since the value of VREF is 1.26V, this relationship reduces to: VN = 23 90 20 µVrms • VOUT V 0.1 (2) 10 100 1k 10k CNR (pF) Connecting a capacitor, CNR, from the Noise Reduction (NR) pin to ground (as shown in Figure 3) forms a low-pass filter for the voltage reference. For CNR = 10nF, the total noise in the 10Hz to 100kHz bandwidth is reduced by approximately a factor of 2.8 for VOUT = 3.3V. This noise reduction effect is shown in Figure 4, and as RMS Noise Voltage vs CNR in the Typical Characteristics section. Noise can be further reduced by carefully choosing an output capacitor, COUT. Best overall noise performance is achieved with very low (< 0.22µF) or very high (> 2.2µF) values of COUT (see the RMS Noise Voltage vs COUT typical characteristic). FIGURE 4. Output Noise versus Noise Reduction Capacitor. typically maintain regulation down to a (VIN – VOUT) voltage drop of 250mV at full rated output current. In Figure 5, the bottom line (DC dropout) shows the minimum V IN to VOUT voltage drop required to prevent dropout under DC load conditions. DROPOUT VOLTAGE vs IOUT 600 The REG113 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the DMOS pass element above VIN. The charge-pump switching noise (nominal switching frequency = 2MHz) is not measurable at the output of the regulator over most values of IOUT and COUT. Dropout for 0mA to IOUT Transient DC Dropout Dropout Voltage (mV) 500 DROPOUT VOLTAGE 400 300 200 100 The REG113 uses an N-channel DMOS as the pass element. When (VIN – VOUT) is less than the dropout voltage (VDROP), the DMOS pass device behaves like a resistor; therefore, for low values of (VIN – VOUT), the regulator inputto-output resistance is the RdsON of the DMOS pass element (typically 600mΩ). For static (DC) loads, the REG113 will 0 0 50 100 150 200 250 300 350 400 IOUT (mA) FIGURE 5. Transient and DC Dropout. VIN NR Low-Noise Charge Pump CNR (optional) VREF (1.26V) DMOS Output VOUT Over-Current Over Temp Protection Enable REG113 GND FIGURE 3. Block Diagram. REG113 SBVS031D www.ti.com 9 For large step changes in load current, the REG113 requires a larger voltage drop across it to avoid degraded transient response. The boundary of this transient dropout region is shown as the top line in Figure 5. Values of VIN to VOUT voltage drop above this line insure normal transient response. In the transient dropout region between DC and Transient, transient response recovery time increases. The time required to recover from a load transient is a function of both the magnitude and rate of the step change in load current and the available headroom VIN to VOUT voltage drop. Under worst-case conditions (full-scale load change with (VIN – VOUT) voltage drop close to DC dropout levels), the REG113 can take several hundred microseconds to re-enter the specified window of regulation. TRANSIENT RESPONSE The REG113 response to transient line and load conditions improves at lower output voltages. The addition of a capacitor (nominal value 0.47µF) from the output pin to ground may improve the transient response. In the adjustable version, the addition of a capacitor, CFB (nominal value 10nF), from the output to the adjust pin also improves the transient response. POWER DISSIPATION The REG113 is available in two different package configurations. The ability to remove heat from the die is different for each package type and, therefore, presents different considerations in the printed circuit board (PCB) layout. On the MSOP-8 package, leads 5 through 8 are fused to the lead frame and may be used to improve the thermal performance of the package. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Although it is difficult or impossible to quantify all of the variables in a thermal design of this type, performance data for several simplified configurations are shown in Figure 6. In all cases the PCB copper area is bare copper, free of solder resist mask, and not solder plated. All examples are for 1-ounce copper and in the case of the MSOP-8, the copper area is connected to fused leads 5 to 8. See Figure 7 for thermal resistance for varying areas of copper. Using heavier copper can increase the effectiveness in removing the heat from the device. In those examples where there is copper on both sides of the PCB, no connection has been provided between the two sides. The addition of plated through holes will improve the heat sink effectiveness. THERMAL PROTECTION MAXIMUM POWER DISSIPATION vs TEMPERATURE 3.0 10 2.0 1.5 1.0 0.5 Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat sink. For reliable operation, junction temperature should be limited to 125°C, maximum. To estimate the margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is triggered. Use worst-case loads and signal conditions. For good reliability, thermal protection should trigger more than 35°C above the maximum expected ambient condition of the application. This produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the REG113 is designed to protect against overload conditions and is not intended to replace proper heat sinking. Continuously running the REG113 into thermal shutdown will degrade reliability. Condition 1 Condition 2 Condition 3 2.5 Power Dissipation (W) Power dissipated within the REG113 can cause the junction temperature to rise, however, the REG113 has thermal shutdown circuitry that protects the regulator from damage. The thermal protection circuitry disables the output when the junction temperature reaches approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on various conditions, the thermal protection circuit can cycle on and off. This limits the dissipation of the regulator, but can have an undesirable effect on the load. 0 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) CONDITION PACKAGE PCB AREA θJA 1 2 3 MSOP-8 MSOP-8 SOT-23-8 1 sq. in. Cu, 1 Side 0.25 sq. in. Cu, 1 Side None 71 90 200 FIGURE 6. Maximum Power Dissipation versus Ambient Temperature for the Various Packages and PCB Heat Sink Configurations. REG113 www.ti.com SBVS031D Power dissipation depends on input voltage, load conditions, and duty cycle and is equal to the product of the average output current times the voltage across the output element (VIN to VOUT voltage drop): Thermal Resistance, θJA (°C/W) PD = (VIN – VOUT ) • IOUT THERMAL RESISTANCE vs PCB COPPER AREA 160 (3) Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required output voltage. 150 140 130 120 110 100 90 80 70 60 0 1 2 3 4 5 Copper Area (inches2) FIGURE 7. Thermal Resistance versus PCB Area for the MSOP-8. REG113 SBVS031D www.ti.com 11 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) REG113EA-2.5/250 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA-2.5/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA-2.5/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA-2.5/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA-3.3/250 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA-3.3/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA-3/250 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA-3/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA-3/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA-3/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA-5/250 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA-5/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA-5/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA-5/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA33250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113EA332K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR REG113NA-2.5/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 16-Aug-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp REG113NA-2.5/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-2.5/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-2.5/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-2.85/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-2.85/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-2.85/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-3.3/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-3.3/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-3.3/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-3.3/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-3/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-3/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-3/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-3/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-5/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-5/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-5/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM REG113NA-5/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 2 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device REG113NA2.85/250G4 16-Aug-2012 Status (1) ACTIVE Package Type Package Drawing SOT-23 DBV Pins 5 Package Qty 250 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant REG113EA-2.5/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 REG113EA-2.5/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 REG113EA-3.3/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 REG113EA-3.3/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 REG113EA-3/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 REG113EA-3/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 REG113EA-5/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 REG113EA-5/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 REG113NA-2.5/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG113NA-2.5/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG113NA-2.85/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG113NA-2.85/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG113NA-3.3/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG113NA-3.3/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG113NA-3/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG113NA-3/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG113NA-5/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 REG113NA-5/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REG113EA-2.5/250 VSSOP DGK 8 250 210.0 185.0 35.0 REG113EA-2.5/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 REG113EA-3.3/250 VSSOP DGK 8 250 210.0 185.0 35.0 REG113EA-3.3/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 REG113EA-3/250 VSSOP DGK 8 250 210.0 185.0 35.0 REG113EA-3/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 REG113EA-5/250 VSSOP DGK 8 250 210.0 185.0 35.0 REG113EA-5/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 REG113NA-2.5/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG113NA-2.5/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG113NA-2.85/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG113NA-2.85/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG113NA-3.3/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG113NA-3.3/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG113NA-3/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG113NA-3/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 REG113NA-5/250 SOT-23 DBV 5 250 203.0 203.0 35.0 REG113NA-5/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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