LP38690-ADJ, LP38692-ADJ www.ti.com SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 LP38690-ADJ LP38692-ADJ 1A Low Dropout CMOS Linear Regulators with Adjustable Output Stable with Ceramic Output Capacitors Check for Samples: LP38690-ADJ, LP38692-ADJ FEATURES DESCRIPTION • • • The LP38690/2-ADJ low dropout CMOS linear regulators provide 2.5% precision reference voltage, extremely low dropout voltage (450mV @ 1A load current, VOUT = 5V) and excellent AC performance utilizing ultra low ESR ceramic output capacitors. 1 2 • • • • • • • • Output Voltage Range of 1.25V - 9V 2.5% Adjust Pin Voltage Accuracy (25°C) Low Dropout Voltage: 450mV @ 1A (typ, 5V out) Wide Input Voltage Range (2.7V to 10V) Precision (Trimmed) Bandgap Reference Ensured Specs for -40°C to +125°C 1µA Off-State Quiescent Current Thermal Overload Protection Foldback Current Limiting SOT-223 and 6-Lead WSON Packages Enable Pin (LP38692-ADJ) The low thermal resistance of the WSON and SOT223 packages allow the full operating current to be used even in high ambient temperature environments. The use of a PMOS power transistor means that no DC base drive current is required to bias it allowing ground pin current to remain below 100 µA regardless of load current, input voltage, or operating temperature. Dropout Voltage: 450 mV (typ) @ 1A (typ. 5V out). APPLICATIONS • • • • Ground Pin Current: 55 µA (typ) at full load. Hard Disk Drives Notebook Computers Battery Powered Devices Portable Instrumentation Adjust Pin Voltage: 2.5% (25°C) accuracy. Typical Application Circuits VIN VOUT VIN VOUT LP38690 -ADJ 1 PF * GND R1 ADJ R2 1 PF * VIN VOUT VIN VEN VOUT LP38692 -ADJ VEN GND R1 ADJ 1 PF * R2 1 PF * VOUT = VADJ x (1 + R1/R2) *Minimum value required for stability. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2013, Texas Instruments Incorporated LP38690-ADJ, LP38692-ADJ SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com Connection Diagrams VEN 1 ADJ 2 5 GND VOUT 3 VIN 4 Figure 1. SOT-223 (LP38692MP-ADJ) – Top View See Package Number NDC0005A VIN 1 GND 2 N/C 3 Exposed Pad on Bottom (DAP) 6 VIN 5 VOUT 4 ADJ Figure 2. 6-Lead WSON (LP38690SD-ADJ) – Top View See Package Number NGG0006A VIN 1 GND 2 VEN 3 Exposed Pad on Bottom (DAP) 6 VIN 5 VOUT 4 ADJ Figure 3. 6-Lead WSON (LP38692SD-ADJ) Top View See Package Number NGG PIN DESCRIPTIONS Pin VIN Description This is the input supply voltage to the regulator. For WSON package devices, both VIN pins must be tied together for full current operation (500mA maximum per pin). GND Circuit ground for the regulator. For the SOT-223 package this is thermally connected to the die and functions as a thermal connection when the soldered down to a large copper plane. VOUT Regulated output voltage. VEN The enable pin allows the part to be turned ON and OFF by pulling this pin high or low. ADJ The adjust pin is used to set the regulated output voltage by connecting it to the external resistors R1 and R2 (see Typical Application Circuits). DAP WSON Only - The DAP (Exposed Pad) functions as a thermal connection when soldered to a copper plane. See WSON MOUNTING section in APPLICATION HINTS for more information. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ LP38690-ADJ, LP38692-ADJ www.ti.com SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) −65°C to +150°C Storage Temperature Range Lead Temp. (Soldering, 5 seconds) 260°C ESD Rating (3) 2 kV Power Dissipation (4) Internally Limited V(max) All pins (with respect to GND) -0.3V to 12V IOUT (5) Internally Limited Junction Temperature −40°C to +150°C (1) (2) (3) (4) (5) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. ESD is tested using the human body model which is a 100pF capacitor discharged through a 1.5k resistor into each pin. At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used). The junction-to-ambient thermal resistance (θJ-A) for the SOT-223 is approximately 125 °C/W for a PC board mounting with the device soldered down to minimum copper area (less than 0.1 square inch). If one square inch of copper is used as a heat dissipator for the SOT-223, the θJ-A drops to approximately 70 °C/W. The θJ-A values for the WSON package are also dependent on trace area, copper thickness, and the number of thermal vias used (refer to the TI AN-1187 Application Report and the WSON MOUNTING section in this datasheet). If power disspation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown. If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground. OPERATING RATINGS VIN Supply Voltage 2.7V to 10V −40°C to +125°C Operating Junction Temperature Range Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ Submit Documentation Feedback 3 LP38690-ADJ, LP38692-ADJ SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VOUT + 1V, CIN = COUT = 10 µF, ILOAD = 10mA. Min/Max limits are specified through testing, statistical correlation, or design. Symbol Min Typ (1) Max VIN = 2.7V 1.219 1.25 1.281 1.187 1.25 1.313 Parameter Conditions Units VADJ ADJ Pin Voltage 3.2V ≤ VIN ≤ 10V 100 µA < IL < 1A ΔVO/ΔVIN Output Voltage Line Regulation (2) VO + 0.5V ≤ VIN ≤ 10V IL = 25mA 0.03 0.1 %/V ΔVO/ΔIL Output Voltage Load Regulation (3) 1 mA < IL < 1A VIN = VO + 1V 1.8 5 %/A (VO = 1.8V) IL = 1A 950 1600 (VO = 2.5V) IL = 0.1A IL = 1A 80 800 145 1300 (VO = 3.3V) IL = 0.1A IL = 1A 65 650 110 1000 (VO = 5V) IL = 0.1A IL = 1A 45 450 100 800 55 100 0.001 1 VIN - VO IQ Dropout Voltage (4) VIN ≤ 10V, IL = 100 µA - 1A Quiescent Current VEN ≤ 0.4V, (LP38692-ADJ Only) IL(MIN) Minimum Load Current VIN - VO ≤ 4V IFB Foldback Current Limit VIN - VO > 5V 450 VIN - VO < 4V 1500 Ripple Rejection TSD Thermal Shutdown Activation (Junction Temp) 160 TSD (HYST) Thermal Shutdown Hysteresis (Junction Temp) 10 IADJ ADJ Input Leakage Current VADJ = 0 - 1.5V VIN = 10V en Output Noise BW = 10Hz to 10kHz VO = 3.3V 0.7 VO (LEAK) Output Leakage Current VO = VO(NOM) + 1V @ 10VIN 0.5 VEN Enable Voltage (LP38692-ADJ Only) Output = OFF (1) (2) (3) (4) 4 mV µA 100 PSRR IEN V VIN = VO + 2V(DC), with 1V(p-p) / 120Hz Ripple mA 55 dB °C Enable Pin Leakage (LP38692ADJ Only) -100 0.01 100 nA µV/√Hz 2 µA 0.4 Output = ON, VIN = 4V 1.8 Output = ON, VIN = 6V 3.0 Output = ON, VIN = 10V 4.0 VEN = 0V or 10V, VIN = 10V -1 V 0.001 1 µA Typical numbers represent the most likely parametric norm for 25°C operation. Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1mA to full load. Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100mV of nominal value. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ LP38690-ADJ, LP38692-ADJ www.ti.com SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 BLOCK DIAGRAMS VIN P-FET N/C + ENABLE LOGIC P-FET MOSFET DRIVER FOLDBACK CURRENT LIMITING THERMAL SHUTDOWN VOUT 1.25V REFERENCE ADJ GND Figure 4. LP38690-ADJ Functional Diagram (WSON) VIN P-FET VEN + ENABLE LOGIC MOSFET DRIVER P-FET FOLDBACK CURRENT LIMITING THERMAL SHUTDOWN VOUT 1.25V REFERENCE ADJ GND Figure 5. LP38692-ADJ Functional Diagram (SOT-223, WSON) Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ Submit Documentation Feedback 5 LP38690-ADJ, LP38692-ADJ SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, enable pin is tied to VIN (LP38692-ADJ only), VO = 1.25V, VIN = 2.7V, IL = 10mA. Noise vs Frequency Noise vs Frequency 1.0 1.2 COUT = 10 PF COUT = 1 PF 0.8 Hz) Hz) 1.0 0.6 NOISE (PV/ NOISE/ (PV 0.8 0.6 0.4 0.4 0.2 0.2 0.0 0.0 10 100 1k 10k 100k 10 100 FREQUENCY (Hz) Figure 6. Noise vs Frequency 100k Ripple Rejection 70 COUT = 100 PF 60 RIPPLE REJECTION (dB) Hz) 10k Figure 7. 1.5 1.0 NOISE (PV/ 1k FREQUENCY (Hz) 0.5 50 40 30 VIN (DC) = 3.25V 20 VIN (AC) = 1V(p-p) COUT = 10 PF 10 0 0.0 10 100 1k 10k 10 100k 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 8. Figure 9. Ripple Rejection 70 60 60 RIPPLE REJECTION (dB) RIPPLE REJECTION (dB) Ripple Rejection 70 50 40 30 20 VIN (DC) = 3.25V VIN (AC) = 1V(p-p) 10 0 10 40 30 VIN (DC) = 3.25V 20 VIN (AC) = 1V(p-p) COUT = 1 PF 10 COUT = 100 PF 100 50 1k 10k 100k 0 10 FREQUENCY (Hz) Submit Documentation Feedback 1k 10k 100k FREQUENCY (Hz) Figure 10. 6 100 Figure 11. Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ LP38690-ADJ, LP38692-ADJ www.ti.com SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, enable pin is tied to VIN (LP38692-ADJ only), VO = 1.25V, VIN = 2.7V, IL = 10mA. VADJ vs Temperature Line Transient Response 0.4 VOUT = 1.25V COUT = 100 PF 20 % DEVIATION 0 -0.2 -0.4 10 VOUT 0 -10 -20 4 VIN -0.6 3 2 -0.8 -1 -50 VIN (V) 'VOUT (mV) 0.2 1 -25 0 25 50 75 100 200 Ps/DIV 125 TEMPERATURE (oC) Figure 12. Figure 13. Line Transient Response Line Transient Response VOUT = 3.3V COUT = 10 PF 40 0 -10 -20 20 VOUT 0 -20 -40 4 VIN 4 3 VIN (V) 5 VIN 2 3 1 200 Ps/DIV 200 Ps/DIV Figure 14. Figure 15. Line Transient Response Line Transient Response VOUT = 3.3V VOUT = 1.25V 100 50 VOUT 0 -50 -100 COUT = 1 PF 50 VOUT 0 -50 -100 4 VIN (V) 5 VIN 4 VIN 2 3 100 Ps/DIV 3 VIN (V) COUT = 10 PF 'VOUT (mV) 'VOUT (mV) 100 VIN (V) VOUT 'VOUT (mV) 'VOUT (mV) 10 VOUT = 1.25V COUT = 100 PF 20 1 40 Ps/DIV Figure 16. Figure 17. Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ Submit Documentation Feedback 7 LP38690-ADJ, LP38692-ADJ SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, enable pin is tied to VIN (LP38692-ADJ only), VO = 1.25V, VIN = 2.7V, IL = 10mA. Line Transient Response Load Transient Response 100 VOUT = 3.3V 'VOUT (mV) 100 50 VOUT 0 -50 50 VOUT 0 COUT = 100 PF -50 -100 -100 1 ILOAD 4 VIN (V) 5 VIN 0.01 ILOAD (A) 'VOUT (mV) COUT = 1 PF 3 100 Ps/DIV 200 Ps/DIV Figure 18. Figure 19. Load Transient Response Load Transient Response 200 COUT = 10 PF COUT = 10 PF 200 'VOUT (mV) 'VOUT (mV) 400 0 VOUT -200 100 0 VOUT -100 -200 -400 0.01 ILOAD (A) ILOAD ILOAD (A) 0.5 1 ILOAD 0.01 40 Ps/DIV 40 Ps/DIV Figure 20. Figure 21. Load Transient Response Load Transient Response 400 400 COUT = 1 PF 200 'VOUT (mV) 'VOUT (mV) COUT = 1 PF VOUT 0 -200 -400 200 0 VOUT -200 -400 0.01 ILOAD 0.01 10 Ps/DIV 10 Ps/DIV Figure 22. 8 Submit Documentation Feedback ILOAD (A) ILOAD ILOAD (A) 0.5 1 Figure 23. Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ LP38690-ADJ, LP38692-ADJ www.ti.com SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, enable pin is tied to VIN (LP38692-ADJ only), VO = 1.25V, VIN = 2.7V, IL = 10mA. VOUT vs VIN , VOUT = 1.25V VOUT vs VIN , VOUT = 1.80V Figure 24. Figure 25. VOUT vs VIN (Power-Up) VOUT vs VEN, ON (LP38692 Only) Figure 26. Figure 27. VOUT vs VEN, OFF (LP38692 Only) Minimum VIN vs IOUT 3.4 3.2 MINIMUM VIN (V) 125°C 3 2.8 2.6 -40°C 2.4 25°C 2.2 2 0 200 400 600 800 1000 IOUT (mA) Figure 28. Figure 29. Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ Submit Documentation Feedback 9 LP38690-ADJ, LP38692-ADJ SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, enable pin is tied to VIN (LP38692-ADJ only), VO = 1.25V, VIN = 2.7V, IL = 10mA. Dropout Voltage vs IOUT Enable Voltage vs Temperature 2.3 1600 VOUT = 1.8V 1400 1.9 1200 1.7 125°C 1000 VEN (V) VDROPOUT (mV) VIN = 10V 2.1 800 600 25°C -40°C 1.3 1.1 400 0.9 200 0.7 200 400 600 800 VIN = 4V 0.5 -50 0 0 VIN = 6V 1.5 1000 -25 0 25 50 75 100 125 TEMPERATURE (oC) IOUT (mA) Figure 30. Figure 31. Load Regulation vs Temperature Line Regulation vs Temperature -1.0 0.034 0.032 'VOUT/'VIN (%/V) 'VOUT/'IOUT (%/A) -1.5 -2.0 -2.5 0.03 0.028 0.026 0.024 -3.0 0.022 -3.5 -50 -25 0 25 50 75 100 125 0.02 -50 -25 TEMPERATURE (oC) Submit Documentation Feedback 25 50 75 100 125 o TEMPERATURE ( C) Figure 32. 10 0 Figure 33. Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ LP38690-ADJ, LP38692-ADJ www.ti.com SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 APPLICATION HINTS EXTERNAL CAPACITORS Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be correctly selected for proper performance. INPUT CAPACITOR: An input capacitor of at least 1µF is required (ceramic recommended). The capacitor must be located not more than one centimeter from the input pin and returned to a clean analog ground. OUTPUT CAPACITOR: An output capacitor is required for loop stability. It must be located less than 1 centimeter from the device and connected directly to the output and ground pins using traces which have no other currents flowing through them. The minimum amount of output capacitance that can be used for stable operation is 1µF. Ceramic capacitors are recommended (the LP38690/2-ADJ was designed for use with ultra low ESR capacitors). The LP38690/2-ADJ is stable with any output capacitor ESR between zero and 100 Ohms. SETTING THE OUTPUT VOLTAGE: The output voltage is set using the external resistors R1 and R2 (see Typical Application Circuits). The output voltage will be given by the equation: VOUT = VADJ x (1 + ( R1 / R2 ) ) (1) Because the part has a minimum load current requirement of 100 µA, it is recommended that R2 always be 12k Ohms or less to provide adequate loading. Even if a minimum load is always provided by other means, it is not recommended that very high value resistors be used for R1 and R2 because it can make the ADJ node susceptible to noise pickup. A maximum value of 100k is recommended for R2 to prevent this from occurring. ENABLE PIN (LP38692-ADJ only): The LP38692–ADJ has an Enable pin (EN) which allows an external control signal to turn the regulator output On and Off. The Enable On/Off threshold has no hysteresis. The voltage signal must rise and fall cleanly, and promptly, through the ON and OFF voltage thresholds. The Enable pin has no internal pull-up or pull-down to establish a default condition and, as a result, this pin must be terminated either actively or passively. If the Enable pin is driven from a source that actively pulls high and low, the drive voltage should not be allowed to go below ground potential or higher than VIN. If the application does not require the Enable function, the pin should be connected directly to the VIN pin. FOLDBACK CURRENT LIMITING: Foldback current limiting is built into the LP38690/2-ADJ which reduces the amount of output current the part can deliver as the output voltage is reduced. The amount of load current is dependent on the differential voltage between VIN and VOUT. Typically, when this differential voltage exceeds 5V, the load current will limit at about 450 mA. When the VIN -VOUT differential is reduced below 4V, load current is limited to about 1500 mA. SELECTING A CAPACITOR It is important to note that capacitance tolerance and variation with temperature must be taken into consideration when selecting a capacitor so that the minimum required amount of capacitance is provided over the full operating temperature range. Capacitor Characteristics CERAMIC For values of capacitance in the 10 to 100 µF range, ceramics are usually larger and more costly than tantalums but give superior AC performance for bypassing high frequency noise because of very low ESR (typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature. Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ Submit Documentation Feedback 11 LP38690-ADJ, LP38692-ADJ SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of the temperature range. X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance. TANTALUM Solid Tantalum capacitors have good temperature stability: a high quality Tantalum will typically show a capacitance value that varies less than 10-15% across the full temperature range of -40°C to 125°C. ESR will vary only about 2X going from the high to low temperature limits. The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if the ESR of the capacitor is near the upper limit of the stability range at room temperature). REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. A less common condition is when an alternate voltage source is connected to the output. There are two possible paths for current to flow from the output pin back to the input during a reverse voltage condition. 1) While VIN is high enough to keep the control circuity alive, and the Enable pin (LP38692-ADJ only) is above the VEN(ON) threshold, the control circuitry will attempt to regulate the output voltage. If the input voltage is less than the programmed output voltage, the control circuit will drive the gate of the pass element to the full ON condition. In this condition, reverse current will flow from the output pin to the input pin, limited only by the RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up to 1000 μF in this manner will not damage the device as the current will rapidly decay. However, continuous reverse current should be avoided. When the Enable pin is low this condition will be prevented. 2) The internal PFET pass element has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, when VIN is below the value where the control circuity is alive, or the Enable pin is low (LP38692-ADJ only), and the output voltage is more than 500 mV (typical) above the input voltage the parasitic diode becomes forward biased and current flows from the output pin to the input pin through the diode. The current in the parasitic diode should be limited to less than 1A continuous and 5A peak. If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin must be diode clamped to ground to limit the negative voltage transition. A Schottky diode is recommended for this protective clamp. PCB LAYOUT Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops. The input and output capacitors must be directly connected to the input, output, and ground pins of the regulator using traces which do not have other currents flowing in them (Kelvin connect). The best way to do this is to lay out CIN and COUT near the device with short traces to the VIN, VOUT, and ground pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its capacitors have a "single point ground". It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane were used at the ground points of the IC and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground technique for the regulator and it’s capacitors fixed the problem. Since high current flows through the traces going into VIN and coming from VOUT, Kelvin connect the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors. 12 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ LP38690-ADJ, LP38692-ADJ www.ti.com SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 WSON MOUNTING The NGG0006A (No Pullback) 6-Lead WSON package requires specific mounting techniques which are detailed in the TI AN-1187 Application Report. Referring to the section PCB Design Recommendations (Page 5), it should be noted that the pad style which should be used with the WSON package is the NSMD (non-solder mask defined) type. Additionally, it is recommended the PCB terminal pads to be 0.2 mm longer than the package pads to create a solder fillet to improve reliability and inspection. The input current is split between two VIN pins, 1 and 6. The two VIN pins must be connected together to ensure that the device can meet all specifications at the rated current. The thermal dissipation of the WSON package is directly related to the printed circuit board construction and the amount of additional copper area connected to the DAP. The DAP (exposed pad) on the bottom of the WSON package is connected to the die substrate with a conductive die attach adhesive. The DAP has no direct electrical (wire) connection to any of the pins. There is a parasitic PN junction between the die substrate and the device ground. As such, it is strongly recommend that the DAP be connected directly to the ground at device lead 2 (i.e. GND). Alternately, but not recommended, the DAP may be left floating (i.e. no electrical connection). The DAP must not be connected to any potential other than ground. For the LP38690-ADJ and LP38692-ADJ in the NGG0006A 6- Lead WSON package, the junction-to-case thermal rating, θJC, is 10.4°C/W, where the case is the bottom of the package at the center of the DAP. The junction-to-ambient thermal performance for the LP38690-ADJ and LP38692-ADJ in the NGG0006A 6-Lead WSON package, using the JEDEC JESD51 standards is summarized in the following table: Board Type Thermal Vias θJC θJA JEDEC 2–Layer JESD 51-3 None 10.4°C/W 237°C/W 1 10.4°C/W 74°C/W 2 10.4°C/W 60°C/W 4 10.4°C/W 49°C/W 6 10.4°C/W 45°C/W JEDEC 4–Layer JESD 51-7 RFI/EMI SUSCEPTIBILITY RFI (radio frequency interference) and EMI (electromagnetic interference) can degrade any integrated circuit’s performance because of the small dimensions of the geometries inside the device. In applications where circuit sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must be taken to ensure that this does not affect the IC regulator. If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the IC. If a load is connected to the IC output which switches at high speed (such as a clock), the high-frequency current pulses required by the load must be supplied by the capacitors on the IC output. Since the bandwidth of the regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above that frequency. This means the effective output impedance of the IC at frequencies above 100 kHz is determined only by the output capacitor(s). In applications where the load is switching at high speed, the output of the IC may need RF isolation from the load. It is recommended that some inductance be placed between the output capacitor and the load, and good RF bypass capacitors be placed directly across the load. PCB layout is also critical in high noise environments, since RFI/EMI is easily radiated directly into PC traces. Noisy circuitry should be isolated from "clean" circuits where possible, and grounded through a separate path. At MHz frequencies, ground planes begin to look inductive and RFI/ EMI can cause ground bounce across the ground plane. In multi-layer PCB applications, care should be taken in layout so that noisy power and ground planes do not radiate directly into adjacent layers which carry analog power and ground. Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ Submit Documentation Feedback 13 LP38690-ADJ, LP38692-ADJ SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com OUTPUT NOISE Noise is specified in two ways- Spot Noise or Output Noise density is the RMS sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a function of frequency. Total Output Noise or Broad-Band Noise is the RMS sum of spot noise over a specified bandwidth, usually several decades of frequencies. Attention should be paid to the units of measurement. Spot noise is measured in units µV/root-Hz or nV/root-Hz and total output noise is measured in µV(rms) The primary source of noise in low-dropout regulators is the internal reference. Noise can be reduced in two ways: by increasing the transistor area or by increasing the current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a smaller package. Increasing the current drawn by the internal reference increases the total supply current (ground pin current). 14 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ LP38690-ADJ, LP38692-ADJ www.ti.com SNVS323H – DECEMBER 2004 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision G (April 2013) to Revision H • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38690-ADJ LP38692-ADJ Submit Documentation Feedback 15 PACKAGE OPTION ADDENDUM www.ti.com 12-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP38690SD-ADJ NRND WSON NGG 6 1000 TBD Call TI Call TI -40 to 125 L112B LP38690SD-ADJ/NOPB ACTIVE WSON NGG 6 1000 Green (RoHS & no Sb/Br) CU SN | Call TI Level-1-260C-UNLIM -40 to 125 L112B LP38690SDX-ADJ/NOPB ACTIVE WSON NGG 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L112B LP38692MP-ADJ NRND SOT-223 NDC 5 1000 TBD Call TI Call TI -40 to 125 LJNB LP38692MP-ADJ/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LJNB LP38692MPX-ADJ/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LJNB LP38692SD-ADJ NRND WSON NGG 6 1000 TBD Call TI Call TI -40 to 125 L122B LP38692SD-ADJ/NOPB ACTIVE WSON NGG 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L122B LP38692SDX-ADJ/NOPB ACTIVE WSON NGG 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L122B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 12-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP38690SD-ADJ WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LP38690SD-ADJ/NOPB WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LP38690SDX-ADJ/NOPB WSON NGG 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LP38692MP-ADJ SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP38692MP-ADJ/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP38692MPX-ADJ/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP38692SD-ADJ WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LP38692SD-ADJ/NOPB WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LP38692SDX-ADJ/NOPB WSON NGG 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38690SD-ADJ WSON NGG 6 1000 210.0 185.0 35.0 LP38690SD-ADJ/NOPB WSON NGG 6 1000 210.0 185.0 35.0 LP38690SDX-ADJ/NOPB WSON NGG 6 4500 367.0 367.0 35.0 LP38692MP-ADJ SOT-223 NDC 5 1000 367.0 367.0 35.0 LP38692MP-ADJ/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP38692MPX-ADJ/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0 LP38692SD-ADJ WSON NGG 6 1000 210.0 185.0 35.0 LP38692SD-ADJ/NOPB WSON NGG 6 1000 210.0 185.0 35.0 LP38692SDX-ADJ/NOPB WSON NGG 6 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NDC0005A www.ti.com MECHANICAL DATA NGG0006A SDE06A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated