TPS734xx www.ti.com ........................................................................................................................................ SBVS089F – DECEMBER 2007 – REVISED FEBRUARY 2009 250mA, Low Quiescent Current, Ultra-Low Noise, High PSRR Low-Dropout Linear Regulator FEATURES DESCRIPTION 1 • 250mA Low Dropout Regulator with EN • Low IQ: 44µA • Multiple Output Voltage Versions Available: – Fixed Outputs of 1.0V to 4.3V Using Innovative Factory EEPROM Programming – Adjustable Outputs from 1.25V to 6.2V • High PSRR: 60dB at 1kHz • Ultra-low Noise: 28µVRMS • Fast Start-Up Time: 45µs • Stable with a Low-ESR, 2.0µF Typical Output Capacitance • Excellent Load/Line Transient Response • 2% Overall Accuracy (Load/Line/Temp) • Very Low Dropout: 125mV at 250mA • ThinSOT-23, 2mm × 2mm SON-6, and 3mm x 3mm SON-8 Packages The TPS734xx family of low-dropout (LDO), low-power linear regulators offers excellent ac performance with very low ground current. High power-supply rejection ratio (PSRR), low noise, fast start-up, and excellent line and load transient response are provided while consuming a very low 44µA (typical) ground current. The TPS734xx is stable with ceramic capacitors and uses an advanced BiCMOS fabrication process to yield a typical dropout voltage of 125mV at 250mA output. The TPS734xx uses a precision voltage reference and feedback loop to achieve overall accuracy of 2% over all load, line, process, and temperature variations. It is fully specified from TJ = –40°C to +125°C and is offered in low-profile ThinSOT-23, 2mm × 2mm SON, and 3mm x 3mm SON packages that are ideal for wireless handsets, printers, and WLAN cards. 2 APPLICATIONS • • • • WiFi, WiMax Printers Cellular Phones, SmartPhones Handheld Organizers, PDAs TPS734xxDDC TSOT23-5 (TOP VIEW) IN 1 GND 2 EN 3 5 4 TPS734xxDRV 2mm x 2mm SON-6 (TOP VIEW) TPS73401DDC TSOT23-5 (TOP VIEW) OUT NR IN 1 GND 2 EN 3 5 4 OUT OUT 1 NR 2 GND 3 GND 6 IN 5 N/C 4 EN TPS73401DRV 2mm x 2mm SON-6 (TOP VIEW) OUT 1 FB 2 GND 3 GND 6 IN 5 N/C 4 EN FB 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2009, Texas Instruments Incorporated TPS734xx SBVS089F – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) VOUT (2) PRODUCT TPS734xxyyyz (1) (2) XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable). YYY is package designator. Z is package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Output voltages from 1.0V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS (1) Over operating temperature range (unless otherwise noted). PARAMETER TPS734xx UNIT VIN range –0.3 to +7.0 V VEN range –0.3 to VIN +0.3 V VOUT range –0.3 to VIN +0.3 V –0.3 to VFB (TYP) +0.3 V VFB range Peak output current Internally limited Continuous total power dissipation See Dissipation Ratings Table Junction temperature range, TJ –55 to +150 Storage junction temperature range, TSTG –55 to +150 °C ESD rating, HBM 2 kV ESD rating, CDM 500 V (1) °C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. DISSIPATION RATINGS BOARD PACKAGE RθJC RθJA DERATING FACTOR ABOVE TA = +25°C TA < +25°C TA = +70°C TA = +85°C Low-K (1) DDC 90°C/W 280°C/W 3.6mW/°C 360mW 200mW 145mW (2) DDC 90°C/W 200°C/W 5.0mW/°C 500mW 275mW 200mW Low-K (1) DRV 20°C/W 140°C/W 7.1mW/°C 715mW 395mW 285mW High-K (2) DRV 20°C/W 65°C/W 15.4mW/°C 1.54W 845mW 615mW High-K (1) (2) 2 The JEDEC low-K (1s) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), two-layer board with 2-ounce (56,699g) copper traces on top of the board. The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), multilayer board with 1-ounce (28,35g) internal power and ground planes and 2-ounce (56,699g) copper traces on top and bottom of the board Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated TPS734xx www.ti.com ........................................................................................................................................ SBVS089F – DECEMBER 2007 – REVISED FEBRUARY 2009 ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA, VEN = VIN, COUT = 2.2µF, CNR = 0.01µF, unless otherwise noted. For TPS73401, VOUT = 3.0V. Typical values are at TJ = +25°C. PARAMETER TEST CONDITIONS (1) VIN Input voltage range VFB Internal reference (TPS73401) Output voltage range (TPS73401) VOUT Output accuracy 6.5 V 1.208 1.232 V VFB 6.3 V +1.0 % +2.0 % Nominal TJ = +25°C –1.0 Over VIN, IOUT, Temp VOUT + 0.3V ≤ VIN ≤ 6.5V 1mA ≤ IOUT ≤ 250mA –2.0 Output accuracy ΔVOUT%/ ΔVIN Line regulation (1) VOUT(NOM) + 0.3V ≤ VIN ≤ 6.5V ΔVOUT%/ ΔIOUT Load regulation 500µA ≤ IOUT ≤ 250mA VDO Dropout voltage (2) (VIN = VOUT(NOM) – 0.1V) IOUT = 250mA ICL Output current limit VOUT = 0.9 × VOUT(NOM) IGND Ground pin current 500µA ≤ IOUT ≤ 250mA ISHDN Shutdown current (IGND) VEN ≤ 0.4V PSRR MAX 1.184 VOUT IFB TYP 2.7 VOUT (1) MIN Feedback pin current (TPS73401) Power-supply rejection ratio VIN = 3.85V, VOUT = 2.85V, CNR = 0.01µF, IOUT = 100mA 300 VN TSTR VEN(HI) Enable high (enabled) VEN(LO) Enable low (shutdown) IEN(HI) Enable pin current, enabled TSD Thermal shutdown temperature TJ Operating junction temperature UVLO (1) (2) Startup time, VOUT = 0 ~ 90%, VOUT = 2.85V, RL = 14Ω, COUT = 2.2µF 0.02 %/V 0.005 %/mA 125 219 mV 580 900 mA 45 65 µA 0.15 1.0 µA 0.5 µA –0.5 f = 100Hz 60 dB f = 1kHz 56 dB f = 10kHz 41 dB f = 100kHz Output noise voltage BW = 10Hz to 100kHz, VOUT = 2.8V ±1.0 UNIT 28 dB CNR = 0.01µF 11 x VOUT µVRMS CNR = none 95 x VOUT µVRMS CNR = none 45 µs CNR = 0.001µF 45 µs CNR = 0.01µF 50 µs CNR = 0.047µF 50 µs 1.2 VIN 0 0.4 V 1.0 µA VEN = VIN = 6.5V 0.03 Shutdown, temperature increasing 165 Reset, temperature decreasing 145 –40 Undervoltage lock-out VIN rising Hysteresis VIN falling 1.90 °C °C +125 2.20 V 2.65 70 °C V mV Minimum VIN = VOUT + VDO or 2.7V, whichever is greater. VDO is not measured for devices with VOUT(NOM) < 2.8V because minimum VIN = 2.7V. Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS734xx SBVS089F – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAMS IN OUT IN OUT 400W 400W 2m A Current Limit Thermal Shutdown EN 3.3MW Current Limit Overshoot Detect Overshoot Detect Thermal Shutdown EN UVLO UVLO Quickstart 1.208V (1) Bandgap NR 500kW 1.208V Bandgap FB 500kW GND GND NOTE (1): Fixed voltage versions between 1.0V to 1.2V have a 1.0V bandgap circuit instead of a 1.208V bandgap circuit. Figure 1. Fixed Voltage Versions Figure 2. Adjustable Voltage Versions PIN CONFIGURATIONS TPS734xxDDC TSOT23-5 (TOP VIEW) IN GND 2 EN 3 OUT 5 1 TPS734xxDRV 2mm x 2mm SON-6 (TOP VIEW) TPS73401DDC TSOT23-5 (TOP VIEW) NR 4 IN 1 GND 2 EN 3 5 4 OUT OUT 1 NR 2 GND 3 GND 6 IN 5 N/C 4 EN TPS73401DRV 2mm x 2mm SON-6 (TOP VIEW) OUT 1 FB 2 GND 3 GND 6 IN 5 N/C 4 EN FB PIN DESCRIPTIONS TPS734xx 4 NAME DDC DRV DRB IN 1 6 8 Input supply. GND 2 3, Pad 4 Ground. The pad must be tied to GND. EN 3 4 5 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used. NR 4 2 3 Fixed voltage versions only; connecting an external capacitor to this pin bypasses noise generated by the internal bandgap. This allows output noise to be reduced to very low levels. FB 4 2 3 Adjustable version only; this is the input to the control loop error amplifier, and is used to set the output voltage of the device. OUT 5 1 1 Output of the regulator. A small capacitor (total typical capacitance ≥ 2.0µF ceramic) is needed from this pin to ground to assure stability. N/C — 5 2, 6, 7 Submit Documentation Feedback DESCRIPTION Not internally connected. This pin must either be left open, or tied to GND. Copyright © 2007–2009, Texas Instruments Incorporated TPS734xx www.ti.com ........................................................................................................................................ SBVS089F – DECEMBER 2007 – REVISED FEBRUARY 2009 TYPICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C); VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA, VEN = VIN,COUT = 2.2µF, CNR = 0.01µF, unless otherwise noted. For TPS73401, VOUT = 3.0V. Typical values are at TJ = +25°C. TPS73401 LINE REGULATION 0.5 IOUT = 100mA 0.3 TJ = -40°C 0.2 TJ = 0°C 0.1 0 -0.1 TJ = +25°C -0.2 TJ = +85°C -0.3 0.3 TJ = 0°C TJ = -40°C 0.2 0.1 0 -0.1 -0.2 TJ = +85°C -0.3 TJ = +125°C -0.4 IOUT = 100mA 0.4 Change in VOUT (%) 0.4 Change in VOUT (%) TPS73425 LINE REGULATION 0.5 TJ = +125°C -0.4 -0.5 -0.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 3.0 6.5 3.5 4.0 4.5 VIN (V) 6.5 Y-axis range is ±2% of 2.5V 2.54 2.84 2.53 2.83 TJ = -40°C 2.81 2.80 2.79 VOUT (V) 2.52 2.82 VOUT (V) 6.0 TPS73425 LOAD REGULATION 2.55 Y-axis range is ±2% of 2.8V 2.85 5.5 Figure 4. TPS73401 LOAD REGULATION 2.86 5.0 VIN (V) Figure 3. TJ = +85°C 2.78 2.77 TJ = 0°C 2.51 2.49 TJ = +25°C 2.47 TJ = +85°C TJ = +125°C 2.46 2.75 2.74 TJ = -40°C 2.50 2.48 TJ = +125°C 2.76 2.45 0 50 100 150 200 0 250 50 100 150 200 250 Load (mA) Load (mA) Figure 5. Figure 6. TPS73425 GROUND PIN CURRENT vs OUTPUT CURRENT TPS73425 GROUND PIN CURRENT (DISABLE) vs TEMPERATURE 60 TJ = +25°C 50 500 TJ = +125°C VEN = 0.4V 450 TJ = +85°C 400 350 TJ = -40°C 30 TJ = 0°C 20 IGND (na) 40 IGND (mA) TJ = +25°C 300 250 VIN = 3.3V 200 VIN = 5.0V 150 VIN = 6.5V 100 10 50 0 0 0 50 100 150 200 250 -40 -25 -10 5 20 35 50 IOUT (mA) TJ (°C) Figure 7. Figure 8. Copyright © 2007–2009, Texas Instruments Incorporated 65 80 95 110 125 Submit Documentation Feedback 5 TPS734xx SBVS089F – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C); VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA, VEN = VIN,COUT = 2.2µF, CNR = 0.01µF, unless otherwise noted. For TPS73401, VOUT = 3.0V. Typical values are at TJ = +25°C. TPS73401 DROPOUT VOLTAGE vs OUTPUT CURRENT POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN – VOUT = 1.0V) 400 90 350 80 TJ = +125°C 250 PSRR (dB) VDO (mV) 300 TJ = +85°C 200 TJ = +25°C 150 40 COUT = 10mF CNR = 0.01mF 10 0 0 0 50 100 150 200 10 250 100 IOUT = 200mA 10k 1k 100k 1M 10M IOUT (mA) Frequency (Hz) Figure 9. Figure 10. POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN – VOUT = 0.5V) POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN – VOUT = 0.3V) 90 90 80 80 IOUT = 1mA 70 IOUT = 200mA 60 IOUT = 100mA 50 40 30 0 IOUT = 200mA 60 IOUT = 100mA 50 40 30 20 10 IOUT = 1mA 70 PSRR (dB) PSRR (dB) IOUT = 100mA 50 20 TJ = 0°C TJ = -40°C 50 20 COUT = 2.2mF CNR = 0.01mF 10 100 IOUT = 250mA 10k 1k COUT = 2.2mF CNR = 0.01mF 10 0 100k 1M 10M 10 100 IOUT = 200mA 10k 1k 100k Frequency (Hz) Frequency (Hz) Figure 11. Figure 12. TPS73425 TOTAL NOISE vs CNR TPS73425 TOTAL NOISE vs COUT 140 Total Noise (mVRMS) 80 60 40 20 15 10 5 20 0 IOUT = 1mA CNR = 0.01mF 0 0.1 1 10 0 5 10 15 CNR (nF) COUT (mF) Figure 13. Figure 14. Submit Documentation Feedback 10M 25 100 0.01 1M 30 IOUT = 1mA COUT = 2.2mF 120 Total Noise (mVRMS) IOUT = 250mA 60 30 100 6 IOUT = 1mA 70 20 25 Copyright © 2007–2009, Texas Instruments Incorporated TPS734xx www.ti.com ........................................................................................................................................ SBVS089F – DECEMBER 2007 – REVISED FEBRUARY 2009 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C); VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA, VEN = VIN,COUT = 2.2µF, CNR = 0.01µF, unless otherwise noted. For TPS73401, VOUT = 3.0V. Typical values are at TJ = +25°C. TPS73425 TURN-ON RESPONSE (VIN = VEN) TPS73425 ENABLE RESPONSE OVER STABLE VIN 3.5 3.5 3.0 COUT = 2.2mF 3.0 VOUT 2.5 2.0 1.5 COUT = 10mF 1.0 VEN VOUT COUT = 2.2mF 2.0 Voltage (V) Voltage (V) 2.5 VEN 1.5 1.0 0.5 0.5 0 0 COUT = 10mF -0.5 -0.5 10ms/div 10ms/div Figure 15. Figure 16. TPS73410 POWER-UP/POWER-DOWN TPS73410 LOAD TRANSIENT RESPONSE 7 IOUT = 250mA 6 VIN = 2.7V COUT = 1.0mF 100mV/div VOUT VIN 5 COUT = 2.2mF 100mV/div Volts 4 VOUT 3 VOUT 2 250mA 1 0 100mA/div 1mA IOUT -1 20ms/div 50ms/div Figure 17. Figure 18. TPS73410 LINE TRANSIENT RESPONSE IOUT = 250mA COUT = 2.2mF 20mV/div 20mV/div VOUT COUT = 1.0mF VOUT 3.7V 1V/div dVIN dt 2.7V = 1V/ms VIN 20ms/div Figure 19. Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 7 TPS734xx SBVS089F – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com APPLICATION INFORMATION The TPS734xx family of LDO regulators combines the high performance required of many RF and precision analog applications with ultra-low current consumption. High PSRR is provided by a high gain, high bandwidth error loop with good supply rejection at very low headroom (VIN – VOUT). Fixed voltage versions provide a noise reduction pin to bypass noise generated by the bandgap reference and to improve PSRR while a quick-start circuit fast-charges this capacitor at startup. The combination of high performance and low ground current also make the TPS734xx an excellent choice for portable applications. All versions have thermal and over-current protection and are fully specified from –40°C to +125°C. Figure 20 shows the basic circuit connections for fixed voltage models. Figure 21 gives the connections for the adjustable output version (TPS73401). R1 and R2 can be calculated for any output voltage using the formula in Figure 21. Optional input capacitor. May improve source impedance, noise, or PSRR. VIN IN VOUT OUT TPS734xx EN GND VEN 2.2mF Ceramic NR Optional bypass capacitor to reduce output noise and increase PSRR. Figure 20. Typical Application Circuit for FIxed Voltage Versions Optional input capacitor. May improve source impedance, noise, or PSRR. VIN IN VOUT = R2 GND ´ 1.208 VOUT OUT TPS73401 EN (R1 + R2) R1 FB CFB 2.2mF Ceramic R2 VEN Figure 21. Typical Application Circuit for Adjustable Voltage Versions space space 8 Submit Documentation Feedback Input and Output Capacitor Requirements Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1µF to 1µF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. The ground of this capacitor should be connected as close as the ground of output capacitor; a capacitor value of 0.1µF is enough in this condition. When it is difficult to place these two ground points close together, a 1µF capacitor is recommended. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1µF input capacitor may be necessary to ensure stability. The TPS734xx is designed to be stable with standard ceramic output capacitors of values 2.2µF or larger. X5R and X7R type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR of the output capacitor should be < 1.0Ω, so output capacitor type should be either ceramic or conductive polymer electrolytic. Feedback Capacitor Requirements (TPS73401 only) The feedback capacitor, CFB, shown in Figure 21 is required for stability. For a parallel combination of R1 and R2 equal to 250kΩ, any value from 3pF to 1nF can be used. Fixed voltage versions have an internal 30pF feedback capacitor that is quick-charged at start-up. The adjustable version does not have this quick-charge circuit, so values below 5pF should be used to ensure fast startup; values above 47pF can be used to implement an output voltage soft-start. Larger value capacitors also improve noise slightly. The TPS73401 is stable in unity-gain configuration (OUT tied to FB) without CFB. Output Noise In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the TPS734xx, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01µF noise reduction capacitor; for the adjustable version, smaller value resistors in the output resistor divider reduce noise. A parallel combination that gives 2µA of divider current has the same noise performance as a fixed voltage version. To further Copyright © 2007–2009, Texas Instruments Incorporated TPS734xx www.ti.com ........................................................................................................................................ SBVS089F – DECEMBER 2007 – REVISED FEBRUARY 2009 optimize noise, equivalent series resistance of the output capacitor can be set to approximately 0.2Ω. This configuration maximizes phase margin in the control loop, reducing total output noise by up to 10%. Noise can be referred to the feedback point (FB pin) such that with CNR = 0.01µF, total noise is given approximately by Equation 1: 11mVRMS VN = x VOUT V (1) The TPS73401 adjustable version does not have the noise-reduction pin available, so ultra-low noise operation is not possible. Noise can be minimized according to the above recommendations. Board Layout Recommendations to Improve PSRR and Noise Performance To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. Internal Current Limit The TPS734xx internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the device should not be operated in current limit for extended periods of time. The PMOS pass element in the TPS734xx has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting may be appropriate. Shutdown The enable pin (EN) is active high and is compatible with standard and low voltage TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN. Dropout Voltage The TPS734xx uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS, ON of the PMOS pass element. Because the PMOS device behaves like a resistor in dropout, VDO approximately scales with output current. Copyright © 2007–2009, Texas Instruments Incorporated As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in the Typical Characteristics section. Startup and Noise Reduction Capacitor Fixed voltage versions of the TPS734xx use a quick-start circuit to fast-charge the noise reduction capacitor, CNR, if present (see the Functional Block Diagrams). This architecture allows the combination of very low output noise and fast start-up times. The NR pin is high impedance so a low leakage CNR capacitor must be used; most ceramic capacitors are appropriate in this configuration. Note that for fastest startup, VIN should be applied first, then the enable pin (EN) driven high. If EN is tied to IN, startup is somewhat slower. Refer to the Typical Characteristics section. The quick-start switch is closed for approximately 135µs. To ensure that CNR is fully charged during the quick-start time, a 0.01µF or smaller capacitor should be used. Transient Response As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. In the adjustable version, adding CFB between OUT and FB improves stability and transient response. The transient response of the TPS734xx is enhanced by an active pull-down that engages when the output overshoots by approximately 5% or more when the device is enabled. When enabled, the pull-down device behaves like a 400Ω resistor to ground. Undervoltage Lock-Out (UVLO) The TPS734xx utilizes an undervoltage lock-out circuit to keep the output shut off until internal circuitry is operating properly. The UVLO circuit has a de-glitch feature so that it typically ignores undershoot transients on the input if they are less than 50µs duration. Minimum Load The TPS734xx is stable and well-behaved with no output load. To meet the specified accuracy, a minimum load of 1mA is required. Below 1mA at junction temperatures near +125°C, the output can drift up enough to cause the output pull-down to turn on. The output pull-down limits voltage drift to 5% typically but ground current could increase by approximately 50µA. In typical applications, the junction cannot reach high temperatures at light loads because there is no appreciable dissipated power. The specified ground current would then be valid at no load conditions in most applications. Submit Documentation Feedback 9 TPS734xx SBVS089F – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com Thermal Information Thermal Protection Power Dissipation Thermal protection disables the output when the junction temperature rises to approximately +165°C, allowing the device to cool. When the junction temperature cools to approximately +145°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Dissipation Ratings table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. Power dissipation depends on input voltage and load conditions. Power dissipation is equal to the product of the output current time the voltage drop across the output pass element, as shown in Equation 2: P D + ǒVIN*V OUTǓ @ I OUT (2) Package Mounting Solder pad footprint recommendations for the TPS734xx are available from the Texas Instruments web site at www.ti.com. The internal protection circuitry of the TPS734xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS734xx into thermal shutdown degrades device reliability. 10 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS73401DDCR PREVIEW SOT DDC 5 3000 TBD Call TI Call TI TPS73401DDCT PREVIEW SOT DDC 5 250 TBD Call TI Call TI TPS73401DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73401DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73418DRBR PREVIEW SON DRB 8 TBD Call TI Call TI TPS73418DRBT PREVIEW SON DRB 8 TBD Call TI Call TI TPS73418DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73418DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73430DRBR PREVIEW SON DRB 8 TBD Call TI Call TI TPS73430DRBT PREVIEW SON DRB 8 TBD Call TI Call TI TPS73430DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73430DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73433DDCR PREVIEW SOT DDC 5 3000 TBD Call TI Call TI 250 Lead/Ball Finish MSL Peak Temp (3) TPS73433DDCT PREVIEW SOT DDC 5 TBD Call TI Call TI TPS73433DRBR PREVIEW SON DRB 8 TBD Call TI Call TI TPS73433DRBT PREVIEW SON DRB 8 TBD Call TI Call TI TPS73433DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS73433DRVT ACTIVE SON DRV 6 250 CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2009 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 28-Mar-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS73401DRVR SON DRV 6 SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73401DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73418DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73418DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73430DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73430DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73433DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS73433DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Mar-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS73401DRVR SON DRV 6 3000 195.0 200.0 45.0 TPS73401DRVT SON DRV 6 250 195.0 200.0 45.0 TPS73418DRVR SON DRV 6 3000 195.0 200.0 45.0 TPS73418DRVT SON DRV 6 250 195.0 200.0 45.0 TPS73430DRVR SON DRV 6 3000 195.0 200.0 45.0 TPS73430DRVT SON DRV 6 250 195.0 200.0 45.0 TPS73433DRVR SON DRV 6 3000 195.0 200.0 45.0 TPS73433DRVT SON DRV 6 250 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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