TI CLVTH32244IGKEREP

SCBS793A − DECEMBER 2003 − REVISED JUNE 2004
D Controlled Baseline
D
D
D
D
D
D Typical VOLP (Output Ground Bounce)
− One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree†
Member of the Texas Instruments
Widebus+  Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
GKE PACKAGE
(TOP VIEW)
1
2
3
4
5
<0.8 V at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot
Insertion
Supports Unregulated Battery Operation
Down To 2.7 V
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
D
D
D
D
D
D
terminal assignments
6
1
2
3
4
5
6
A
A
1Y2
1Y1
1OE
2OE
1A1
1A2
B
B
1Y4
1Y3
GND
GND
1A3
1A4
C
C
2Y2
2Y1
2A2
D
2Y4
2Y3
1VCC
GND
2A1
D
1VCC
GND
2A3
2A4
E
3Y2
3Y1
GND
GND
3A1
3A2
F
3Y4
3Y3
3A4
4Y2
4Y1
1VCC
GND
3A3
G
1VCC
GND
4A1
4A2
H
4Y3
4Y4
4OE
3OE
4A4
4A3
E
F
G
H
J
5Y2
5Y1
5OE
6OE
5A1
5A2
K
5Y4
5Y3
GND
GND
5A3
5A4
K
L
6Y2
6Y1
6A2
M
6Y4
6Y3
2VCC
GND
6A1
L
2VCC
GND
6A3
6A4
M
N
7Y2
7Y1
GND
GND
7A1
7A2
N
P
7Y4
7Y3
8Y2
8Y1
2VCC
GND
7A4
R
2VCC
GND
7A3
P
8A1
8A2
R
T
8Y3
8Y4
8OE
7OE
8A4
8A3
J
T
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
Copyright  2004, Texas Instruments Incorporated
!" # $%&" !# '%()$!" *!"&
*%$"# $ " #'&$$!"# '& "+& "&# &,!# #"%&"#
#"!*!* -!!". *%$" '$&##/ *&# " &$&##!). $)%*&
"&#"/ !)) '!!&"&#
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCBS793A − DECEMBER 2003 − REVISED JUNE 2004
description/ordering information
The SN74LVTH32244 is a 32-bit buffer and line driver designed for low-voltage (3.3-V) VCC operation, but with
the capability to provide a TTL interface to a 5-V system environment. This device can be used as eight 4-bit
buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. The device provides true outputs and has
symmetrical active-low output-enable (OE) inputs. It is designed specifically to improve the performance and
density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
When VCC is between 0 and 1.5-V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5-V, OE shall be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
ORDERABLE
PART NUMBER
PACKAGE†
TOP-SIDE
MARKING
−40°C to 85°C
LFBGA − GKE
Tape and reel CLVTH32244IGKEREP
L244EP
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each 4-bit buffer/driver)
INPUTS
2
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCBS793A − DECEMBER 2003 − REVISED JUNE 2004
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
5OE
5A1
5A2
5A3
5A4
6OE
6A1
6A2
6A3
6A4
A3
3OE
A5
A2
A6
A1
B5
B2
B6
B1
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
A4
4OE
C5
C2
C6
C1
D5
D2
D6
D1
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
J3
7OE
J5
J2
J6
J1
K5
K2
K6
K1
5Y1
7A1
5Y2
7A2
5Y3
7A3
5Y4
7A4
J4
8OE
L5
L2
L6
L1
M5
M2
M6
M1
6Y1
8A1
6Y2
8A2
6Y3
8A3
6Y4
8A4
POST OFFICE BOX 655303
H4
E5
E2
E6
E1
F5
F2
F6
F1
3Y1
3Y2
3Y3
3Y4
H3
G5
G2
G6
G1
H6
H1
H5
H2
4Y1
4Y2
4Y3
4Y4
T4
N5
N2
N6
N1
P5
P2
P6
P1
7Y1
7Y2
7Y3
7Y4
T3
R5
R2
R6
R1
T6
T1
T5
T2
• DALLAS, TEXAS 75265
8Y1
8Y2
8Y3
8Y4
3
SCBS793A − DECEMBER 2003 − REVISED JUNE 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage temperature range, Tstg (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction
of overall device life. See Figure 1 for additional information on thermal derating.
0.0001
1/Time to Failure − Hours
125°C (16 kHours, 1.84 Years)
115°C (40 kHours, 4.57 Years)
0.00001
105°C (104 kHours, 11.94 Years)
100°C (172 kHours, 19.65 Years)
0.000001
1/TJ − Constant Device Junction Temperature
Figure 1. Estimated Wirebond Life Based on Elevated-Temperature Kirkendall-Voiding Failure Mode
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCBS793A − DECEMBER 2003 − REVISED JUNE 2004
recommended operating conditions (see Note 5)
MIN
MAX
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
5.5
V
IOH
IOL
High-level output current
−32
mA
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
−40
High-level input voltage
2
V
0.8
Low-level output current
Outputs enabled
V
V
64
mA
10
ns/V
µs/V
85
°C
NOTE 5: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SCBS793A − DECEMBER 2003 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
−1.2
V
VIK
VCC = 2.7 V,
VCC = 2.7 V to 3.6 V,
II = −18 mA
IOH = −100 µA
VOH
VCC = 2.7 V,
VCC = 3 V,
IOH = −8 mA
IOH = −32 mA
IOL = 100 µA
IOL = 24 mA
0.2
VCC = 2.7 V
IOL = 16 mA
IOL = 32 mA
0.4
IOL = 64 mA
VI = 5.5 V
0.55
VOL
VCC = 3 V
Control inputs
VCC = 0 or 3.6 V,
VCC = 3.6 V,
Data inputs
VCC = 3.6 V
II
Ioff
II(hold)
IOZH
IOZL
VCC = 0,
Data inputs
VCC−0.2
2.4
V
2
0.5
10
±1
VI = VCC or GND
VI = VCC
1
VI = 0
VI or VO = 0 to 4.5 V
VCC = 3 V
VI = 0.8 V
VI = 2 V
VCC = 3.6 V‡,
VCC = 3.6 V,
VI = 0 to 3.6 V
VO = 3 V
VCC = 3.6 V,
VO = 0.5 V
V
0.5
µA
A
−5
±100
µA
75
µA
−75
±500
5
µA
−5
µA
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don’t care
± 100
µA
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don’t care
±100
µA
ICC
VCC = 3.6 V, IO = 0,
VI = VCC or GND
Outputs high
0.38
Outputs low
10
Outputs disabled
∆ICC§
VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
VO = 3 V or 0
mA
0.38
0.2
4
mA
pF
Co
9
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCBS793A − DECEMBER 2003 − REVISED JUNE 2004
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 2)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
PARAMETER
tsk(o)
† All typical values are at VCC = 3.3 V, TA = 25°C.
POST OFFICE BOX 655303
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
TYP†
MAX
1.2
2.3
3.2
3.7
1.2
2
3.2
3.7
1.2
2.6
4
5
1.2
2.7
4
5
2.2
3.3
4.5
5
2
3.1
4.2
4.4
0.5
• DALLAS, TEXAS 75265
MIN
UNIT
MAX
ns
ns
ns
ns
7
SCBS793A − DECEMBER 2003 − REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT
1.5 V
Timing Input
0V
tw
tsu
2.7 V
Input
1.5 V
th
2.7 V
1.5 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
2.7 V
Input
1.5 V
1.5 V
0V
tPHL
tPLH
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPZL
tPLZ
3V
1.5 V
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLH
tPHL
2.7 V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CLVTH32244IGKEREP
ACTIVE
LFBGA
GKE
96
1000
TBD
SNPB
Level-3-220C-168 HR
V62/04720-01XA
ACTIVE
LFBGA
GKE
96
1000
TBD
SNPB
Level-3-220C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVTH32244-EP :
• Catalog: SN74LVTH32244
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CLVTH32244IGKEREP
Package Package Pins
Type Drawing
LFBGA
GKE
96
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
5.7
B0
(mm)
K0
(mm)
P1
(mm)
13.7
2.0
8.0
W
Pin1
(mm) Quadrant
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CLVTH32244IGKEREP
LFBGA
GKE
96
1000
333.2
345.9
31.8
Pack Materials-Page 2
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