E2N0026-18-Y3
¡ Semiconductor
ML60851A
¡ Semiconductor
Pr
el
im
This version: Nov.
1998
ML60851A ina
ry
USB Device Controller
GENERAL DESCRIPTION
The ML60851A is a general purpose Universal Serial Bus (USB) device controller. The ML60851A
provides a USB interface, control/status block, application interface, and FIFOs. The FIFO interface
and two types of transfer have been optimized for BulkOut devices such as printers and BulkIn
devices such as digital still cameras and image scanners. In addition, Mass Storage devices are
also applicable to this device.
FEATURES
• USB 1.0 compliant
• Built-in USB transceiver circuit
• Full-speed (12 Mb/sec) support
• Supports printer device class, image device class, and Mass Storage device class
• Supports three types of transfer; control transfer, bulk transfer, and interrupt transfer
• Built-in FIFOs for control transfer
Two 8-byte FIFOs (one for receive FIFO and the other for transmit FIFO)
• Built-in FIFOs for bulk transfer (available for either receive FIFO or transmit FIFO)
One 64-byte FIFO
Two 64-byte FIFOs
• Built-in FIFO for interrupt transfer
One 8-byte FIFO
• Supports one control endpoint, two bulk endpoint addresses, and one interrupt endpoint
address
• Two 64-byte FIFOs enable fast BulkOut transfer and BulkIn transfer
• Supports 8 bit/16 bit DMA transfer
• VCC is 3.0 V to 3.6 V
• Supporting dual power supply enables 5 V application interface
• Built-in 48 MHz oscillator circuit
• Package options:
44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: ML60851AGA)
44-pin plastic TQFP (TQFP44-P-1010-0.80-K) (Product name: ML60851ATB)
1/44
XIN
48 MHz
XOUT
A7:A0
Status/Control
Oscillator
DPLL
D15:D0
Application
Application
Interface
Module
CS, WR, RD
RESET
D+
D–
(Local MCU)
Protocol
USB
USB Bus
¡ Semiconductor
BLOCK DIAGRAM
ML60851A
INTR
Engine
Transceiver
Endpoint FIFO/
8-byte Setup Register
DREQ
DACK
ML60851A
2/44
¡ Semiconductor
ML60851A
D+
AD0
AD1
AD2
AD3
VCC5
VSS
AD4
AD5
AD6
AD7
DREQ
44
43
42
41
40
39
38
37
36
35
34
PIN CONFIGURATION (TOP VIEW)
1
33
DACK
D–
2
32
A0
VCC3
3
31
A1
TEST1
4
30
A2
TEST2
5
29
A3
XIN
6
28
A4
XOUT
7
27
A5
CS
8
26
A6
AD6
AD7
DREQ
36
35
34
22
D8
AD5
37
21
D9
AD4
38
D10
VSS
39
D11
VCC5
40
VCC5
AD3
41
VSS
AD2
42
D12
AD1
43
D13
AD0
44
D14
20
DACK
19
33
18
1
17
ALE
16
23
15
11
14
ADSEL
RESET
13
A7
24
12
25
D15
9
10
INTR
RD
WR
44-Pin Plastic QFP
A3
6
28
A4
7
27
A5
8
26
A6
19
20
21
22
D11
D10
D9
D8
ALE
18
23
VCC5
ADSEL
11
17
A7
24
VSS
25
16
9
10
D12
RESET
29
15
RD
WR
30
14
CS
A2
4
5
D13
XOUT
A1
D14
XIN
A0
31
13
TEST2
32
12
TEST1
2
3
D15
D–
VCC3
INTR
D+
44-Pin Plastic TQFP
3/44
¡ Semiconductor
ML60851A
PIN DESCRIPTION
Pin
Symbol
Type
1, 2
D+, D–
I/O
USB data
6, 7
XIN, XOUT
—
Pin for external crystal oscillator
4, 5
TEST1, 2
I
D15:D8
I/O
Data bus (MSB)
AD7:AD0
I/O
Data bus (LSB)/address input
A7:A0
I
Address input
8
CS
I
Chip select signal input pin. LOW active
9
RD
I
Read signal input pin. LOW active
13 to 16,
19 to 22
35 to 38,
41 to 44
25 to 32
Description
Test Pins (normally "L")
10
WR
I
Write signal input pin. LOW active
12
INTR
O
Interrupt request signal output pin
34
DREQ
O
DMA request output pin
33
DACK
I
DMA acknowledge signal input pin
23
ALE
I
Address latch enable signal input pin
24
ADSEL
I
Address input mode select input pin. "H": address/data multiplex
11
RESET
I
System Reset signal input pin. LOW active
4/44
¡ Semiconductor
ML60851A
INTERNAL REGISTERS
Addresses and Names of Registers
Address
Register name
Read
Write
A7, A6
A7, A6
00h
11b
01b
Device Address Register
01h
11b
01b
Device State Register
02h
11b
—
Packet Error Register
03h
11b
—
Receive FIFO Register
04h
11b
—
Transmit FIFO Register
08h
11b
01b
Endpoint Packet-Ready Register
A5:A0
09h
11b
—
Endpoint 0 Receive-Byte Count Register
0Ah
11b
—
Endpoint 1 Receive-Byte Count Register
0Bh
11b
—
Endpoint 2 Receive-Byte Count Register
0Eh
—
01b
Flash Transmit FIFO
0Fh
—
01b
System Control
10h
11b
—
bmRequestType Setup Register
11h
11b
—
bRequest Setup Register
12h
11b
—
wValue LSB Setup Register
13h
11b
—
wValue MSB Setup Register
14h
11b
—
wIndex LSB Setup Register
15h
11b
—
wIndex MSB Setup Register
16h
11b
—
wLength LSB Setup Register
17h
11b
—
wLength MSB Setup Register
1Ah
11b
01b
Assertion Select Register
1Bh
11b
01b
Interrupt Enable Register
1Ch
11b
—
Interrupt Status Register
1Dh
11b
01b
DMA Control Register
1Eh
11b
01b
DMA Interval Register
1Fh
—
—
Reserved
20h
11b
—
Endpoint 0 Receive Control Register
21h
11b
—
Endpoint 0 Receive General Register
22h
11b
01b
Endpoint 0 Receive Payload Register
23h
—
—
Reserved
24h
11b
01b
Endpoint 1 Control Register
25h
11b
01b
Endpoint 1 General Register
26h
11b
01b
Endpoint 1 Payload Register
27h
—
—
Reserved
5/44
¡ Semiconductor
ML60851A
Addresses and Names of Registers (Continued)
Address
Register name
Read
Write
A7, A6
A7, A6
30h
11b
—
Endpoint 0 Transmit Control Register
31h
11b
—
Endpoint 0 Transmit General Register
32h
11b
01b
Endpoint 0 Transmit Payload Register
33h
11b
01b
Endpoint 0 General Register
34h
11b
01b
Endpoint 2 Control Register
35h
11b
01b
Endpoint 2 General Register
36h
11b
01b
Endpoint 2 Payload Register
A5:A0
37h
—
—
Reserved
38h
11b
01b
Endpoint 3 Control Register
39h
11b
01b
Endpoint 3 General Register
3Ah
11b
01b
Endpoint 3 Payload Register
00h
01b
—
Endpoint 0 Receive FIFO data
01h
01b
—
Endpoint 1 Receive FIFO data
02h
01b
—
Endpoint 2 Receive FIFO data
00h
—
11b
Endpoint 0 Transmit FIFO data
01h
—
11b
Endpoint 1 Transmit FIFO data
02h
—
11b
Endpoint 2 Transmit FIFO data
03h
—
11b
Endpoint 3 Transmit FIFO data
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¡ Semiconductor
ML60851A
Register Description
Device Address Register (C0h, 40h)
D7
D6
D5
D4
RFU
D3
D2
D1
D0
Device Address (R/W)
The local MCU writes a device address, which is given by the SET_ADDRESS command form the
host computer, into this register. Thereafter, this device processes an only token packet transmitted
to the given device address.
Device State Register (C1h, 41h)
D7
D6
D5
D4
D3
D2
D1
D0
RFU
Default State (R/W)
Address State (R/W)
Configuration State (R/W)
Suspended State (R)
Remote Wakeup (R/W)
USB Bus Reset Clear (W)
Default, Address, and Configuration States: D2, D1, and D0 are set to 0, 0, and 1 (default states) by
reset respectively. Changing the values of this register gives no influence on operation of this
device.
Suspended State: This register is asserted when the device enters the suspended state.
This register is deaserted by reset or when the device exits the suspended state by a resume signaling
from the USB bus.
Remote Wakeup: When this device signals a remote wakeup during the suspended state, this
register is asserted by a local MCU. This register is automatically deasserted when the device exits
the suspended state by a resume signaling from the USB bus.
USB Bus Reset Status Clear: Writing "1" to this bit causes the interrupt status to be cleared (the USB
bus reset interrupt status bit is "0" and the INTR pin is deasserted) while the USB bus reset interrupt
is being serviced (when D5, the USB bus reset interrupt status bit, of the interrupt status register is
"1" and the INTR pin is asserted). This bit is readable, and when read, its value will be always "0".
Packet Error Register (C2h, –)
D7
D6
D5
D4
D3
D2
D1
D0
RFU
Bit Stuff Error (R)
RFU = 0000b
Data CRC Error (R)
Address CRC Error (R)
PID Error (R)
7/44
¡ Semiconductor
ML60851A
FIFO Status Register 1 (C3h, –)
D7
D6
D5
D4
D3
D2
D1
D0
RFU
Receive FIFO0 Full (R)
RFU = 0000b
Receive FIFO0 Empty (R)
FIFO1 Full (R)
FIFO1 Empty (R)
FIFO Status Register 2 (C4h, –)
D7
D6
D5
D4
D3
D2
D1
D0
RFU
Transmit FIFO0 Full (R)
Transmit FIFO0 Empty (R)
FIFO2 Full (R)
FIFO2 Empty (R)
RFU = 0000b
FIFO3 Full (R)
FIFO3 Empty (R)
Endpoint Packet-Ready Register (C8h, 48h)
D7
D6
D5
D4
D3
D2
D1
D0
RFU
EP0 Receive Packet Ready (R/Reset)
EP1 Receive Packet Ready (R/Reset)
EP2 Receive Packet Ready (R/Reset)
EP0 Transmit Packet Ready (R/Set)
EP1 Transmit Packet Ready (R/Set)
EP2 Transmit Packet Ready (R/Set)
EP3 Transmit Packet Ready (R/Set)
Receive Packet Ready: When a valid packet arrives at an endpoint, this bit is automatically set and
the endpoint is locked. When "1" is written in this register, Receiver Packet Ready is reset and the
endpoint is unlocked. (This bit also is set to "0".)
When DMA is enabled, EP1 Receive Packet Ready is automatically reset after all the data in EP1 is
read during DMA transfer.
Transmit Packet Ready: When "1" is written in this register, the Transmit Packet Ready is set and the
packet in the corresponding endpoint is transmitted. Transmit Packet Ready is automatically reset
when the ACK handshake is returned from the host.
When DMA is enabled, EP1 Transmit Packet Ready is automatically set after the data written in EP1
reaches the maximum packet size during DMA transfer.
The value of this register remains unchanged when "0" is written in this register.
8/44
¡ Semiconductor
ML60851A
Endpoint 0 Receive Byte Count Register (C9h, –)
D7
D6
D5
D4
D3
RFU
D2
D1
D0
D1
D0
D1
D0
EP0 Byte Count (R)
Endpoint 1 Receive Byte Count Register (CAh, –)
D7
D6
D5
D4
D3
RFU
D2
EP1 Byte Count (R)
Endpoint 2 Receive Byte Count Register (CBh, –)
D7
D6
D5
D4
D3
RFU
D2
EP2 Byte Count (R)
Flash Transmit FIFO (–, 4Eh)
D7
D6
D5
D4
0
0
0
0
D3
D2
D1
D0
0
In case EP1 is set as a transmission endpoint, when "1" is
written in this bit, the FIFO at EP1 is cleared and Packet
Ready at EP1 is reset by the WRITE pulse.
In case EP2 is set as a transmission endpoint, when "1" is
written in this bit, the FIFO at EP2 is cleared and Packet
Ready at EP2 is reset by the WRITE pulse.
In case EP3 is set as a transmission endpoint, when "1" is
written in this bit, the FIFO at EP3 is cleared and Packet
Ready at EP3 is reset by the WRITE pulse.
Note: Please clear all FIFOs at the same time, otherwise some of them may not be cleared.
System Control (–, 4Fh)
D7
D6
D5
D4
D3
D2
D1
0
0
0
D0
When "1" is written in this bit, the ML60851A is reset
by the WRITE pulse.
Oscillation Stop Command
Oscillation Stop Command: Writing 1010b to D7 to D4, (writing A0h into this register) causes the
oscillator circuit of the ML60851A to be deactivated and go into the standby mode.
When oscillation is stopped, reading and writing into the register is possible but reading and writing
into FIFO is not possible. Asserting the RESET pin restarts oscillation.
9/44
¡ Semiconductor
ML60851A
bmRequestType Setup Register (D0h, –)
D7
D6
D5
D4
Type (R)
D3
D2
D1
D0
Recipient (R)
0 = Device
1 = Interface
2 = Endpoint
3 = Others
4 to 31 = Reserved
0 = Standard
1 = Class
2 = Vendor
3 = Reserved
0 = Host to device
Data Transfer Direction (R)
1 = Device to host
bRequest Setup Register (D1h, –)
D7
D6
D5
D4
D3
D2
D1
D0
Specific Request (R)
• wValueLSB Setup Register (D2h, –)
D7:D0 = LSB of Word Size Field (R)
• wValueMSB Setup Register (D3h, –)
D7:D0 = MSB of Word Size Field (R)
• wIndexLSB Setup Register (D4h, –)
D7:D0 = LSB of Word Size Field (R)
• wIndexMSB Setup Register (D5h, –)
D7:D0 = MSB of Word Size Field (R)
• wLengthLSB Setup Register (D6h, –)
This field defines the length of data that is transferred in the second stage (data stage) of control
transfer. (R)
• wLengthMSB Setup Register (D7h, –)
This field defines the length of data that is transferred in the data stage of control transfer. (R)
10/44
¡ Semiconductor
ML60851A
Assertion Select Register (DAh, 5Ah) (R/W)
D7
D6
D5
D4
D3
RFU
D2
D1
D0
Assertion
Assertion
Assertion
of DACK
of DREQ
of INTR
0 = Active LOW (Initial value)
1 = Active HIGH
0 = Active LOW (Initial value)
1 = Active HIGH
0 = Active HIGH (Initial value)
1 = Active LOW
Interrupt Enable Register (DBh, 5Bh) (R/W)
D7
D6
D5
D4
D3
D2
D1
D0
Setup Ready
Interrupt Enable
EP1 Packet Ready
Interrupt Enable
EP2 Packet Ready
Interrupt Enable
EP0 Receive Packet Ready
Interrupt Enable
EP0 Transmit Packet Ready
Interrupt Enable
USB Bus Reset
Interrupt Enable
Suspended State
Interrupt Enable
EP3 Packet Ready
Interrupt Enable
Initial value of D0 is 1.
Initial values of D1 to D7 are 0.
11/44
¡ Semiconductor
ML60851A
Interrupt Status Register (DCh, 5Ch) (R)
D7
D6
D5
D4
D3
D2
D1
D0
Setup Ready
Interrupt Status (R)
EP1 Packet Ready
Interrupt Status (R)
EP2 Packet Ready
Interrupt Status (R)
EP0 Receive Packet Ready
Interrupt Status (R)
EP0 Transmit Packet Ready
Interrupt Status (R)
USB Bus Reset
Interrupt Status
Suspended State
Interrupt Status (R)
EP3 Packet Ready
Interrupt Status
Setup Ready Interrupt Status: Equivalent to Setup Ready at (F3h)described later when the corresponding
Interrupt Enable bit is asserted.
EP1 Packet Ready Interrupt Status: Equivalent to EP1 Receive Packet Ready (the complement of EP1
Transmit Packet Ready when EP1 is set for transmitter) at (C8h) described before when the
corresponding Interrupt Enable bit is asserted.
EP2 Packet Ready Interrupt Status: Equivalent to EP2 Receive Packet Ready (the complement of EP2
Transmit Packet Ready when EP2 is set for transmitter) at (C8h) described before when the
corresponding Interrupt Enable bit is asserted.
EP0 Receive Packet Ready Interrupt Status: Equivalent to EP0 Receive Packet Ready at (C8h) described
before when the corresponding Interrupt Enable bit is asserted.
EP0 Transmit Packet Ready Interrupt Status: Equivalent to the complement of EP0 Transmit Packet
Ready at (C8h) described before when the corresponding Interrupt Enable bit is asserted.
USB Bus Reset Interrupt Status: This bit is set to "1" at USB bus reset when the D5 bit of the interrupt
enable register (DBh) is "1". To return this bit back to "0", "1" should be written to the D5 bit of the
device states register.
Suspended State Interrupt Status: Equivalent to Suspended State Register at (C1h) described before
when the corresponding Interrupt Enable bit is asserted.
EP3 Packet Ready Interrupt Status: When the D7 bit of the interrupt enable register (DBh) is "1", the
complement of the D7 bit of the endpoint packet ready register (C8h) is being copied.
12/44
¡ Semiconductor
ML60851A
DMA Control Register (DDh, 5Dh) (R/W)
D7
D6
D5
RFU
D4
D3
D2
D1
D0
Transfer
Transfer
Byte
Address
DMA
Mode
Size
Count
Mode
Enable
0 = Disables DMA Transfer (Initial value)
1 = Enables DMA Transfer for EP1
0 = Single Address Mode (Initial value)
1 = Dual Address Mode
0 = (Initial value)
1 = Inserts EP1 receive byte count into the top byte or
top word of the transfer data. (Note 1)
0 = Byte (8 bits) (Initial value)
1 = Word (16 bits) (Note 2)
0 = Single Transfer Mode (Initial value)
1 = Demand Transfer Mode
(Note 1)
(Note 2)
When 16-bit mode is set, the upper byte of the top word is 00h.
When 16-bit mode is set and the packet size is an odd-number byte, the upper byte of the
last word is 00h.
DMA Interval Register (DEh, 5Eh) (R/W)
D7
D6
D5
D4
D3
D2
D1
D0
This register specifies a DMA transfer interval between de-assertion and re-assertion of DREQ in
Single Transfer mode. The interval is specified between 0 and 255 (bit times). The initial value is 0.
1-bit time = 1/12 MHz (= 84 ns)
13/44
¡ Semiconductor
ML60851A
Endpoint 0 Receive Control Register (E0h, –)
D7
D6
D5
D4
D3
D2
D1
RFU
0
0
0
0
0
RFU
D0
Configuration Bit (R)
Transfer Type (R)
Endpoint Address (R)
Configuration Bit: Only when this bit is asserted ("1"), a packet transmitted from a host computer
to this EP is received. The packet is ignored when this bit is deasserted ("0").
This bit is deasserted by system reset and is asserted by USB reset (both D+ and D- are 0s for more
than 2.5 ms).
Endpoint 0 Receive General Register (E1h, –)
D7
D6
D5
D4
D3
D2
D1
D0
RFU
Data Sequence
Toggle Bit (R)
Endpoint 0 Receive Payload Register (E2h, 62h)
D7
RFU
D6
D5
D4
D3
D2
D1
D0
Maximum Packet Size (R/W)
14/44
¡ Semiconductor
ML60851A
Endpoint 1 Control Register (E4h, 64h)
Register to set the attribute of EP1.
To use EP1, the local MCU writes EP1's attribute in this register by the request from the host
computer.
D7
D6
D5
D4
D3
D2
0
0
1
1
0
D1
D0
Configuration Bit (R/W)
Stall Bit (R/W)
10 = Bulk Transfer
Transfer Type (R)
Endpoint Address (R)
0 = Reception (OUT endpoint) (Supports printer)
Transfer Direction (R/W)
1 = Transmission (IN endpoint) (Supports scanner, DSC)
Configuration Bit: Only when this bit is asserted ("1"), a packet transmitted from the host computer
to this EP is received. The packet is ignored when this bit is deasserted ("0").
Whether or not this EP is configured can be known by referencing this bit.
Stall Bit: When this bit is asserted ("1"), a stall handshake for a packet transmitted from the host
computer to this EP is automatically returned to the host computer.
Endpoint 1 General Register (E5h, 65h)
D7
D6
D5
D4
D3
D2
D1
D0
RFU
Data Sequence
Toggle Bit (R/Reset)
Data Sequence Toggle Bit: When initializing EP, PID of DATA0 is specified after resetting the Data
Packet Toggle bit by writing "1" to this bit (this bit goes to "0").
Endpoint 1 Payload Register (E6h, 66h)
D7
RFU
D6
D5
D4
D3
D2
D1
D0
Maximum packet size (R/W)
15/44
¡ Semiconductor
ML60851A
Endpoint 3 Control Register (F8h, 78h)
Register to set the attribute of EP3.
To use EP3, the local MCU writes EP3's attribute in this register by the request from the host
computer.
D7
D6
D5
D4
D3
D2
0
1
1
1
1
D1
D0
Configuration Bit (R/W)
Stall Bit (R/W)
11 = Interrupt Transfer
Transfer Type (R)
Endpoint Address (R)
0 = Number
Toggle Condition (R/W)
1 = Rate Feedback Mode
Configuration Bit: Only when this bit is asserted ("1"), a packet transmitted from the host computer
to this EP is received. The packet is ignored when this bit is deasserted ("0").
Whether or not this EP is configured can be known by referencing this bit.
Stall Bit: When this bit is asserted ("1"), a stall handshake for a packet transmitted from the host
computer to this EP is automatically returned to the host computer.
Toggle Condition Bit: When this bit is "0", DATA0 and DATA1 are toggled each time ACK is
received form the host computer by the EP3. Setting this bit to "1" causes the ML60851A to go
into the rate feedback mode, in which case DATA0 and DATA1 are toggled each time the packet
ready is asserted by the local MCU.
Endpoint 3 General Register (F9h, 79h)
D7
D6
D5
D4
D3
D2
D1
D0
RFU
Data Sequence
Toggle Bit (R/Reset)
Data Sequence Toggle Bit: When initializing EP, PID of DATA0 is specified after resetting the Data
Packet Toggle bit by writing "1" to this bit (this bit goes to "0").
Endpoint 3 Payload Register (FAh, 7Ah)
D7
RFU
D6
D5
D4
D3
D2
D1
D0
Maximum packet size (R/W)
16/44
¡ Semiconductor
ML60851A
Endpoint 0 Transmit Control Register (F0h, –)
D7
D6
D5
D4
RFU
D3
D2
0
0
D1
D0
RFU
Transfer Type (R)
Endpoint 0 Transmit General Register (F1h, –)
D7
D6
D5
D4
D3
D2
D1
D0
RFU
Data Sequence
Toggle Bit (R)
Endpoint 0 Transmit Payload Register (F2h, 72h)
D7
D6
D5
RFU
D4
D3
D2
D1
D0
D1
D0
Maximum Packet Size (R/W)
Endpoint 0 Transmit General Register (F3h, 73h)
D7
D6
RFU
D5
D4
D3
D2
RFU
Setup Ready (R/Reset)
Stall Bit (R/W)
EP0 Stage (R)
00 = Setup Stage
01 = Data Stage
10 = Status Stage
Setup Ready: When a valid setup packet has arrived at an 8-byte setup register, this register is
automatically set and the receive FIFO at endpoint 0 is locked. Writing "1" in this register resets Setup
Ready. When the data stage of Control Write transaction follows, Packet Ready at endpoint 0 is also
reset. Therefore, the endpoint 0 receive FIFO is unlocked and ready to receive the packets in the data
stage.
The value of this register remains unchanged when "0" is written in this register.
17/44
¡ Semiconductor
ML60851A
Endpoint 2 Control Register (F4h, 74h)
D7
D6
D5
D4
D3
D2
0
1
0
1
0
D1
D0
Configuration Bit (R/W)
Stall Bit (R/W)
10 = Bulk Transfer
Transfer Type (R)
Endpoint Address (R)
0 = Reception (OUT endpoint)
Transfer Direction (R/W)
1 = Transmission (IN endpoint)
Configuration Bit: Only when this bit is asserted ("1"), a packet transmitted from the host computer
to this EP is received. The packet is ignored when this bit is deasserted ("0").
Whether or not this EP is configured can be known by referencing this bit.
Stall Bit: When this bit is asserted ("1"), a stall handshake for a packet transmitted from the host
computer to this EP is automatically returned to the host computer.
Endpoint 2 General Register (F5h, 75h)
D7
D6
D5
D4
D3
D2
D1
D0
RFU
Data Sequence
Toggle Bit (R/Reset)
Data Sequence Toggle Bit: When initializing EP, PID of DATA0 is specified after resetting the Data
Packet Toggle bit by writing "1" to this bit (this bit goes to "0").
Endpoint 2 Payload Register (F6h, 76h)
D7
RFU
D6
D5
D4
D3
D2
D1
D0
Maximum Packet Size (R/W)
18/44
¡ Semiconductor
ML60851A
Endpoint 0 Receive FIFO Data (40h, –)
D7
D6
D5
D4
D3
D2
D1
D0
Endpoint 0 Receive FIFO Data (R)
Area to store data to be transmitted from the host computer to this device in the data stage of Control
Write transfer.
Endpoint 1 Receive FIFO Data (41h, –)
D7
D6
D5
D4
D3
D2
D1
D0
Endpoint 1 Receive FIFO Data (R)
Area to store data to be transmitted from the host computer to EP1 of this device in Bulk Out transfer.
This register is valid only when EP1 is set for the OUT endpoint.
Endpoint 2 Receive FIFO Data (42h, –)
D7
D6
D5
D4
D3
D2
D1
D0
Endpoint 2 Receive FIFO Data (R)
Area to store data to be transmitted from the host computer to EP2 of this device in Bulk Out transfer.
This register is valid only when EP2 is set for the OUT endpoint.
19/44
¡ Semiconductor
ML60851A
Endpoint 0 Transmit FIFO Data (–, C0h)
D7
D6
D5
D4
D3
D2
D1
D0
Endpoint 0 Transmit FIFO Data (W)
Area to store data to be transmitted from this device to the host computer in the data stage of Control
Read transter.
Endpoint 1 Transmit FIFO Data (–, C1h)
D7
D6
D5
D4
D3
D2
D1
D0
Endpoint 1 Transmit FIFO Data (W)
Area to store data to be transmitted from EP1 of this device to the host computer in Bulk In transfer.
This register is valid only when EP1 is set for the IN endpoint.
Endpoint 2 Transmit FIFO Data (–, C2h)
D7
D6
D5
D4
D3
D2
D1
D0
Endpoint 2 Transmit FIFO Data (W)
Area to store data to be transmitted from EP2 of this device to the host computer in Bulk In transfer.
This register is valid only when EP2 is set for the IN endpoint.
Endpoint 3 Transmit FIFO Data (–, C3h)
D7
D6
D5
D4
D3
D2
D1
D0
Endpoint 3 Transmit FIFO Data (W)
Area to store data to be transmitted from EP3 of this device to the host computer in Bulk In transfer.
This register is valid only when EP3 is set for the IN endpoint.
20/44
¡ Semiconductor
ML60851A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Power Supply 3
VCC3
—
–0.3 to +4.6
V
Power Supply 5
VCC5
—
–0.5 to +6.5
V
VI
—
–0.3 to VCC5 + 0.3
V
TSTG
—
–55 to +150
°C
Input Voltage
Storage Temperature
RECOMMENDED OPERATING CONDITIONS
Symbol
Condition
Range
Unit
Power Supply 3
Parameter
VCC3
—
3.0 to 3.6
V
Power Supply 5
VCC5
—
3.0 to 5.5
V
Ta
—
0 to 70
°C
FOSC
—
48
MHz
Operating Temperature
Oscillation Frequency
21/44
¡ Semiconductor
ML60851A
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VCC5 = VCC3 = 3.0 to 3.6 V, VSS = 0 V, Ta = 0 to 70°C)
Parameter
High-level Input
Voltage
Low-level Input
Voltage
High-level Input
Voltage
Low-level Input
Voltage
Schmitt Trigger
Input Voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
VIH
—
2.0
—
VCC5 + 0.3
V
Applicable pin
Note 1
VIL
—
–0.3
—
+0.8
V
VIH
—
VCC3 ¥ 0.8
—
VCC3 + 0.3
V
VIL
—
–0.3
—
VCC3 ¥ 0.2
V
Vt+
—
—
1.6
2.0
V
Vt–
—
0.8
1.2
—
V
XIN
RESET
DVt
(Vt+) – (Vt–)
0.1
0.4
—
V
VOH
IOH = –100 mA
IOH = –4 mA
VCC5 – 0.2
—
—
V
2.4
—
—
V
IOL = 100 mA
—
—
0.2
V
IOL = 4 mA
—
—
0.4
V
IIH
VIH = VCC5
—
0.01
1
mA
IIL
VIL = VSS
–1
–0.01
—
mA
3-state Output
IOZH
VOH = VCC5
—
0.01
1
mA
D15:D8
Leakage Current
IOZL
VOL = VSS
–1
–0.01
—
mA
AD7:AD0
Power Supply
ICC3
—
—
—
50
mA
VCC3
Current (Operating)
ICC5
—
—
—
5
mA
VCC5
Power Supply
ICCS3
Note 3
—
—
50
mA
VCC3
Current (Standby)
ICCS5
Note 3
—
—
50
mA
VCC5
High-level
Output Voltage
Low-level
Output Voltage
High-level Input
Current
Low-level Input
Current
VOL
D15:D8
AD7:AD0
INTR, DREQ
Note 2
Notes: 1. Applied to D15:D8, AD7:AD0, A7:A0, CS, RD, WR, DACK, ALE, and ADSEL.
2. Applied to XIN, A7:A0, CS, RD, WR, DACK, ALE, and ADSEL. VIH = VCC3 for only XIN.
3. The XIN pin is fixed to High level or Low level in the suspend state. All the output
pins are open.
22/44
¡ Semiconductor
ML60851A
DC Characteristics (2)
(VCC5 = 4.5 to 5.5 V, VCC3 = 3.0 to 3.6 V, VSS = 0 V, Ta = 0 to 70°C)
Parameter
High-level Input
Voltage
Low-level Input
Voltage
Schmitt Trigger
Input Voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
VIH
—
2.2
—
VCC5 + 0.5
V
VIL
—
–0.5
—
+0.8
V
Vt+
—
—
1.7
2.2
V
Vt–
—
0.8
1.4
—
V
Applicable pin
Note 1
RESET
DVt
(Vt+) – (Vt–)
0.2
0.3
—
V
VOH
IOH = –100 mA
IOH = –8 mA
VCC5 – 0.2
—
—
V
3.7
—
—
V
IOL = 100 mA
—
—
0.2
V
IOL = 8 mA
—
—
0.4
V
IIH
VIH = VCC5
—
0.01
10
mA
IIL
VIL = VSS
–10
–0.01
—
mA
3-state Output
IOZH
VOH = VCC5
—
0.01
10
mA
D15:D8
Leakage Current
IOZL
VOL = VSS
–10
–0.01
—
mA
AD7:AD0
Power Supply
ICC3
—
—
—
50
mA
VCC3
Current (Operating)
ICC5
—
—
—
5
mA
VCC5
Power Supply
ICCS3
Note 3
—
—
50
mA
VCC3
Current (Standby)
ICCS5
Note 3
—
—
50
mA
VCC5
High-level
Output Voltage
Low-level
Output Voltage
High-level Input
Current
Low-level Input
Current
VOL
D15:D8
AD7:AD0
INTR, DREQ
Note 2
Notes: 1. Applied to D15:D8, AD7:AD0, A7:A0, CS, RD, WR, DACK, ALE, and ADSEL. The DC
characteristics (1) applies to XIN.
2. Applied to A7:A0, CS, RD, WR, DACK, ALE, and ADSEL. The DC characteristics (1)
applies to XIN.
3. The XIN pin is fixed to High level or Low level in the suspend state. All the output
pins are open.
23/44
¡ Semiconductor
ML60851A
DC Characteristics (3) USB Port
(VCC3 = 3.0 to 3.6 V, VSS = 0 V, Ta = 0 to 70°C)
Parameter
Differential Input
Sensitivity
Differential Common
Mode Range
Single Ended
Receiver Threshold
High-level Output
Voltage
Low-level Output
Voltage
Output Leakage
Current
Symbol
Condition
Min.
VDI
(D+) – (D–)
0.2
VCM
Includes VDI range
0.8
2.5
V
0.8
2.0
V
2.8
3.6
V
0.3
V
+10
mA
VSE
Typ.
Max.
Unit
Applicable pin
V
D+, D–
VOH
RL of 15 kW to VSS
VOL
RL of 1.5 kW to 3.6 V
ILO
0 V < VIN < 3.3 V
–10
AC Characteristics USB Port
(VCC3 = 3.0 to 3.6 V, VSS = 0 V, Ta = 0 to 70°C)
Condition
Parameter
Symbol
Rise Transition Time
tR
CL = 50 pF
Fall Transition Time
tF
CL = 50 pF
tRFM
(tR/tF)
Rise/Fall Time
Matching
Output Signal
Crossover Voltage
Driver Output
Resistance
Data Rate
(Notes 1. and 2.)
VCRS
ZDRV
tDRATE
Steady State Driver
Ava. Bit
Rate (12 Mb/s ±0.25%)
Min.
Typ.
Max.
Unit
4
25
ns
4
25
ns
90
140
%
1.2
2
V
28
43
W
11.97
12.03
Mbs
Applicable pin
D+, D–
Notes: 1. 1.5 kW pull-up to 2.8 V on the D+ data line.
2. Measured from 10% to 90% of the data signal.
24/44
¡ Semiconductor
ML60851A
TIMING DIAGRAM
READ Timing (1)
(Address Separate ADSEL = 0)
Parameter
Symbol
Condition
Min.
Max.
Unit
Note
Address Setup Time (RD)
t1 (RD)
21
—
ns
5
Address Setup Time (CS)
t1 (CS)
10
—
ns
5
0
—
ns
2
Load 20 pF
—
25
ns
1
0
—
ns
t5
FIFO READ
63
—
ns
3
t6
FIFO READ
42
—
ns
4
Address (CS) Hold Time
t2
Read Data Delay Time
t3
Read Data Hold Time
t4
Recovery Time
FIFO Access Time
Notes: 1.
2.
3.
4.
5.
t1 and t3 are defined depending upon CS or RD which becomes active last.
t2 is defined depending upon CS or RD which becomes active first.
3-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
2-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
Either of them should be met.
A7:A0
t1
t2
t6
CS
t5
RD
t3
t4
AD7:AD0
DATA OUT
25/44
¡ Semiconductor
ML60851A
READ Timing (2)
(Address/Data Multiplex ADSEL = 1)
Parameter
Symbol
Address (CS) Setup Time
Condition
t1
Min.
Max.
Unit
10
—
ns
Note
0
—
ns
Load 20 pF
—
25
ns
0
—
ns
t5
FIFO READ
63
—
ns
1
t6
FIFO READ
42
—
ns
2
Address (CS) Hold Time
t2
Read Data Delay Time
t3
Read Data Hold Time
t4
Recovery Time
FIFO Access Time
Notes: 1. 3-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
2. 2-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
AD7:AD0
ADDRESS
t1
DATA OUT
t2
t4
CS
ALE
t3
t5
RD
t6
26/44
¡ Semiconductor
ML60851A
WRITE Timing (1)
(Address Separate ADSEL = 0)
Parameter
Symbol
Condition
Min.
Max.
Unit
Note
Address Setup Time (WR)
t1 (WR)
21
—
ns
4
Address Setup Time (CS)
t1 (CS)
10
—
ns
4
Address (CS) Hold Time
t2
0
—
ns
CS Setup Time
t3
10
—
ns
Write Data Setup Time
t4
30
—
ns
Write Data Hold Time
t5
5
—
ns
Recovery Time
t6
FIFO WRITE
63
—
ns
2
FIFO Access Time
t7
FIFO WRITE
42
—
ns
3
Notes: 1.
2.
3.
4.
t1 is defined depending upon CS or WR which becomes active last.
3-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
2-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
Either of them should be met.
A7:A0
t1
t2
t7
CS
t3
t6
WR
t4
AD7:AD0
t5
DATA IN
27/44
¡ Semiconductor
ML60851A
WRITE Timing (2)
(Address/Data Multiplex ADSEL = 1)
Parameter
Symbol
Condition
Min.
Max.
Unit
Note
Address (CS) Setup Time
t1
10
—
ns
Address (CS) Hold Time
t2
0
—
ns
Write Data Setup Time
t3
30
—
ns
Write Data Hold Time
t4
5
—
ns
Recovery Time
t5
FIFO WRITE
63
—
ns
1
FIFO Access Time
t6
FIFO WRITE
42
—
ns
2
Notes: 1. 3-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
2. 2-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
AD7:AD0
ADDRESS
t1
DATA IN
t2
t4
CS
ALE
t3
t5
WR
t6
28/44
¡ Semiconductor
ML60851A
DMA Transfer Timing (1)
ML60851A to Memory (Single Transfer, Single Address Mode)
Symbol
Condition
Min.
Max.
Unit
DREQ Disable Time
Parameter
t1
Load 20 pF
—
20
ns
DREQ Enable Time
t2
—
63
ns
DACK Hold Time
t3
0
—
ns
Read Data Delay Time
t4
—
25
ns
Data Hold Time
t5
0
—
ns
Recovery Time
t6
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
Load 20 pF
Note
1
Notes: 1. When in Single Address mode, CS and A7:A0 are ignored.
t4 is defined depending on DACK or RD which becomes active last.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
DREQ
t1
t2
t3
DACK
t4
t6
RD
t5
DOUT
29/44
¡ Semiconductor
ML60851A
DMA Transfer Timing (2)
ML60851A to Memory (Single Transfer, Dual Address Mode)
Parameter
DREQ Disable Time
Symbol
Condition
Min.
Max.
Unit
t1
Load 20 pF
—
20
ns
—
63
ns
Load 20 pF
—
25
ns
0
—
ns
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
DREQ Enable Time
t2
Read Data Delay Time
t3
Data Hold Time
t4
Recovery Time
t5
Note
1
Notes: 1. When in Dual Address mode, the DACK is ignored.
t3 is defined depending on CS or RD which becomes active last.
A7:A0 specifies the FIFO address.
Refer to READ Timing (1) for Address Setup Time and Address Hold Time.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
A7:A0
DREQ
CS
t2
t1
t5
t3
RD
t4
DOUT
30/44
¡ Semiconductor
ML60851A
DMA Transfer Timing (3)
ML60851A to Memory (Demand Transfer, Single Address Mode)
Parameter
Symbol
Condition
Min.
DREQ Disable Time
t1
Load 20 pF
DACK Hold Time
t2
Read Data Delay Time
t3
Data Hold Time
t4
Recovery Time
t5
Max.
Unit
—
20
ns
0
—
ns
—
25
ns
0
—
ns
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
Load 20 pF
Note
1
Notes: 1. When in Single Address mode, t3 is defined depending on DACK or RD which becomes
active last.
A7:A0 and CS are ignored.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
DREQ
t1
DACK
t5
t2
RD
t3
t4
Last Packet Read
DOUT
31/44
¡ Semiconductor
ML60851A
DMA Transfer Timing (4)
ML60851A to Memory (Demand Transfer, Dual Address Mode)
Parameter
DREQ Disable Time
Symbol
Condition
Min.
Max.
Unit
t1
Load 20 pF
—
20
ns
0
—
ns
Load 20 pF
—
25
ns
0
—
ns
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
CS Hold Time
t2
Read Data Delay Time
t3
Data Hold Time
t4
Recovery Time
t5
Note
1
Notes: 1. When in Dual Address mode, the DACK is ignored.
t3 is defined depending on CS or RD which becomes active last.
A7:A0 specifies the FIFO address.
Refer to READ Timing (1) for Address Setup Time and Address Hold Time.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
A7:A0
DREQ
t1
CS
t5
t2
RD
t3
t4
Last Packet Read
DOUT
32/44
¡ Semiconductor
ML60851A
DMA Transfer Timing (5)
Memory to ML60851A (Single Transfer, Single Address Mode)
Symbol
Condition
Min.
Max.
Unit
DREQ Disable Time
Parameter
t1
Load 20 pF
—
20
ns
DREQ Enable Time
t2
—
63
ns
FIFO Access Time
t3
42
—
ns
DACK Hold Time
t4
0
—
ns
Write Data Setup Time
t5
30
—
ns
Write Data Hold Time
t6
Recovery Time
FIFO WRITE
t7
Note
1
5
—
ns
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
Notes: 1. When in Single Address mode, CS and A7:A0 are ignored.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
DREQ
t4
t1
t2
DACK
t3
t7
WR
t5
t6
DIN
33/44
¡ Semiconductor
ML60851A
DMA Transfer Timing (6)
Memory to ML60851A (Single Transfer, Dual Address Mode)
Symbol
Condition
Min.
Max.
Unit
DREQ Disable Time
Parameter
t1
Load 20 pF
—
20
ns
DREQ Enable Time
t2
—
63
ns
FIFO Access Time
t3
42
—
ns
Write Data Setup Time
t4
30
—
ns
Write Data Hold Time
t5
5
—
ns
Recovery Time
t6
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
FIFO WRITE
Note
1
Notes: 1. When in Dual Address mode, the DACK is ignored.
Refer to WRITE Timing (1) for Address Setup Time and Address Hold Time.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
A7:A0
DREQ
t2
t1
CS
t3
t6
WR
t5
t4
DIN
34/44
¡ Semiconductor
ML60851A
DMA Transfer Timing (7)
Memory to ML60851A (Demand Transfer, Single Address Mode)
Parameter
Symbol
Condition
Min.
Max.
Unit
t1
Load 20 pF
—
20
ns
FIFO Access Time
t2
FIFO WRITE
42
—
ns
DACK Hold Time
t3
0
—
ns
Write Data Setup Time
t4
30
—
ns
Write Data Hold Time
t5
5
—
ns
Recovery Time
t6
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
DREQ Disable Time
Note
1
Notes: 1. When in Single Address mode, A7:A0 and CS and ignored.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
DREQ
t1
DACK
t2
t6
t3
WR
(Note)
t4
t5
Last Packet Write
DIN
(Note) The last Write to reach the byte size (maximum packet size) specified by the EP1 Payload
Register.
To terminate DMA transfer before reaching the maximum packet size, set EP1 Packet Ready
by writing "1" to the EP1 Transmit Packet Ready bit.
35/44
¡ Semiconductor
ML60851A
DMA Transfer Timing (8)
Memory to ML60851A (Demand Transfer, Dual Address Mode)
Parameter
Symbol
Condition
Min.
Max.
Unit
t1
Load 20 pF
—
20
ns
FIFO Access Time
t2
FIFO WRITE
42
—
ns
CS Hold Time
t3
0
—
ns
Write Data Setup Time
t4
30
—
ns
Write Data Hold Time
t5
5
—
ns
Recovery Time
t6
8-bit DMA
63
—
ns
2
16-bit DMA
105
—
ns
3
DREQ Disable Time
Note
1
Notes: 1. When in Dual Address mode, the DACK is ignored.
A7:A0 specifies the FIFO address.
Refer to WRITE Timing (1) for Address Setup Time and Address Hold Time.
2. 3-clock time of oscillation clock (clock period: 21 ns).
3. 5-clock time of oscillation clock (clock period: 21 ns).
A7:A0
DREQ
t1
CS
t2
t3
t6
WR
(Note)
t4
t5
Last Packet Write
DIN
(Note) Refer to the previous page.
36/44
¡ Semiconductor
ML60851A
FUNCTIONAL DESCRIPTIONS
Pin Functional Description
USB Interface
Signal
Type Assertion
Description
USB data (Plus). This signal and the D– signal are the transmitted or received
data from/to USB Bus. The table below shows values and results for these signal.
D+
I/O
—
D+
D–
Result
0
0
Single end 0
0
1
Differential "0"
1
0
Differential "1"
1
1
Undefined
USB Data (Minus). This signal and the D+ signal are the transmitted or
D–
I/O
—
received data from/to USB Bus. The table above shows values and results for
these signals.
Crystal Oscillator Interface
Signal
XIN
XOUT
Type Assertion
I
O
—
—
Description
For internal oscillation, connect a crystal to XIN and XOUT.
For external oscillation, supply an external 48 MHz clock signal to XIN.
Set XOUT to be open.
37/44
¡ Semiconductor
ML60851A
Application Interface
Signal
D15:D8
Type Assertion
I/O
—
AD7:AD0
I/O
—
A7:A0
I
—
Description
Upper byte (MSB) of data bus. This data bus is used by applications to access
register files and FIFO data.
Lower byte (LSB) of data bus when ADSEL is LOW.
Address and lower byte of data bus are multiplexed when ADSEL is HIGH.
Address when ADSEL is LOW. This address signal is used by application to
access register files and FIFO data.
This signal is ignored (all lows or all highs) when ADSEL is HIGH.
CS
RD
WR
I
I
I
LOW
LOW
LOW
LOW
INTR
O
DREQ
O
DACK
I
ALE
I
—
ADSEL
I
—
(Note 1)
LOW
Chip Select. When this signal is asserted LOW, the ML60851A is selected
and ready to read or write data.
Read Strobe. When this signal is asserted LOW, the Read instruction is
executed.
Write Strobe. When this signal is asserted LOW, the Write instruction is
executed.
Interrupt Request. When this signal is asserted, the ML60851A makes an
interrupt request to the application.
DMA Request. This signal requests the Endpoint FIFO to make a DMA transfer.
(Note 1)
HIGH
(Note 1)
DMA Acknowledge Signal. This signal, when asserted, enables accessing
FIFOs, without address bus setting.
When ADSEL is HIGH, the address and CS on AD7:AD0 is latched at the
trailing edge of this signal. This signal is ignored when ADSEL is LOW.
When ADSEL is LOW, the address is input on A7:A0 and data i input on
D15:D8 and AD7:AD0. When ADSEL is HIGH, the lower bytes (LSB) of
address and data are multiplexed on AD7:AD0.
RESET
I
LOW
System Reset. When this signal is asserted LOW, the ML60851A is reset.
When the ML60851A is powered on, this signal must be asserted for 1 ms.
Note: 1. Initial value immediately after resetting. Its assertion can be changed by programming.
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ML60851A
Functional Description
The ML60851A USB device controller contains the Protocol Engine, DPLL, Timer, Status/Control,
FIFO Control, Application Interface, and Remote Wakeup blocks.
• Protocol Engine
The Protocol Engine handles the USB communication protocol. It performs control of packet
transmission/reception, generation/detection of synchronous patterns, CRC generation/checking,
NRZI data modulation, bit stuffing, and packet ID (PID) generation/checking.
• DPLL (Digital Phase Locked Loop)
The DPLL extracts clock and data from the USB differential received data (D+ and D–).
• Timer
The Timer block monitors idle time on the USB bus.
• Status/Control
The Status Control block moniors the transaction status and transmits control events to the
application through an interrupt request.
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• FIFO Control
The FIFO Control block controls all FIFO operations for transmitting and receiving USB packets.
The FIFO configuration is described below.
Endpoint FIFO/8-Byte Setup Register Configuration
For Control Transfer
8-Byte
Endpoint Address 0
Setup Register
Setup Ready
8-Byte
Endpoint Address 0
EP0 Receive FIFO
FIFO Rx
Packet Ready
8-Byte
Endpoint Address 0
EP0 Transmit FIFO
FIFO Tx
Packet Ready
For Bulk Transfer
64-Byte
FIFO
Packet Ready
EP1 FIFO (128 bytes)
DMA Request
(Selectable for transmitter
or receiver)
64-Byte
Endpoint Address 1
FIFO
EP2 FIFO (64 bytes)
64-Byte
Endpoint Address 2
(Selectable for transmitter
FIFO
or receiver)
Packet Ready
8-Byte
Endpoint Address 3
EP3 FIFO (8 bytes)
FIFO
Packet Ready
FIFO type
Endpoint address
Function
Program size
Reception
0
8 Bytes
Transfer control
Transmission
0
8 Bytes
Transfer control
Reception/Transmission
1
64 Bytes (2 levels)
Bulk-In and bulk-Out
Reception/Transmission
2
64 Bytes
Bulk-Out and bulk-In
Transmission
3
8 Bytes
Interrupt
Every FIFO has a flag that indicates a full or empty FIFO and the capability of re-transmitting and
re-receiving data. Endpoint addresses 1 and 2 can be used for either of reception and transmission
by writing the register.
The FIFO at endpoint address 1 can be used for DMA transfer.
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ML60851A
• Interrupt
Interrupt factors include Packet Ready for a transmit/receive FIFO, Setup Ready for 8-byte setup
data, and Suspend. Generation of each interrupt request can be enabled or disabled by the
Interrupt Enable register.
• DMA
8-bit and 16-bit demand transfer DMA and single transfer DMA are enabled for bulk-transfer FIFO
at endpoint address 1.
In Demand Transfer mode, DREQ is asserted when a valid packet arrives at the FIFO. When the
external DMA contoller has completed transferring all byte data of a received packet, DREQ is
deasserted. Accordingly, other devices cannot access the local bus during DMA transfer.
In Single Tranfer mode, each time transfer of one byte data is completed, DREQ is deasserted.
While DREQ is deasserted, other devices can access the local bus.
• Remote Wakeup
This functional block supports the remote wakeup function.
• USB Transfers
The ML60851A supports the two transfer types (Control Transfer and Bulk Transfer) of four
transfer types (Control, Isochronous, Interrupt, and Bulk) defined by the USB Specifications.
- The Control Transfer is required for transfer of configuration, commands, and status information
between the host and devices.
- The Bulk Transfer enables transfer of a large amount of data when the bus bandwidth is enough.
• USB Transceiver
The ML60851A contains an Oki's USB transceiver which converts internal unidirectional signals
into USB-compatible signals.
This enables the designer's application module to interface to the physical layer of the USB.
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ML60851A
EXAMPLE OF OSCILLATOR CIRCUIT
ML60851A
XIN
Rf
C2
XOUT
C3
L1
Crystal: HC-49U (KINSEKI, LTD)
C2 = 5 pF
C3 = 1000 pF
Rf = 1 MW
L1 = 2.2 mF
Note: The example indicated above is not guaranteed for circuit operation.
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ML60851A
PACKAGE DIMENSIONS
(Unit : mm)
QFP44-P-910-0.80-2K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Epoxy resin
42 alloy
Solder plating
5 mm or more
Package weight (g)
0.41 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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ML60851A
(Unit : mm)
TQFP44-P-1010-0.80-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.28 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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E2Y0002-28-41
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1998 Oki Electric Industry Co., Ltd.
Printed in Japan