OKI MSM51V16405F

FEDD51V16405F-02
Issue Date: Aug. 16, 2002
OKI Semiconductor
MSM51V16405F
4,194,304-Word × 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM51V16405F is a 4,194,304-word × 4-bit dynamic RAM fabricated in Oki’s silicon-gate
CMOS technology. The MSM51V16405F achieves high integration, high-speed operation, and
low-power consumption because Oki manufactures the device in a quadruple-layer
polysilicon/double-layer metal CMOS process. The MSM51V16405F is available in a 26/24-pin plastic
TSOP.
FEATURES
· 4,194,304-word × 4-bit configuration
· Single 3.3V power supply, ±0.3V tolerance
· Input : LVTTL compatible, low input capacitance
· Output : LVTTL compatible, 3-state
· Refresh : 4096 cycles/64ms
· Fast page mode with EDO, read modify write capability
· CAS before RAS refresh, hidden refresh, RAS-only refresh capability
· Packages
26/24-pin 300mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM51V16405F-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Family
MSM51V16405F
tRAC
tAA
tCAC
tOEA
Cycle Time
(Min.)
50ns
60ns
70ns
25ns
30ns
35ns
13ns
15ns
20ns
13ns
15ns
20ns
84ns
104ns
124ns
Power Dissipation
Operating
(Max.)
360mW
324mW
288mW
Standby
(Max.)
1.8mW
1/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
PIN CONFIGURATION (TOP VIEW)
VCC 1
26 VSS
DQ1 2
25 DQ4
DQ2 3
24 DQ3
WE 4
23 CAS
RAS 5
22 OE
A11R 6
21 A9
A10R 8
A0 9
19 A8
A1 10
17 A6
A2 11
16 A5
A3 12
15 A4
VCC 13
14 VSS
18 A7
26/24-Pin Plastic TSOP
(K Type)
Pin Name
Function
A0–A9, A10R, A11R
Address Input
RAS
Row Address Strobe
CAS
Column Address Strobe
DQ1–DQ4
Data Input/Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (3.3V)
VSS
Ground (0V)
NC
No Connection
Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must
be provided to every VSS pin.
2/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
BLOCK DIAGRAM
Timing
Generator
RAS
Timing
Generator
CAS
10
Column
Address
Buffers
10
10
A10R , A11R 2
Row
Address
Buffers
Column Decoders
OE
4
Internal
Address
Counter
A0 − A9
WE
Write
Clock
Generator
Refresh
Control Clock
Sense Amplifiers
4
I/O
Selector
Row
Decoders
Word
Drivers
4
4
4
4
12
Output
Buffers
Input
Buffers
DQ1 − DQ4
4
Memory
Cells
VCC
On Chip
VBB Generator
VSS
3/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on Any Pin Relative to VSS
VIN, VOUT
–0.5 to VCC+ 0.5
V
Voltage VCC Supply relative to VSS
VCC
–0.5 to 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–55 to 150
°C
*: Ta = 25°C
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70°C)
Parameter
Power Supply Voltage
Symbol
Min.
Typ.
Max.
Unit
VCC
3.0
3.3
3.6
V
VSS
0
0
0
Input High Voltage
VIH
2.0

Input Low Voltage
VIL
− 0.3*2

V
*1
VCC + 0.3
0.8
V
V
Notes: *1. The input voltage is VCC + 1.0V when the pulse width is less than 20ns (the pulse width is with respect
to the point at which VCC is applied).
*2. The input voltage is VSS − 1.0V when the pulse width is less than 20ns (the pulse width respect to the
point at which VSS is applied).
PIN CAPACITANCE
(Vcc = 3.3V ± 0.3V, Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Min.
Min.
Unit
CIN1
—
5
pF
(RAS, CAS, WE, OE)
CIN2
—
7
pF
Output Capacitance (DQ1 – DQ4)
CI/O
—
7
pF
Input Capacitance (A0 – A9, A10R, A11R)
Input Capacitance
4/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
DC CHARACTERISTICS
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C)
Parameter
Symbol
Condition
Min.
Max.
Min.
Max.
Min.
Max.
2.4
VCC
2.4
VCC
2.4
VCC
V
0
0.4
0
0.4
0
0.4
V
All other pins not
under test = 0V
− 10
10
− 10
10
− 10
10
µA
DQ disable
− 10
10
− 10
10
− 10
10
µA

75

70

65
mA
1,2
RAS, CAS = VIH

2

2

2
RAS, CAS
≥ VCC − 0.2V


1
0.5

mA
0.5
0.5

75

70

65
mA
1,2

5

5

5
mA
1

75

70

65
mA
1,2

100

90

80
mA
1,3
Output High Voltage
VOH
IOH = −2.0mA
Output Low Voltage
VOL
IOL = 2.0mA
0V ≤ VI ≤ VCC+0.3V;
Input Leakage
Current
ILI
Output Leakage
Current
ILO
Average Power
Supply Current
ICC1
(Operating)
Power Supply
Current
ICC2
(Standby)
Average Power
Supply Current
ICC3
(CAS before RAS
Refresh)
Average Power
Supply Current
(Fast Page Mode)
RAS, CAS cycling,
tRC = Min.
CAS = VIH,
tRC = Min.
RAS = VIH,
ICC5
(Standby)
Average Power
Supply Current
0V ≤ VO ≤ VCC
RAS cycling,
(RAS-only Refresh)
Power Supply
Current
MSM51V16405 MSM51V16405 MSM51V16405
F-50
F-60
F-70
Unit Note
CAS = VIL,
DQ = enable
ICC6
RAS = cycling,
CAS before RAS
RAS = VIL,
ICC7
CAS cycling,
tHPC = Min.
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
5/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
AC CHARACTERISTICS (1/3)
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3,12,13
Parameter
MSM51V16405
F-50
Symbol
MSM51V16405
F-60
MSM51V16405
F-70
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
tRC
84

104

124

ns
Read Modify Write Cycle Time
tRWC
110

135

160

ns
Fast Page Mode Cycle Time
tHPC
20

25

30

ns
Fast Page Mode Read Modify Write
tHPRWC
Cycle Time
58

68

78

ns
Access Time from RAS
tRAC

50

60

70
ns
4, 5, 6
Access Time from CAS
tCAC

13

15

20
ns
4,5
Access Time from Column Address
tAA

25

30

35
ns
4,6
Access Time from CAS Precharge
tCPA

30

35

40
ns
4
Access Time from OE
tOEA

13

15

20
ns
4
Output Low Impedance Time from
CAS
tCLZ
0

0

0

ns
4
Data Output Hold After CAS Low
tDOH
5

5

5

ns
CAS to Data Output Buffer Turnoff Delay Time
tCEZ
0
13
0
15
0
20
ns
7,8
RAS to Data Output Buffer Turnoff Delay Time
tREZ
0
13
0
15
0
20
ns
7,8
OE to Data Output Buffer Turn-off
Delay Time
tOEZ
0
13
0
15
0
20
ns
7
WE to Data Output Buffer Turnoff Delay Time
tWEZ
0
13
0
15
0
20
ns
7
Transition Time
tT
1
50
1
50
1
50
ns
3
Refresh Period
tREF

64

64

64
ms
RAS Precharge Time
tRP
30

40

50

ns
RAS Pulse Width
tRAS
50
10,000
60
10,000
70
10,000
ns
RAS Pulse Width
(Fast Page Mode with EDO)
tRASP
50
100,000
60
100,000
70
100,000
ns
RAS Hold Time
tRSH
7

10

13

ns
RAS Hold Time referenced to OE
tROH
7

10

13

ns
CAS Precharge Time
(Fast Page Mode with EDO)
tCP
7

10

10

ns
CAS Pulse Width
tCAS
7
10,000
10
10,000
13
10,000
ns
CAS Hold Time
tCSH
35

40

45

ns
Random Read or Write Cycle Time
6/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
AC CHARACTERISTICS (2/3)
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3,12,13
Parameter
MSM51V16405
F-50
Symbol
MSM51V16405
F-60
MSM51V16405
F-70
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
5

5

5

ns
RAS Hold Time from CAS Precharge tRHCP
30

35

40

ns
OE Hold Time from CAS
(DQ Disable)
tCHO
5

5

5

ns
RAS to CAS Delay Time
tRCD
11
37
14
45
14
50
ns
5
RAS to Column Address Delay Time
tRAD
9
25
12
30
12
35
ns
6
Row Address Set-up Time
tASR
0

0

0

ns
Row Address Hold Time
tRAH
7

10

10

ns
Column Address Set-up Time
tASC
0

0

0

ns
Column Address Hold Time
tCAH
7

10

13

ns
Column Address to RAS Lead Time
tRAL
25

30

35

ns
Read Command Set-up Time
tRCS
0

0

0

ns
Read Command Hold Time
tRCH
0

0

0

ns
9
Read Command Hold Time
referenced to RAS
tRRH
0

0

0

ns
9
Write Command Set-up Time
tWCS
0

0

0

ns
10
Write Command Hold Time
tWCH
7

10

13

ns
Write Command Pulse Width
tWP
7

10

10

ns
WE Pulse Width (DQ Disable)
tWPE
7

10

10

ns
OE Command Hold Time
tOEH
7

10

13

ns
OE Precharge Time
tOEP
7

10

10

ns
OE Command Hold Time
tOCH
7

10

10

ns
Write Command to RAS Lead Time
tRWL
7

10

13

ns
Write Command to CAS Lead Time
tCWL
7

10

13

ns
Data-in Set-up Time
tDS
0

0

0

ns
11
Data-in Hold Time
tDH
7

10

13

ns
11
OE to Data-in Delay Time
tOED
13

15

20

ns
CAS to WE Delay Time
tCWD
30

34

44

ns
10
Column Address to WE Delay Time
tAWD
42

49

59

ns
10
RAS to WE Delay Time
tRWD
67

79

94

ns
10
CAS Precharge WE Delay Time
tCPWD
47

54

64

ns
10
CAS to RAS Precharge Time
tCRP
7/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
AC CHARACTERISTICS (3/3)
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3,12,13
Parameter
MSM51V16405
F-50
Symbol
MSM51V16405
F-60
MSM51V16405
F-70
Min.
Max.
Min.
Max.
Min.
Max.
Unit
CAS Active Delay Time from RAS
Precharge
tRPC
5

5

5

ns
RAS to CAS Set-up Time
(CAS before RAS)
tCSR
5

5

5

ns
RAS to CAS Hold Time
(CAS before RAS)
tCHR
10

10

10

ns
WE to CAS Hold Time
(CAS before RAS)
tWRP
10

10

10

ns
WE Hold Time from RAS
(CAS before RAS)
tWRH
10

10

10

ns
RAS to WE Set-up Time
(Test Mode)
tWTS
10

10

10

ns
RAS to WE Hold Time (Test Mode)
tWTH
10

10

10

ns
Note
8/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2. The AC characteristics assume tT = 2ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT)
are measured between VIH and VIL.
4. -50 is measured with a load circuit equivalent to 1 TTL load and 50pF, and -60/-70 is measured with a
load circuit equivalent to 1 TTL load and 100pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit,
then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit,
then the access time is controlled by tAA.
7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.), and tOEZ (Max.) define the time at which the output achieved the
open circuit condition and are not referenced to output voltage levels.
8. tCEZ, and tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and
the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD
(Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify
write cycle and data out will contain data read from the selected cell; if neither of the above sets of
conditions is satisfied, then the condition of the data out (at access time) is indeterminate.
11. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. In a test CA8 and CA9 are not used and
each DQ pin now access 4-bit locations. Since all 4 DQ pins are used, a total 16 data bits can be written
in parallel into the memory array. In a read cycle, if 4 data bits are equal, the DQ pin will indicate a
high level. If the 4 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared
and the memory device returned to its normal operating state by performing a RAS-only refresh cycle
or a CAS before RAS refresh cycle.
13. In a test mode read cycle, the value of access time parameter is delayed for 5ns for the specified value.
These parameters should be specified in test mode cycle by adding the above value to the specified
value in this data sheet.
9/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
TIMING CHART
Read Cycle
RAS
tRC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRCD
VIH
tRAD
VIL
tRAL
tASR
Address
WE
tCRP
tRSH
tCAS
VIH
tRAH
tASC
Row
VIL
tCAH
Column
tRCS
tRRH
VIH
tAA
VIL
tRCH
tROH
tREZ
tOEA
OE
VIH
VIL
tCAC
tRAC
DQ
tCEZ
tOEZ
tCLZ
VOH
Valid Data-out
Open
VOL
“H” or “L”
Write Cycle (Early Write)
tRC
tRAS
RAS
VIH
tRP
VIL
tCSH
tCRP
CAS
VIH
tRAD
VIL
tRAL
tASR
Address
VIH
VIL
tRAH
tASC
Row
OE
tCWL
VIH
tWCH
tWP
VIL
tRWL
VIH
VIL
tDS
DQ
tCAH
Column
tWCS
WE
tCRP
tRSH
tCAS
tRCD
VIH
VIL
tDH
Valid Data-in
Open
“H” or “L”
10/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
Read Modify Write Cycle
tRWC
tRAS
RAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tCRP
tRSH
tCAS
VIH
tRAD
VIL
tASR
Address
tRCD
VIH
VIL
tRAH
Row
tCWL
tRWL
tCAH
tASC
Column
tCWD
tRCS
tRWD
WE
OE
tWP
VIH
VIL
tAWD
tAA
tOEH
tOEA
VIH
tOED
VIL
tDH
tCAC
tRAC
DQ
VI/OH
VI/OL
tOEZ
tCLZ
Valid
Data-out
tDS
Valid
Data-in
“H” or “L”
11/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
Fast Page Mode Read Cycle (Part-1)
tRASP
tRCD
RAS
Address
tRHCP
VIH
VIL
tCSH
tCRP
CAS
tRP
tHPC
tCP
tCP
tCAS
tCAS
tCAS
VIH
VIL
VIH
VIL
tRAD
tASR
tRAH
tASC
Row
tCAH
tASC
Column
tASC
tCAH
Column
Column
tRCS
WE
OE
tOCH
tRRH
VIH
tAA
VIL
tCAC
tRAC
tAA
VIH
VIL
tCAC
tOEP
tOEA
tOEA
tOEZ
tOEZ
tDOH
VOH
Valid Data-out
VOL
tCAC
tAA
tCHO
tOEP
tCPA
tOEA
DQ
tCAH
Valid
Data-out
tREZ
Valid *
Data-out
Valid *
Data-out
tCLZ
* : Same Data,
“H” or “L”
Fast Page Mode Read Cycle (Part-2)
tRP
tRASP
tRHCP
tHPC
RAS
CAS
Address
VIH
VIL
tCRP
tCSH
tRCD
VIH
VIL
tCAS
OE
tCAS
tRAD
tASR
tRAH
Row
tASC
tCAH
tCAH
tASC
Column
Column
tRCS
WE
tCP
tCAS
VIH
VIL
tCRP
tHPC
tCP
tASC
tCAH
Column
tRCS
VIH
VIL
tAA
tRAC
VIH
tRCH
tWPE
tOEA
tAA
tCPA
tAA
tCAC
tDOH
VIL
tCAC
tCAC
DQ
VOH
VOL
tWEZ
Valid
Data-out
Valid Data-out
tCEZ
Valid
Data-out
tCLZ
“H” or “L”
12/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
tCSH
RAS
tHPC
VIH
VIL
tCRP
tRCD
tCP
tCP
tCAS
CAS
Address
OE
VIL
VIH
VIL
tRAD
tASR
tASC
tRAH
Row
tASC
tCAH
Column
tASC
tCAH
Column
tWCS
tWCH
tCAH
Column
tWCS
tWCH
tWCH
VIH
VIL
VIH
VIL
tDS
DQ
tRSH
tCAS
tCAS
VIH
tWCS
WE
tHPC
VIH
tDH
tDS
Valid
Data-in
VIL
tDH
tDS
tDH
Valid
Data-in
Valid
Data-in
“H” or “L”
Fast Page Mode Read Modify Write Cycle
tRASP
tRWD
RAS
VIH
VIL
tCRP
tCPWD
tRCD
tCP
tRWL
tCWD
CAS
VIH
tASR
Address
VIH
VIL
tASC
tASC
tRAD
VIL
tHPRWC
tRAH
Row
Column
Column
tRCS
WE
VIH
VIL
tCAH
tCPA
tCWL
tCAH
tCWD
tRCS
tAWD
tAWD
tAA
tWP
tDS
tRAC
tAA
VIH
tOED
VIL
tCAC
DQ
VI/OH
VI/OL
tCLZ
tWP
tOEA
tOEA
OE
tDS
tOED
tOEH
tOEZ
tDH
Valid
Data-out
Valid
Data-in
tCAC
tOEH
tOEZ
Valid
Data-out
tDH
Valid
Data-in
tCLZ
“H” or “L”
13/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
RAS-only Refresh Cycle
tRC
RAS
CAS
Address
tRAS
VIH
VIL
tRP
tRPC
tCRP
VIH
VIL
tASR
VIH
tRAH
Row
VIL
tCEZ
DQ
VOH
Open
VOL
Note: WE, OE = “H” or “L”
“H” or “L”
CAS before RAS Refresh Cycle
tRP
RAS
tRC
tRAS
VIH
VIL
tRPC
tCP
tRP
tCSR
tRPC
tCHR
CAS
WE
VIH
VIL
tWRP
tWRH
tWRP
VIH
VIL
tCEZ
DQ
VOH
VOL
Open
Note: OE, Address = “H” or “L”
“H” or “L”
14/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
Hidden Refresh Read Cycle
tRC
tRC
tRAS
RAS
tRAS
VIH
VIL
tCRP
tRCD
tRSH
tRP
tRP
tCHR
CAS
VIH
tRAD
VIL
tRAH
tASR
Address
VIH
tASC
Row
VIL
tCAH
Column
tRCS
WE
tCAC
VIH
VIL
tRAL
tREZ
tAA
tROH
OE
DQ
tRRH
tWRP tWRH
tCEZ
tOEA
VIH
VIL
tRAC
tOEZ
tCLZ
VOH
Open
VOL
Valid Data-out
“H” or “L”
Hidden Refresh Write Cycle
tRC
tRC
tRAS
RAS
tRAS
VIH
VIL
tCRP
tRCD
tRSH
tRP
tRP
tCHR
CAS
VIH
tRAD
VIL
tASR
Address
VIH
VIL
tRAH
tASC
Row
tCAH
Column
tRAL
tRWL
tWP
WE
VIH
VIL
tWCS
OE
DQ
tWCH
tWRP
tWRH
VIH
VIL
VIH
tDS
tDH
Valid Data-in
VIL
“H” or “L”
15/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
Test Mode-in Cycle
tRC
tRP
RAS
tRAS
VIH
VIL
tRPC
tCP
tCSR
CAS
VIL
tWTS
WE
DQ
tCHR
VIH
tWTH
VIH
VIL
VIH
VIL
tOFF
Open
Note: OE, Address = “H” or “L”
“H” or “L”
16/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
REVISION HISTORY
Document
No.
Date
Page
Previous Current
Edition
Edition
FEDD51V16405F-01
May, 2001
–
–
FEDD51V16405F-02
Aug, 2002
1, 2
1, 2
Description
Final edition 1
Deleted SOJ package
17/18
FEDD51V16405F-02
1Semiconductor
MSM51V16405F
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that
the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special or
enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2002 Oki Electric Industry Co., Ltd.
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