Pr E2G0107-18-42 el im y 4,194,304-Word ¥ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM5116405C is a 4,194,304-word ¥ 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM5116405C achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5116405C is available in a 26/24-pin plastic SOJ or 26/24-pin plastic TSOP. FEATURES • 4,194,304-word ¥ 4-bit configuration • Single 5 V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 4096 cycles/64 ms • Fast page mode with EDO, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Multi-bit test mode capability • Package options: 26/24-pin 300 mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM5116405C-xxSJ) 26/24-pin 300 mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM5116405C-xxTS-K) (TSOPII26/24-P-300-1.27-L) (Product : MSM5116405C-xxTS-L) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA ar This version: Apr. 1998 MSM5116405C in ¡ Semiconductor MSM5116405C ¡ Semiconductor Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM5116405C-50 50 ns 25 ns 13 ns 13 ns 90 ns 550 mW MSM5116405C-60 60 ns 30 ns 15 ns 15 ns 110 ns 495 mW MSM5116405C-70 70 ns 35 ns 20 ns 20 ns 130 ns 440 mW 5.5 mW 1/18 , ¡ Semiconductor MSM5116405C PIN CONFIGURATION (TOP VIEW) VCC 1 26 VSS VCC 1 26 VSS VSS 26 1 VCC DQ1 2 25 DQ4 DQ1 2 25 DQ4 DQ4 25 2 DQ1 DQ2 3 24 DQ3 DQ2 3 24 DQ3 DQ3 24 3 DQ2 WE 4 23 CAS WE 4 23 CAS CAS 23 4 WE RAS 5 22 OE RAS 5 22 OE OE 22 5 RAS A11R 6 21 A9 A11R 6 21 A9 A9 21 6 A11R A10R 8 19 A8 A10R 8 19 A8 A8 19 8 A10R A0 9 18 A7 A0 9 18 A7 A7 18 9 A0 A1 10 17 A6 A1 10 17 A6 A6 17 10 A1 A2 11 16 A5 A2 11 16 A5 A5 16 11 A2 A3 12 15 A4 A3 12 15 A4 A4 15 12 A3 VCC 13 14 VSS VCC 13 14 VSS VSS 14 13 VCC 26/24-Pin Plastic SOJ 26/24-Pin Plastic TSOP (K Type) Pin Name A0 - A9, A10R, A11R Address Input Row Address Strobe CAS Column Address Strobe OE Note : Function RAS DQ1 - DQ4 26/24-Pin Plastic TSOP (L Type) Data Input/Data Output Output Enable WE Write Enable VCC Power Supply (5 V) VSS Ground (0 V) The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/18 ¡ Semiconductor MSM5116405C BLOCK DIAGRAM RAS Timing Generator Timing Generator CAS 10 Column Address Buffers 10 Write Clock Generator Column Decoders WE OE 4 Internal Address Counter A0 - A9 Refresh Control Clock Sense Amplifiers 4 I/O Selector A10R, A11R 2 Row Address Buffers 12 Row Decoders Word Drivers 4 4 4 4 10 Output Buffers Input Buffers DQ1 - DQ4 4 Memory Cells VCC On Chip VBB Generator On Chip IVCC Generator VSS 3/18 ¡ Semiconductor MSM5116405C ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN, VOUT –0.5 to VCC + 0.5 V Voltage on VCC Supply Relative to VSS VCC –0.5 to 7 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C *: Ta = 25°C Recommended Operating Conditions (Ta = 0°C to 70°C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V VIH 2.4 — VCC + 0.5*1 V VIL –0.5*2 — 0.8 V Notes : *1. The input voltage is VCC + 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS – 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VSS is applied). Capacitance (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit Input Capacitance (A0 - A9, A10R, A11R) Parameter CIN1 — 5 pF Input Capacitance (RAS, CAS, WE, OE) CIN2 — 7 pF Output Capacitance (DQ1 - DQ4) CI/O — 7 pF 4/18 ¡ Semiconductor MSM5116405C DC Characteristics Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol Condition Output High Voltage VOH IOH = –5.0 mA Output Low Voltage VOL IOL = 4.2 mA Input Leakage Current ILI MSM5116405 MSM5116405 MSM5116405 C-50 C-60 C-70 Unit Note Min. Max. Min. Max. Min. Max. 2.4 0 VCC 2.4 0 VCC 0.4 2.4 0 VCC 0.4 0.4 V V –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 100 — 90 — 80 mA 1, 2 — 2 — 2 — 2 mA 1 — 1 — 1 — 1 — 100 — 90 — 80 mA 1, 2 — 5 — 5 — 5 mA 1 — 100 — 90 — 80 mA 1, 2 — 90 — 80 — 70 mA 1, 3 0 V £ VI £ 6.5 V; All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) Power Supply Current (Standby) ICC2 Current (Standby) (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) tRC = Min. RAS, CAS = VIH RAS, CAS RAS cycling, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable Average Power Supply Current RAS, CAS cycling, ICC3 CAS = VIH, (RAS-only Refresh) Power Supply 0 V £ VO £ VCC ≥ VCC –0.2 V Average Power Supply Current DQ disable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tHPC = Min. Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 5/18 ¡ Semiconductor MSM5116405C AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Symbol MSM5116405 MSM5116405 MSM5116405 C-50 C-70 C-60 Unit Note Min. Max. Min. Max. Min. Max. — ns ns tRC 84 — 110 20 — 104 135 — tRWC tHPC — 124 160 — 25 — 30 — — tHPRWC 58 — 68 — 78 — ns ns tRAC — 50 — 60 — 70 ns 4, 5, 6 Access Time from CAS tCAC Access Time from Column Address Access Time from CAS Precharge tAA tCPA — — 13 25 — — 15 30 — — 20 35 ns ns 4, 5 4, 6 — 30 — 35 — 40 ns 4 Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ — 0 13 — — 0 15 — — 0 20 — ns ns 4 4 Data Output Hold After CAS Low tDOH 5 — 5 — 5 — ns CAS to Data Output Buffer Turn-off Delay Time RAS to Data Output Buffer Turn-off Delay Time tCEZ tREZ 0 13 0 0 20 ns 0 13 0 15 15 0 20 ns 7, 8 7, 8 OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turn-off Delay Time tOEZ tWEZ 0 0 13 13 0 0 15 15 0 0 20 20 ns ns 7 7 Transition Time Refresh Period tT tREF 1 — 50 64 1 — 50 64 1 — 50 64 ns ms 3 RAS Precharge Time tRP 30 — 40 — 50 — ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode with EDO) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time 7 — 10 — 13 — ns RAS Hold Time referenced to OE tRSH tROH 7 — 10 — 13 — ns CAS Precharge Time (Fast Page Mode with EDO) tCP 7 — 10 — 10 — ns CAS Pulse Width tCAS 7 10,000 10 10,000 13 10,000 ns CAS Hold Time CAS to RAS Precharge Time tCSH tCRP 35 5 — — 40 5 — — 45 5 — — ns ns RAS Hold Time from CAS Precharge tRHCP 30 — 35 — 40 — ns OE Hold Time from CAS (DQ Disable) RAS to CAS Delay Time RAS to Column Address Delay Time tCHO tRCD tRAD 5 11 9 — 37 25 5 14 12 — 45 30 5 14 12 — 50 35 ns ns ns Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 7 — 10 — 13 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns Column Address Hold Time Column Address to RAS Lead Time tCAH tRAL 7 25 — — 10 30 — — 13 35 — — ns ns 5 6 6/18 ¡ Semiconductor MSM5116405C AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13 Parameter Symbol MSM5116405 MSM5116405 MSM5116405 C-50 C-60 C-70 Unit Note Min. Max. Min. Max. Min. Max. tRCS 0 — 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — 0 — ns 9 Read Command Hold Time referenced to RAS Write Command Set-up Time tRRH tWCS 0 0 — — 0 0 — — 0 0 — — ns ns 9 10 Write Command Hold Time tWCH 7 — 10 — 13 — ns Write Command Pulse Width tWP 7 — 10 — 10 — ns WE Pulse Width (DQ Disable) tWPE 7 — 10 — 10 — ns Read Command Set-up Time OE Command Hold Time tOEH 7 — 10 — 13 — ns OE Precharge Time tOEP 7 — 10 — 10 — ns OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time tOCH tRWL tCWL 7 7 7 — — — 10 10 10 — — — 10 13 13 — — — ns ns ns Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time tDS tDH tOED tCWD tAWD tRWD 0 7 13 — — — 0 10 15 — — — 0 13 20 — — — ns ns ns 11 11 30 42 67 — — — 34 49 79 — — — 44 59 94 — — — ns ns ns 10 10 10 CAS Precharge WE Delay Time tCPWD 47 — 54 — 64 — ns 10 CAS Active Delay Time from RAS Precharge tRPC 5 — 5 — 5 — ns RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) tCSR tCHR tWRP tWRH tWTS tWTH 5 10 10 10 10 10 — — — — — — 5 10 10 10 10 10 — — — — — — 5 10 10 10 10 10 — — — — — — ns ns ns ns ns ns 7/18 ¡ Semiconductor Notes: MSM5116405C 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In a test mode CA0 and CA1 are not used and each DQ pin now accesses 4-bit locations. Since all 4 DQ pins are used, a total of 16 data bits can be written in parallel into the memory array. In a read cycle, if 4 data bits are equal, the DQ pin will indicate a high level. If the 4 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 8/18 E2G0100-17-41M ,, , , , ,,,, ,, ¡ Semiconductor MSM5116405C TIMING WAVEFORM Read Cycle tRC tRP tRAS RAS VIH – VIL – tCRP tCSH tCRP tRCD VIH – CAS VIL – tRAD tASR Address VIH – VIL – tRSH tCAS tRAH tASC tRAL tCAH Column Row tRCS WE OE VIH – VIL – tAA tROH tREZ tOEA VIH – VIL – tCAC tRAC DQ VOH – tOEZ Open VOL – tRCH tRRH tCEZ Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRP tRAS RAS VIH – VIL – tCRP tCRP VIH – CAS VIL – VIH – VIL – tASC Row tCAS tCAH tRAL Column tWCS WE tRSH tRAD tRAH tASR Address tCSH tRCD VIH – VIL – tWCH tWP tCWL tRWL OE VIH – VIL – tDS DQ VIH – VIL – tDH Valid Data-in Open "H" or "L" 9/18 ,,, ¡ Semiconductor MSM5116405C Read Modify Write Cycle tRWC tRAS VIH – RAS VIL – tRCD tRSH tCAS VIH – VIL – tASR VIH – Address VIL – WE VIH – VIL – OE VIH – VIL – tRAH tASC tCAH Column Row tRAD tRWD tAA tOEA tOED tCAC VI/OH– VI/OL– tCWL tRWL tWP tCWD tAWD tRCS tRAC DQ tCRP tCSH tCRP CAS tRP tCLZ tOEZ Valid Data-out tOEH tDS tDH Valid Data-in "H" or "L" 10/18 ,,,, , , ¡ Semiconductor MSM5116405C Fast Page Mode Read Cycle (Part-1) tRASP RAS VIH – VIL – tRHCP tCRP CAS WE tHPC tRCD tCP tCP tCAS VIH – VIL – tCAS tCAS tRAD tASR Address tRP VIH – VIL – tASC tRAH Row tCSH tCAH tASC Column tASC tCAH Column Column tRCS tRRH VIH – VIL – tCHO DQ tOCH tRAC tAA OE tCAH tOEP tAA VIH – VIL – tCPA tOEA tCAC VOH – VOL – tOEZ tCAC Valid Data-out Valid Data-out tCLZ tOEA tOEA tCAC tDOH tOEP tAA tOEZ Valid* Data-out * : Same Data, tREZ Valid* Data-out "H" or "L" Fast Page Mode Read Cycle (Part-2) tRASP RAS VIH – VIL – tRHCP WE OE DQ VIH – VIL – VIH – VIL – tCP tRAH tCSH tASC tCAH Row tASC Column tCAH Column tRCS tCAS tASC tCAH Column tRCS tRAC tAA VIH – VIL – VOH – VOL – tCP tCAS tRAD tASR Address tRCD tCAS VIH – VIL – tCRP tHPC tCRP CAS tRP tRCH tWPE tAA tAA tCPA tOEA tCAC tCLZ tWEZ Valid Data-out tCAC tDOH tCAC Valid Data-out tCEZ Valid Data-out "H" or "L" 11/18 ,,, , , ¡ Semiconductor MSM5116405C Fast Page Mode Write Cycle (Early Write) tRP tRASP RAS VIH – VIL – CAS tRAD tRAH tASR VIH – VIL – WE VIH – VIL – OE VIH – VIL – DQ VIH – VIL – tCP tCAS tCSH tASC tCAH Row tHPC tCP tCAS VIH – VIL – Address tHPC tRCD tCRP tASC Column tWCS tCAH tWCS tDH Valid Data-in Column tWCH tDS tRSH tCAH tASC Column tWCH tDS tCAS tDH Valid Data-in tWCS tWCH tDS tDH Valid Data-in "H" or "L" Fast Page Mode Read Modify Write Cycle tRASP RAS tRWD VIH – VIL – tCRP CAS VIH – VIL – VIH – VIL – tCWD tRAD tASR Address tCP tRCD Row tCWL tCAH tRCS tAWD VIH – VIL – tAWD tDS tWP VIH – VIL – tCAC VI/OH – VI/OL – tOED tOEZ Valid Data-out tCLZ tRWL tCWD tRAC tOEA DQ tCPA tCAH Column tAA OE tASC Column tRCS WE tCPWD tHPRWC tRAH tASC tAA tOEH tDS tOED tOEA tCAC tDH Valid Data-in tOEZ Valid Data-out tCLZ tWP tOEH tDH Valid Data-in "H" or "L" 12/18 _ ^ ] K S R Q P O N M F : ¡ Semiconductor MSM5116405C RAS-Only Refresh Cycle t RC tRP tRAS RAS V IH – V IL – tRPC tCRP CAS V IH – V IL – tRAH tASR Address V IH – V IL – Row tCEZ DQ V OH – V OL – Open Note: WE, OE = "H" or "L" "H" or "L" CAS before RAS Refresh Cycle tRC t RP RAS tRP tRAS VIH – VIL – t RPC tRPC tCP CAS tCSR tCHR tWRP tWRH VIH – VIL – WE VIH – VIL – DQ VOH – VOL – tWRP t CEZ Open Note: OE, Address = "H" or "L" "H" or "L" 13/18 , ,, ,, , ,, ¡ Semiconductor MSM5116405C Hidden Refresh Read Cycle tRC tRAS RAS CAS VIH – VIL – tCRP VIH – VIL – tASR Address WE OE VIH – VIL – tRSH tRCD tRAD tASC tRRH tRAL VIH – VIL – tAA tROH tOEA VIH – VIL – VOH – VOL – tCHR Column tRCS tRAC DQ tRP tCAH tRAH Row tRC tRAS tRP tCEZ tCAC tCLZ tOEZ Open tREZ Valid Data-out "H" or "L" Hidden Refresh Write Cycle tRC tRAS RAS CAS Address VIH – VIL – VIH – VIL – VIH – VIL – tCRP tASR tRCD tRAD tASC tRAH VIH – VIL – OE VIH – VIL – DQ VIH – VIL – tRSH tCAH tRP tCHR tRAL Column Row tWCS WE tRC tRAS tRP tRWL tWCH tWP tDS tDH Valid Data-in "H" or "L" 14/18 , ¡ Semiconductor MSM5116405C Test Mode Initiate Cycle tRC tRP RAS VIH – VIL – tRPC tCP CAS tRAS tCSR VIH – VIL – tWTS WE tCHR tWTH VIH – VIL – tOFF DQ VOH – VOL – Open Note: OE, Address = "H" or "L" "H" or "L" 15/18 ¡ Semiconductor MSM5116405C PACKAGE DIMENSIONS (Unit : mm) SOJ26/24-P-300-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/18 ¡ Semiconductor MSM5116405C (Unit : mm) TSOPII26/24-P-300-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/18 ¡ Semiconductor MSM5116405C (Unit : mm) TSOPII26/24-P-300-1.27-L Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/18