SCBS115A − OCTOBER 1990 − REVISED NOVEMBER 1993
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DL PACKAGE
(TOP VIEW)
BiCMOS Design Significantly Reduces ICCZ
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Support IEEE BTL Standard 1194.1-1991
Open-Collector B Port Drives Load
Impedances as Low as 10 Ω
BTL Logic Level 1-V Bus Swing Reduces
Power Consumption
Latchable Transceiver With Output Sink
of 24 mA at the A Bus and 100 mA at the
B Bus
Option to Generate and Check Parity or
Feed-Through Data/Parity in Directions
A to B or B to A
Independent Latch Enables for A-to-B
and B-to-A Directions
Select Pin for ODD/EVEN Parity
ERRA and ERRB Output Pins for Parity
Checking
Ability to Simultaneously Generate and
Check Parity
Packaged in 300-mil Plastic Shrink
Small-Outline (DL) Package
VCC
AI1
AO1
AI2
AO2
GND
AI3
AO3
AI4
AO4
AI5
GND
AO5
AI6
AO6
AI7
AO7
GND
AI8
AO8
APARI
APARO
VCC
LEBA
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
OEBA
LEAB
B1
GND
GND
B2
ERRA
B3
GND
GND
B4
ODD/EVEN
B5
SEL
B6
GND
GND
B7
ERRB
B8
GND
GND
BPAR
OEAB
description
The SN74BCT979 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a
feed-through transceiver, or it can generate/check parity from the 8-bit data bus in either direction. It has a
guaranteed current-sinking capability of 24 mA at the A bus and 100 mA at the open-collector B bus.
The SN74BCT979 features independent latch-enable (LEAB, LEBA) inputs for the A-to-B direction and the
B-to-A direction, an ODD/EVEN input to select odd or even parity, and separate error-signal (ERRA, ERRB)
outputs for checking parity.
When communication between buses occurs, parity is generated and passed on to either bus as APARO or
BPAR. Error detection of the parity generated from AI1−AI8 and B1−B8 can be checked by ERRA and ERRB,
providing LEAB and LEBA are high and the mode select (SEL) is low. If SEL is high, the communication between
buses is in a feed-through mode where parity is still generated and checked as ERRA and ERRB.
The SN74BCT979 features open-collector driver outputs (B port) with a series Schottky diode to reduce
capacitive loading to the bus. By using a 2-V pullup on the bus, the output signal swing will be approximately
1 V, which reduces the power necessary to drive the bus load capacitance. The driver outputs are capable of
driving an equivalent dc load of as low as 10 Ω.
The transceiver has a precision threshold set by an internal bandgap reference to give accurate input thresholds
over VCC and temperature variations.
This transceiver is compatible with backplane transceiver logic (BTL) technology at significantly reduced power
dissipation per channel.
The SN74BCT979 is characterized for operation from 0°C to 70°C.
Copyright 1993, Texas Instruments Incorporated
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• DALLAS, TEXAS 75265
• HOUSTON, TEXAS 77251−1443
POST OFFICE BOX 655303
POST OFFICE BOX 1443
1
SCBS115A − OCTOBER 1990 − REVISED NOVEMBER 1993
FUNCTION TABLE
INPUTS
OPERATION OR FUNCTION†
OEAB
OEBA
SEL
LEAB
LEBA
H
H
X
X
X
Isolation. AO1 −AO8 /APARO are in the high-impedance state and B1 −B8 /APAR are high.
H
L
L
X
H
Parity is generated from B1 −B8 data and output on APARO and is checked against BPAR and
output on ERRB.
H
L
L
X
L
Parity is generated from latched B1 −B8 data and output on APARO and is checked against BPAR
and output on ERRB.
H
L
H
X
H
BPAR is output on APARO. Parity is generated from B1 −B8 data, checked against BPAR, and
output on ERRB.
H
L
H
X
L
BPAR is output on APARO. Parity is generated from latched B1 −B8 data, checked against BPAR,
and output on ERRB.
L
H
L
H
X
Parity is generated from AI1 −AI8 data and output on BPAR and is checked against APARI and
output on ERRA.
L
H
L
L
X
Parity is generated from latched AI1 −AI8 data and output on BPAR and is checked against APARI
and output on ERRA.
L
H
H
H
X
APARI is output on BPAR. Parity is generated from AI1 −AI8 data, checked against APARI, and
output on ERRA.
L
H
H
L
X
APARI is output on BPAR. Parity is generated from latched AI1 −AI8 data, checked against APARI,
and output on ERRA.
L
L
X
X
X
AO1 −AO8 /APARO and B1 −B8 /BPAR are active (high or low logic levels).
† Parity is generated from AI1 −AI8 and from B1 − B8 based on the level present at ODD/EVEN. Parity is checked (AI1 − AI8 against APARI and
B1 −B8 against BPAR) based on the level present at ODD/EVEN (see parity function table).
PARITY FUNCTION TABLE‡
INPUTS
OUTPUTS
OEAB
SEL
ODD/EVEN
Σ OF INPUTS
AI1 −AI8 = H
L
L
L
0, 2, 4, 6, 8
L
L
L
1, 3, 5, 7
L
L
L
0, 2, 4, 6, 8
H
L
L
L
L
L
1, 3, 5, 7
H
H
H
L
L
H
0, 2, 4, 6, 8
L
H
L
L
L
H
1, 3, 5, 7
L
L
H
L
L
H
0, 2, 4, 6, 8
H
H
H
L
L
H
1, 3, 5, 7
H
L
L
L
H
L
0, 2, 4, 6, 8
L
L
H
L
H
L
1, 3, 5, 7
L
L
L
L
H
L
0, 2, 4, 6, 8
H
H
L
L
H
L
1, 3, 5, 7
H
H
H
L
H
H
0, 2, 4, 6, 8
L
L
L
L
H
H
1, 3, 5, 7
L
L
H
L
H
H
0, 2, 4, 6, 8
H
H
H
L
H
H
1, 3, 5, 7
H
H
L
H
X
X
X
X
H
X
APARI
BPAR
ERRA
L
L
H
L
H
L
‡ Parity functions for the A bus are shown. Parity functions for the B bus are
similar, but use B1 −B8 and BPAR as inputs and APARO and ERRB as outputs.
2
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SCBS115A − OCTOBER 1990 − REVISED NOVEMBER 1993
LATCH FUNCTION TABLES
INPUTS†
OUTPUT
B
OEAB
LEAB
AI
L
H
L
L
L
H
H
H
L
L
X
Q0
H
X
X
H
B
OUTPUT
AO
INPUTS†
OEBA
LEBA
L
H
L
L
L
H
H
H
L
L
X
Q0
H
X
X
Z
† If LEAB = H, current AI1 −AI8 and APARI
data is used. If LEAB = L, latched
AI1 −AI8 and APARI data is used.
•
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
3
SCBS115A − OCTOBER 1990 − REVISED NOVEMBER 1993
logic diagram (positive logic)
OEAB
LEAB
AI1 −AI8
C1
8
1D
EN
Latch
Buffer
8X
8X
8
B1 −B8
LEBA
8
OEBA
AO1 −AO8
EN
Buffer
8
C1
8X
Latch
8X
8
1D
2k
Parity
ODD/EVEN
ERRA
C1
APARI
1D
8
2k
Parity
ERRB
C1
1D
EN
APARO
1
G1
SEL
1
EN
BPAR
1
G1
1
4
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SCBS115A − OCTOBER 1990 − REVISED NOVEMBER 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1): B1−B8, BPAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC
Input clamp current, IIK (VI < 0) (A port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA
Current into any output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Maximum power dissipation at TA = 55°C (in still air) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.85 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input negative-voltage rating may be exceeded if the input clamp-current rating is observed.
recommended operating conditions (see Note 2)
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
IIK
High-level output voltage
IOH
High-level output current
B1 −B8, BPAR
Other inputs
MIN
NOM
MAX
4.5
5
5.5
∆t /∆v
Input transition rise or fall rate
V
2
1.47
Other inputs
0.8
B1 −B8, BPAR
V
2.1
mA
−18
mA
AO1 −AO8, APARO, ERRA, ERRB
−3
mA
AO1 −AO8, APARO, ERRA, ERRB
24
Input clamp current
Low-level output current
V
1.6
B1 −B8, BPAR
IOL
UNIT
B1 −B8, BPAR
100
Outputs enabled
TA
Operating free-air temperature
NOTE 2: Unused or floating pins (input or I/O) must be held high or low.
•
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
0
mA
10
ns / V
70
°C
5
SCBS115A − OCTOBER 1990 − REVISED NOVEMBER 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
IOH
TEST CONDITIONS
LE, OE, SEL, ODD/EVEN, AI1 −AI8, APARI
B1 −B8, BPAR
VCC = 4.5 V,
VCC = 5.5 V,
II = −18 mA
VOH = 2.1 mA
IOH = −1 mA
IOH = − 3 mA
VOH
AO1 −AO8, APARO, ERRA, ERRB
VCC = 4.5 V
VOL
AO1 −AO8, APARO, ERRA, ERRB
VCC = 4.5 V
IOL = 24 mA
IOL = 80 mA
II
LE, OE, SEL, ODD/EVEN, AI1 −AI8, APARI
VCC = 5.5 V,
IOL = 100 mA
VI = 5.5 V
IIH
LE, OE, SEL, ODD/EVEN, AI1 −AI8, APARI
B1 −B8, BPAR‡
IIL
LE, OE, SEL, ODD/EVEN, AI1 − AI8, APARI
B1 −B8, BPAR‡
IOZH
IOZL
IOS§
MIN
2.5
3.4
2.4
3.3
0.35
MAX
UNIT
−1.2
V
100
µA
V
0.5
0.75
1.1
0.75
1.15
100
VCC = 5.5 V
VI = 2.7 V
VI = 2.1 V
100
VCC = 5.5 V
VI = 0.5 V
VI = 0.3 V
−100
AO1 −AO8, APARO
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.5 V
AO1 −AO8, APARO
VCC = 5.5 V,
VO = 0
AO1 −AO8, APARO
20
−20
−60
Outputs high
ICC
TYP†
Outputs low
VCC = 5.5 V,
Outputs open
Outputs disabled
LE, OE, SEL, ODD/EVEN
Ci
AI1 −AI8, APARI
Cio
B1 −B8, BPAR
Co
AO1 −AO8, APARO
V
µA
µA
A
µA
A
50
µA
−50
µA
−200
mA
17
36
69
85
21
42
mA
8
VCC = 5 V,
VI = 2.5 V or 0.5 V
VCC = 5 V,
VCC = 5 V,
B port¶
VO = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
pF
8
TT
Output transition time
† All typical values are at VCC = 5 V, TA = 25°C.
‡ For I/O ports, the parameters IIH and IIL include the off-state output current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ Measured from 1.3 V to 1.8 V (see Figure 1).
5
pF
6.5
pF
1
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
MIN
tw
Pulse duration
AI1 −AI8, APARI before LEAB↓
tsu
Setup time
AI1 −AI8, APARI after LEAB↓
th
Hold time
B1 −B8, BPAR after LEBA↓
6
LEAB high
5
5
LEBA high
4
4
Data high
4
4
Data low
3
3
8.5
8.5
Data low
7
7
Data high
1
1
Data low
2.5
2.5
Data high
0.5
0.5
Data low
0.5
0.5
Data high
B1 −B8, BPAR before LEBA↓
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
MIN
MAX
UNIT
MAX
ns
ns
ns
SCBS115A − OCTOBER 1990 − REVISED NOVEMBER 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Note 3)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
AI
B
tPLH
tPHL
AI
BPAR
tPLH
tPHL
B
AO
tPLH
tPHL
B
APARO
tPLH
tPHL
APARI
BPAR
tPLH
tPHL
BPAR
APARO
PARAMETER
tPLH
tPLH
VCC = 5 V,
TA = 25°C
MIN
MAX
8.6
1.3
10.4
7.8
9.8
2.1
11.8
3.7
11.6
13.9
3.7
17.6
5.4
13.9
15.7
5.4
19.2
2.8
9
11.1
2.8
14.3
2.4
8.1
10
2.4
12.3
4.5
14.1
16.1
4.5
20.9
4.2
13.3
15.9
4.2
20.5
1.6
6
7.7
1.6
9.3
3.4
9.5
11.2
3.4
13.6
2.7
7.9
9.9
2.7
12.8
3
8.1
10
3
12.5
MIN
TYP
MAX
1.3
6.8
2.1
AI
ERRA
APARI
tPHL
tPHL
AI
APARI
tPLH
tPLH
BPAR
tPHL
tPHL
BPAR
3
10.9
13
3
16.1
2.8
8.2
10.2
2.8
12.6
4.2
11.8
14
4.2
16.7
4
8.9
10.9
4
12.8
4.3
13.4
15.9
4.3
20.6
4.2
10.8
13.1
4.2
16.6
5.5
14.5
17
5.5
21.5
5.5
11.3
13.5
5.5
16.5
3.4
9.1
10.9
3.4
13.7
4.4
10.3
12.2
4.4
14.5
3.4
8.7
10.7
3.4
13.3
4.6
10
11.9
4.6
14.2
3.4
8.7
10.6
3.4
13.5
3.1
9
10.9
3.1
13.4
ERRA
B
ERRB
B
ERRB
tPLH
tPHL
ODD/EVEN
ERRA
tPLH
tPHL
ODD/EVEN
ERRB
tPLH
tPHL
ODD/EVEN
APARO
tPLH
tPHL
ODD/EVEN
BPAR
tPLH
tPHL
SEL
APARO
tPLH
tPHL
SEL
BPAR
4
10.3
12.1
4
15.8
4.9
12.3
14.1
4.9
17.3
0.7
5.3
6.9
0.7
8.4
1.1
5
6.5
1.1
7.8
1.1
6.4
8.1
1.1
10.1
2.8
8.3
9.9
2.8
12.6
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
•
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•
7
SCBS115A − OCTOBER 1990 − REVISED NOVEMBER 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Note 3) (continued)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
LEAB
B
tPLH
tPHL
LEAB
tPLH
tPHL
PARAMETER
VCC = 5 V,
TA = 25°C
MIN
MAX
9.5
1.6
11.6
8.1
10
2.7
11.7
2.3
7.3
9.2
2.3
10.8
4.6
9.3
11
4.6
13.3
4.7
10.7
13
4.7
16.2
6.2
11.5
13.4
6.2
16
3.3
8.6
10.7
3.3
12.8
4.7
9.8
12
4.7
13.7
1.3
6.5
8.5
1.3
10
1.4
5.9
7.6
1.4
8.5
APARO
(parity feed through)
1.7
5.9
7.7
1.7
9.1
1.9
6
7.8
1.9
9
APARO
(parity generated)
3.5
9.3
11.5
3.5
14.1
LEBA
3.1
8.2
10.3
3.1
12.2
tPLH
tPHL
3.4
8.7
10.8
3.4
12.7
LEBA
ERRB
4.6
9
11
4.6
12.5
tPLH
tPHL
OEAB
B
tPLH
tPHL
OEAB
BPAR
tPZH
tPZL
OEBA
AO
tPHZ
tPLZ
OEBA
AO
tPZH
tPZL
OEBA
APARO
tPHZ
tPLZ
OEBA
APARO
MIN
TYP
MAX
1.6
7.6
2.7
BPAR
(parity feed through)
LEAB
BPAR
(parity generated)
tPLH
tPHL
LEAB
ERRA
tPLH
tPHL
LEBA
AO
tPLH
tPHL
LEBA
tPLH
tPHL
1.5
5.5
7
1.5
7.9
4.9
10.4
12.1
4.9
14.1
1.4
5.4
6.9
1.4
7.8
4.8
10.6
12.5
4.8
14.9
1.4
6
7.8
1.4
9.2
6
10.7
12.5
6
14.6
2.4
6.7
8.6
2.4
9.5
1.2
4.7
6.3
1.2
7.1
1.7
6.1
7.8
1.7
9.3
1.4
5.1
6.7
1.4
7.8
2.7
6.8
8.6
2.7
9.5
1.2
4.7
6.2
1.2
7.1
NOTE 3: Load circuits and waveforms are shown in Section 1.
8
•
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•
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jul-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
SN74BCT979DL
OBSOLETE
SSOP
DL
48
TBD
Call TI
Call TI
SN74BCT979DLR
OBSOLETE
SSOP
DL
48
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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