DS90UH927Q 5MHz - 85MHz 24-bit Color FPD-Link III Serializer with HDCP General Description Features The DS90UH927Q serializer, in conjunction with a DS90UH928Q or DS90UH926Q deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a FPD-Link video interface into a single-pair high-speed serialized interface. The digital video data is protected using the industry standard High-Bandwidth Digital Content Protection (HDCP) copy protection scheme. The FPD-Link III serial bus scheme supports full duplex, high speed forward channel data transmission and low-speed back channel communication over a single differential link. Consolidation of audio, video, and control data over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design. The DS90UH927Q serializer embeds the clock, content protects the data payload, and level shifts the signals to highspeed differential signaling. Up to 24 RGB data bits are serialized along with three video control signals, and up to four I2S data inputs. The FPD-Link data interface allows for easy interfacing with data sources while also minimizing EMI and bus width. EMI on the high-speed FPD-Link III bus is minimized using low voltage differential signaling, data scrambling and randomization, and dc-balancing. The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory. ● Integrated HDCP cipher engine with on-chip key storage ● Bidirectional control channel interface with I2C compatible ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● serial control bus Low EMI FPD-Link video input Supports high definition (720p) digital video format 5MHz – 85MHz PCLK supported RGB888 + VS, HS, DE and I2S audio supported Up to 4 I2S Digital Audio inputs for surround sound applications 4 Bidirectional GPIO channels with 2 dedicated pins Single 3.3V supply with 1.8V or 3.3V compatible LVCMOS I/O interface AC-coupled STP Interconnect up to 10 meters DC-balanced & scrambled Data with Embedded Clock Supports HDCP repeater application Internal pattern generation Low power modes minimize power dissipation Automotive grade product: AEC-Q100 Grade 2 qualified >8kV HBM and ISO 10605 ESD rating Backward compatible modes Applications ● Automotive Display for Navigation ● Rear Seat Entertainment Systems Applications Diagram 30193027 TRI-STATE® is a registered trademark of National Semiconductor Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 301930 SNLS433A Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q DS90UH927Q Pin Diagram 30193019 DS90UH927Q — Top View Pin Descriptions Pin Name Pin # I/O, Type Description FPD-Link Input Interface RxIN[3:0]+ 38, 34, 32, 30 I, LVDS True LVDS Data Inputs Each pair requires external 100Ω differential termination for standard LVDS levels RxIN[3:0]- 37, 33, 31, 29 I, LVDS Inverting LVDS Data Inputs Each pair requires external 100Ω differential termination for standard LVDS levels RxCLKIN+ 36 I, LVDS True LVDS Clock Input The pair requires external 100Ω differential termination for standard LVDS levels RxCLKIN- 35 I, LVDS Inverting LVDS Clock Input The pair requires external 100Ω differential termination for standard LVDS levels LVCMOS Parallel Interface I2S_WC I2S_CLK 1 2 I, LVCMOS Digital Audio Interface I2S Word Clock and I2S Bit Clock Inputs w/ pull down Shared with GPIO_REG7 and GPIO_REG8 Table 3 I2S_DA I2S_DB I2S_DC I2S_DD 3 4 5 6 I, LVCMOS Digital Audio Interface I2S Data Inputs w/ pull down Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3 2 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q Pin Name Pin # I/O, Type Description GPIO[1:0] 40, 39 REPEAT 21 I, LVCMOS Repeater Mode Select w/ pull down REPEAT = 0, Repeater Mode disabled (Default) REPEAT = 1, Repeater Mode enabled Requires a 10kΩ pull-up if set HIGH BKWD 22 I, LVCMOS Backward Compatible Mode Select w/ pull down BKWD = 0, interfacing to DS90UH926/8Q (Default) BKWD = 1, interfacing to DS90UR906/8Q, DS90UR916Q Requires a 10kΩ pull-up if set HIGH MAPSEL 23 I, LVCMOS FPD-Link Input Map Select w/ pull down MAPSEL = 0, LSBs on RxIN3± (Default) MAPSEL = 1, MSBs on RxIN3± See Figure 12and Figure 13 Requires a 10kΩ pull-up if set HIGH LFMODE 25 I, LVCMOS Low Frequency Mode Select w/ pull down LFMODE = 0, 15MHz ≤ RxCLKIN ≤ 85MHz (Default) I/O, General Purpose I/O LVCMOS See Table 1 w/ pull down LFMODE = 1, 5MHz ≤ RxCLKIN < 15MHz Requires a 10kΩ pull-up if set HIGH Optional Parallel Interface GPIO[3:2] GPIO_REG [8:5] 6, 5 I/O, LVCMOS w/ pull down General Purpose I/O Shared with I2S_DD and I2S_DC See Table 1 2, 1, 3, 4 I/O, LVCMOS w/ pull down Register-Only General Purpose I/O Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB See Table 2 Control and Configuration PDB 18 I, LVCMOS Power-down Mode Input Pin w/ pull-down Must be driven or pulled up to VDD33. Refer to “Power Up Requirements and PDB Pin" in the Applications Information Section. PDB = H, device is enabled (normal operation) PDB = L, device is powered down. When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is shutdown, and IDD is minimized. Control Registers are RESET. SCL 9 I/O, LVCMOS Open Drain I2C Clock Input / Output Interface Must have an external pull-up to VDD33. DO NOT FLOAT. SDA 10 I/O, LVCMOS Open Drain I2C Data Input / Output Interface Must have an external pull-up to VDD33. DO NOT FLOAT. IDx 11 I, Analog Recommended pull-up: 4.7kΩ. Recommended pull-up: 4.7kΩ. I2C Address Select External pull-up to VDD33 is required under all conditions. DO NOT FLOAT. Connect to external pull-up to VDD33 and pull-down to GND to create a voltage divider. See Figure 23and Table 4 Status INTB 27 O, LVCMOS HDCP Interrupt Open Drain INTB = H, normal INTB = L, Interrupt request Recommended pull-up: 4.7kΩ to VDDIO. DO NOT FLOAT. FPD-Link III Serial Interface DOUT+ 17 I/O, LVDS True Output The output must be AC-coupled with a 0.1µF capacitor. Copyright © 1999-2012, Texas Instruments Incorporated 3 DS90UH927Q Pin Name Pin # I/O, Type Description DOUT- 16 I/O, LVDS Inverting Output The output must be AC-coupled with a 0.1µF capacitor. CMF 20 Analog Common Mode Filter. Connect 0.1µF to GND (required) 19 26 Power Power to on-chip regulator 3.0 V - 3.6 V. Each pin requires a 4.7µF capacitor to GND VDDIO 7, 24 Power LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Each pin requires 4.7µF capacitor to GND GND DAP Ground Large metal contact at the bottom center of the device package Connect to the ground plane (GND) with at least 9 vias. Power* and Ground VDD33_A VDD33_B Regulator Capacitor CAPP12 CAPHS12 CAPLVD12 12 14 28 CAP Decoupling capacitor connection for on-chip regulator Each requires a 4.7µF decoupling capacitor to GND. CAPL12 8 CAP Decoupling capacitor connection for on-chip regulator Requires two 4.7µF decoupling capacitors to GND 15, 13 GND Reserved Connect to GND. Other RES[1:0] * The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. 4 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q Block Diagram 30193028 Ordering Information NSID Quantity SPEC Package ID DS90UH927QSQE Package Description 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch 250 NOPB SQA40A DS90UH927QSQ 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch 1000 NOPB SQA40A DS90UH927QSQX 40-pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch 2000 NOPB SQA40A Note: Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades defined in the AEC Q100 standard. Automotive Grade products are identified with the letter Q. For more information go to http://www.ti.com/automotive. Copyright © 1999-2012, Texas Instruments Incorporated 5 DS90UH927Q Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Parameter Supply Voltage – VDD33 DS90UH927Q Unit −0.3 to +4.0 V Supply Voltage – VDDIO −0.3 to +4.0 −0.3 to (VDDIO + 0.3) V LVCMOS I/O Voltage −0.3 to +2.75 +150 −65 to +150 V V °C °C 1/ θJA °C/W θJA 28.0 °C/W θJC 4.4 °C/W ≥±15 kV ≥±8 kV ≥±15 kV ≥±8 kV ≥±15 kV ≥±8 ≥±8 kV ≥±1.25 ≥±250 kV Serializer Output Voltage Junction Temperature Storage Temperature 40 LLP Package Maximum Power Dissipation Capacity at 25°C Derate above 25°C ESD Rating (IEC, powered-up only), RD = 330Ω, CS = 150pF Air Discharge (DOUT+, DOUT−) Contact Discharge (DOUT+, DOUT−) ESD Rating (ISO10605), RD = 330Ω, CS = 150pF Air Discharge (DOUT+, DOUT−) Contact Discharge (DOUT+, DOUT−) ESD Rating (ISO10605), RD = 2kΩ, CS = 150pF or 330pF Air Discharge (DOUT+, DOUT−) Contact Discharge (DOUT+, DOUT−) ESD Rating (HBM) ESD Rating (CDM) ESD Rating (MM) For soldering specifications: see product folder at www.ti.com and kV V www.ti.com/lit/an/snoa549c/snoa549c.pdf Recommended Operating Conditions Parameter Supply Voltage (VDD33) Min 3.0 Nom 3.3 Max 3.6 Units V LVCMOS Supply Voltage (VDDIO) Note: VDDIO < VDD33+0.3V 3.0 3.3 3.6 V OR LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V −40 5 +25 +105 85 100 °C MHz mVP-P Operating Free Air Temperature (TA) PCLK Frequency Supply Noise ((Note 5)) 6 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units 2.0 VDDIO V GND 0.8 V +15 μA LVCMOS I/O VIH High Level Input Voltage VDDIO = 3.0V to 3.6V (Note 14) VIL Low Level Input Voltage VDDIO = 3.0V to 3.6V (Note 14) IIN Input Current VIN = 0V or VDDIO = 3.0V to 3.6V (Note 14) VIH High Level Input Voltage PDB −15 VDDIO = 3.0V to 3.6V VIL IIN Low Level Input Voltage Input Current GPIO[1:0] I2S_CLK VDDIO = 3.0V to 3.6V I2S_WC I2S_D VDDIO = 1.71V to 1.89V [A,B,C,D] VDDIO = 3.0V LFMODE MAPSEL to 3.6V VIN = 0V or BKWD VDDIO = VDDIO REPEAT 1.71V to 1.89V VDDIO = 1.71V to 1.89V VDDIO = 3.0V to 3.6V VOH High Level Output Voltage IOH = −4mA IOL = +4mA VOL Low Level Output Voltage VDDIO = 1.71V to 1.89V VDDIO = 3.0V GPIO[3:0], GPO_REG to 3.6V [8:5] VDDIO = 1.71V to 1.89V IOS Output Short Circuit Current VOUT = 0V IOZ TRI-STATE® Output Current VOUT = 0V or VDDIO, PDB = L, ±1 2.0 VDDIO V 0.65* VDDIO VDDIO V GND 0.8 V GND 0.35* VDDIO V −15 ±1 +15 μA −15 ±1 +15 μA 2.4 VDDIO V VDDIO 0.45 VDDIO V GND 0.4 V GND 0.45 V −55 −15 mA +15 μA +100 mV FPD-Link LVDS Receiver VTH Threshold High Voltage VTL Threshold Low Voltage |VID| Differential Input Voltage Swing VCM Common Mode Voltage IIN Input Current Copyright © 1999-2012, Texas Instruments Incorporated VCM = 1.2V −100 RxCLKIN± RxIN[3:0]± mV 200 0 −10 600 1.2 mV 2.4 V +10 μA 7 DS90UH927Q Symbol Parameter Conditions Pin/Freq. Min Typ Max Units 800 1000 1200 mVp-p 1 50 mV FPD-LINK III CML Driver VODp-p Differential Output Voltage (DOUT+) – (DOUT-) ΔVOD Output Voltage Unbalance VOS Offset Voltage – Single-ended RL = 100Ω RL = 100Ω 2.5-0.2 5*VODpDOUT± ΔVOS Offset Voltage Unbalance Single-ended IOS Output Short Circuit Current RT Internal Termination Resistance - Differential V p (TYP) 1 50 DOUT+/- = 0V, PDB = L or H mV mA 100 120 Ω VDD33= 3.6V 135 160 mA VDDIO = 3.6V 100 500 μA VDDIO = 1.89V 200 600 μA VDD33= 3.6V 133 mA VDDIO = 3.6V 100 μA VDDIO = 1.89V 100 μA VDD33 = 3.6V 1.2 2.4 mA reg_0x01[7]=1, Back channel VDDIO = 3.6V Idle VDDIO = 1.89V 4 30 μA 5 30 μA VDD33 = 3.6V 1 2.2 mA PDB = 0V, All other LVCMOS VDDIO = 3.6V Supply Current — Power Down inputs = 0V VDDIO = 1.89V 8 20 μA 4 20 μA 80 Supply Current IDD1 Checkerboard Pattern IDDIO1 IDD2 Supply Current RL = 100Ω, PCLK = 85MHz Random Pattern PRBS7 IDDIO2 IDDS IDDIOS IDDZ IDDIOZ 8 Supply Current — Remote Auto Power Down Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units FPD-Link LVDS INPUT tRSP Receiver Strobe Position Figure 4 RxCLKIN±, RXIN[3:0]± 0.25 0.5 0.75 UI FPD-Link III CML I/O tLHT tHLT CML Output Low-to-High Transition Time CML Output High-to-Low Transition Time tPLD Figure 3 Figure 5, (Note 6) Serializer PLL Lock Time tSD tTJIT Delay — Latency Figure 6 Output Total Jitter, Checkerboard Pattern PCLK = 5MHz Figure 8 Bit Error Rate ≤1E-9 Figure 7, (Note 12, Note 11, Note 8, Note 7) Input Jitter Tolerance, Bit Error tIJIT Rate ≤1E-9 (Note 7, Note 10) Checkerboard Pattern PCLK = 85MHz Figure 8 DOUT+, DOUT- 100 140 ps 100 140 ps 5 ms PCLK = 5MHz to 85MHz 146*T ns 0.17 0.2 UI 0.26 0.29 UI RxCLKIN± f/40 < Jitter Freq < f/20, DES = DS90UH926Q RxCLKIN±, f f/40 < Jitter Freq < f/20, DES = 78MHz = DS90UH928Q 0.6 UI 0.5 UI I2S Receiver TI2S I2S Clock Period Figure 10, (Note 8, Note 16) RxCLKIN± f=5MHz to 85MHz I2S_CLK, PCLK = 5MHz to 85MHz >4/ PCLK or >77 ns THC I2S Clock High Time Figure 10, (Note 16) I2S_CLK 0.35 TI2S TLC I2S Clock Low Time Figure 10, (Note 16) I2S_CLK 0.35 TI2S tsr I2S Set-up Time I2S_WC I2S_D [A,B,C,D] 0.2 TI2S thtr I2S Hold Time I2S_WC I2S_D [A,B,C,D] 0.2 TI2S Other I/O tGPIO,FC tGPIO,BC GPIO Pulse Width, Forward Channel GPIO Pulse Width, Back Channel Copyright © 1999-2012, Texas Instruments Incorporated GPIO[3:0], PCLK = 5MHz to 85MHz GPIO[3:0] >2/ PCLK s 20 µs 9 DS90UH927Q Recommended Timing for the Serial Control Bus Over 3.3V supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4) Symbol fSCL tLOW tHIGH Parameter SCL Clock Frequency SCL Low Period SCL High Period Max Units Standard Mode Conditions Min 0 Typ 100 kHz Fast Mode 0 400 kHz Standard Mode 4.7 µs Fast Mode 1.3 µs Standard Mode 4.0 µs Fast Mode 0.6 µs Hold time for a start or a repeated start condition Figure 9 Standard Mode 4.0 µs Fast Mode 0.6 µs Set Up time for a start or a repeated start condition Figure 9 Standard Mode 4.7 µs Fast Mode 0.6 µs Data Hold Time Figure 9 Standard Mode 0 3.45 µs Fast Mode 0 0.9 µs Data Set Up Time Figure 9 Standard Mode 250 ns Fast Mode 100 ns Set Up Time for STOP Condition Figure 9 Standard Mode 4.0 µs Fast Mode 0.6 µs Bus Free Time Between STOP and START Figure 9 Standard Mode 4.7 µs tBUF Fast Mode 1.3 µs tr SCL & SDA Rise Time, Figure 9 Standard Mode 1000 ns Fast Mode 300 ns tf SCL & SDA Fall Time, Figure 9 Standard Mode 300 ns Fast mode 300 ns tHD;STA tSU:STA tHD;DAT tSU;DAT tSU;STO DC and AC Serial Control Bus Characteristics Over 3.3V supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4) Symbol Parameter VIH Input High Level VIL Input Low Level Voltage VHY Input Hysteresis VOL Max Units SDA and SCL 0.7* VDDIO Min VDD33 V SDA and SCL GND 0.3* VDD33 V 0 SDA or SCL, Vin = VDDIO or GND tR SDA RiseTime – READ tF SDA Fall Time – READ tSU;DAT Typ >50 SDA or SCL, IOL = 1.25mA Iin 10 Conditions -10 mV 0.36 V +10 µA SDA, RPU = 10kΩ, Cb ≤ 400pF, Figure 9 430 ns 20 ns Set Up Time — READ Figure 9 560 ns tHD;DAT Hold Up Time — READ Figure 9 615 ns tSP Input Filter 50 ns Cin Input Capacitance <5 pF SDA or SCL Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: Typical values represent most likely parametric norms at VDD33 = 3.3V, VDDIO = 1.8V or 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages. Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the supply pins with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency is less than 50MHz. Note 5: Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDD33 and VDDIOsupplies with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz. Note 6: tPLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK. Note 7: Specification is guaranteed by characterization and is not tested in production Note 8: Specification is guaranteed by design and is not tested in production Note 9: tTJIT (@BER of 1E-9) specifies the allowable jitter on RxCLKIN± Note 10: Jitter Frequency is specified in conjunction with DS90UH928Q PLL bandwidth. Note 11: UI – Unit Interval is equivalent to one ideal serialized bit width. The UI scales with PCLK frequency. Note 12: Output jitter specs are dependent upon the input clock jitter at the SER Note 13: The DS90UH927Q VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less than 1.5ms with a monotonic rise Note 14: PDB is specified to 3.3V LVCMOS only and must be driven or pulled up to VDD33 or to VDDIO ≥ 3.0V Note 15: IOS is not specified for an indefinite period of time. Do not hold in short circuit for more than 500ms or part damage may result Note 16: I2S specifications for tLC and tHC pulses must each be greater than 2 PCLK periods to guarantee sampling and supersedes the 0.35*TI2S_CLK requirement. tLC and tHC must be longer than the greater of either 0.35*TI2S_CLK or 2*PCLK Copyright © 1999-2012, Texas Instruments Incorporated 11 DS90UH927Q AC Timing Diagrams and Test Circuits 30193013 FIGURE 1. FPD-Link DC VTH/VTL Definition 30193062 FIGURE 2. Serializer VOD DC Output 30193047 FIGURE 3. Output Transition Times 12 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q 30193014 FIGURE 4. FPD-Link Input Strobe Position 30193049 FIGURE 5. Serializer Lock Time 30193015 FIGURE 6. Latency Delay Copyright © 1999-2012, Texas Instruments Incorporated 13 DS90UH927Q 30193048 FIGURE 7. CML Serializer Output Jitter 30193046 FIGURE 8. Checkerboard Data Pattern 30193036 FIGURE 9. Serial Control Bus Timing Diagram 14 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q 30193006 FIGURE 10. I2S Timing Diagram Copyright © 1999-2012, Texas Instruments Incorporated 15 DS90UH927Q Functional Description The DS90UH927Q converts a FPD-Link interface (4 LVDS data channels + 1 LVDS Clock) to a FPD-Link III interface. This device transmits a 35-bit symbol over a single serial pair operating at up to a 2.975Gbps line rate. The serial stream contains an embedded clock, video control signals, RGB video data, and audio data. The payload is DC-balanced to enhance signal quality and support AC coupling. The DS90UH927Q applies encryption to the video data using a High-Bandwidth Digital Content Protection (HDCP) Cipher, and transmits the encrypted data out through the FPD-Link III interface. Audio encryption is supported. On chip non-volatile memory stores the HDCP keys. All key exchanges are conducted over the FPD-Link III bidirectional control interface. The DS90UH927Q serializer is intended for use with a DS90UH928Q or DS90UH926Q deserializer, but is also backward compatible with DS90UR906Q, DS90UR908Q, DS90UR910Q, and DS90UR916Q FPD-Link II deserializers. The DS90UH927Q serializer and DS90UH928Q or DS90UH926Q deserializer incorporate an I2C compatible interface. The I2C compatible interface allows programming of serializer or deserializer devices from a local host controller. In addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between serializer/deserializer as well as remote I2C slave devices. The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial link from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at either side of the serial link. HIGH SPEED FORWARD CHANNEL DATA TRANSFER The High Speed Forward Channel is composed of a 35-bit frame containing RGB data, sync signals, HDCP, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 11 illustrates the serial stream generated per PCLK cycle into RxCLKIN±. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized, DC-balanced and scrambled. 30193007 FIGURE 11. FPD-Link III Serial Stream The device supports pixel clock ranges of 5MHz to 15MHz (LFMODE=1) and 15MHz to 85MHz (LFMODE=0). This corresponds to an application payload rate range of 155Mbps to 2.635Gbps, with an actual line rate range of 525Mbps to 2.975Gbps. LOW SPEED BACK CHANNEL DATA TRANSFER The Low-Speed Back Channel of the DS90UH927Q provides bidirectional communication between the display and host processor. Data is transferred simultaneously over the same physical link as the high-speed forward channel data. The back channel transports I2C, HDCP, CRC, and 4 bits of standard GPIO information with a 10Mbps line rate. BACKWARD COMPATIBLE MODE The DS90UH927Q is also backward compatible to DS90UR906Q, DS90UR908Q FPD, and DS90UR916Q FPD-Link II deserializers for PCLK frequencies ranging from 5MHz to 65MHz. It is also backward compatible with the DS90UR910Q for PCLK frequencies ranging from 5MHz to 75MHz. The serializer transmits 28-bits of data over a single serial FPD-Link II pair operating at a payload rate of 120Mbps to 1.8Gbps, corresponding to a line rate of 140Mbps to 2.1Gbps. The Backward Compatibility configuration can be selected through the BKWD pin or programmed through the configuration register (Table 5). The bidirectional control channel, HDCP, bidirectional GPIOs, I2S, and interrupt (INTB) are not active in this mode. However, local I2C access to the serializer is still available. Note: PCLK frequency range in this mode is 15MHz to 75MHz for LFMODE=0 and 5MHZ to <15MHz for LFMODE=1. COMMON MODE FILTER PIN (CMF) The serializer provides access to the center tap of the internal CML termination. A 0.1μF capacitor must be connected from this pin to GND for additional common-mode filtering of the differential pair (Figure 27). This increases noise rejection capability in highnoise environments. FPD-LINK INPUT FRAME AND COLOR BIT MAPPING SELECT The DS90UH927Q can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes: LSBs on RxIN[3]±, shown in Figure 12, or MSBs on RxIN[3], shown in Figure 13. Each frame corresponds to a single pixel clock (PCLK) cycle. The 16 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q LVDS clock input to RxCLKIN± follows a 4:3 duty cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock periods high, three low, and ending with two high. The mapping scheme is controlled by MAPSEL pin or by Register (Table 5). 30193004 FIGURE 12. FPD-Link Mapping: LSBs on RxIN3 (MAPSEL=L) 30193005 FIGURE 13. FPD-Link Mapping: MSBs on RxIN3 (MAPSEL=H) VIDEO CONTROL SIGNALS The video control signal bits embedded in the high-speed FPD-Link LVDS are subject to certain limitations relative to the video pixel clock period (PCLK). By default, the DS90UH927Q applies a minimum pulse width filter on these signals to help eliminate spurious transitions. Normal Mode Control Signals (VS, HS, DE) have the following restrictions: • Horizontal Sync (HS): The video control signal pulse width must be 3 PCLKs or longer when the Control Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this restriction (minimum is 1 PCLK). See Table 5. HS can have at most two transitions per 130 PCLKs. Copyright © 1999-2012, Texas Instruments Incorporated 17 DS90UH927Q • • Vertical Sync (VS): The video control signal pulse is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130 PCLKs. Data Enable Input (DE): The video control signal pulse width must be 3 PCLKs or longer when the Control Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this restriction (minimum is 1 PCLK). See Table 5. DE can have at most two transitions per 130 PCLKs. EMI REDUCTION FEATURES LVCMOS VDDIO OPTION The 1.8V or 3.3V LVCMOS inputs and outputs are powered from separate VDDIO supply pins to offer compatibility with external system interface signals. Note: When configuring the VDDIO power supplies, all the single-ended control input pins for device need to scale together with the same operating VDDIO levels. If VDDIO is selected to operate in the 3.0V to 3.6V range, VDDIO must be operated within 300mV of VDD33. POWER DOWN (PDB) The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin may be controlled by an external device, or through VDDIO, where VDDIO = 3.0V to 3.6V or VDD33. To save power, disable the link when the display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before VDD33 and VDDIO have reached final levels. When PDB is driven low, ensure that the pin is driven to 0V for at least 1.5ms before releasing or driving high. In the case where PDB is pulled up to VDDIO = 3.0V to 3.6V or VDD33 directly, a 10kΩ pull-up resistor and a >10µF capacitor to ground are required (See Figure 27). Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time, PDB must be held low for a minimum period of time. See AC Electrical Characteristics for more information. REMOTE AUTO POWER DOWN MODE The DS90UH927Q serializer features a Remote Auto Power Down mode. This feature is enabled and disabled through the register bit 0x01[7] (Table 5). When the back channel is not detected, either due to an idle or powered-down deserializer, the serializer enters remote auto power down mode. Power dissipation of the serializer is significantly reduced in this mode. The serializer automatically attempts to resume normal operation upon detection of an active back channel from the deserializer. To complete the wake-up process and reactivate forward channel operation, the remote power-down feature must be disabled by either a local I2C host, or by an auto-ACK I2C transaction from a remote I2C host located at the deserializer. The Remote Auto Power Down Sleep/Wake cycle is shown below in Figure 14: 30193009 FIGURE 14. Remote Auto Power Down Sleep/Wake Cycle To resume normal operation, the Remote Auto Power Down feature must be disabled in the device control register. This may be accomplished from a local I2C controller by writing reg_0x01[7]=0 (Table 5). To disable from a remote I2C controller located at the deserializer, perform the following procedure to complete the wake-up process: 1. 2. 3. 4. 5. 18 Power up remote deserializer (back channel must be active) Enable I2C PASS-THROUGH ALL by setting deserializer register reg_0x05[7]=1 Enable I2C AUTO ACK by setting deserializer register reg_0x03[2]=1 Disable Remote Auto Power Down by setting serializer register reg_0x01[7]=0 Disable I2C AUTO ACK by setting deserializer register reg_0x03[2]=0 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q 6. Disable I2C PASS-THROUGH ALL by setting deserializer register reg_0x05[7]=0 INPUT RxCLKIN LOSS DETECT The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. A clock loss condition is detected when PCLK drops below approximately 1MHz. When a PCLK is detected again, the serializer will then lock to the incoming RxCLKIN±. Note – when RxCLKIN± is lost, the optional Serial Bus Control Registers values are still retained. See (Table 5) for more information. SERIAL LINK FAULT DETECT The DS90UH927Q can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C (Table 5). The DS90UH927Q will detect any of the following conditions: 1. 2. 3. 4. 5. 6. 7. Cable open “+” to “-” short ”+” to GND short ”-” to GND short ”+” to battery short ”+” to battery short Cable is linked incorrectly (DOUT+/DOUT- connections reversed) Note: The device will detect any of the above conditions, but does not report specifically which one has occurred. LOW FREQUENCY OPTIMIZATION (LFMODE) The LFMODE is set via register (Table 5) or LFMODE Pin. This mode optimizes device operation for lower input data clock ranges supported by the serializer. If LFMODE is Low (LFMODE = 0, default), the RxCLKIN± frequency is between 15MHz and 85MHz. If LFMODE is High (LFMODE = 1), the RxCLKIN± frequency is between 5 MHz and <15 MHz. Note: when the device LFMODE is changed, a PDB reset is required. When LFMODE is high (LFMODE=1), the line rate relative to the input data rate is multiplied by four. Thus, for the operating range of 5MHz to <15MHz, the line rate is 700Mbps to <2.1Gbps with an effective data payload of 175Mbps to 525Mbps. Note: for Backwards Compatibility Mode (BKWD=1), the line rate relative to the input data rate remains the same. INTERRUPT PIN (INTB) 1. 2. 3. On the DS90UH927Q serializer, set register reg_0xC6[5] = 1 and 0xC6[0] = 1 (Table 5) to configure and arm the interrupt. When INTB_IN on the deserializer (DS90UH926Q or DS90UH928Q) is set LOW, the INTB pin on the serializer also pulls low, indicating an interrupt condition. The external controller detects INTB = LOW and reads the HDCP_ISR register (Table 5) to determine the interrupt source. Reading this register also clears and resets the interrupt. GENERAL-PURPOSE I/O GPIO[3:0] In normal operation, GPIO[3:0] may be used as general purpose IOs in either forward channel (inputs) or back channel (outputs) applications. GPIO modes may be configured from the registers (Table 5). GPIO[1:0] are dedicated pins and GPIO[3:2] are shared with I2S_DC and I2S_DD respectively. Note: if the DS90UH927Q is paired with a DS90UH926Q deserializer, the devices must be configured into 18-bit mode to allow usage of GPIO pins on the DS90UH927 serializer. To enable 18-bit mode, set serializer register reg_0x12[2] = 1. 18-bit mode will be auto-loaded into the deserializer from the serializer. See Table 1 for GPIO enable and configuration. TABLE 1. GPIO Enable and Configuration Description GPIO3 GPIO2 GPIO1 GPIO0 Device Forward Channel Back Channel 0x0F = 0x05 DS90UH927Q 0x0F = 0x03 DS90UH926/8Q 0x1F = 0x05 0x1F = 0x03 DS90UH927Q 0x0E = 0x30 0x0E = 0x50 DS90UH926/8Q 0x1E = 0x50 0x1E = 0x30 DS90UH927Q 0x0E = 0x03 0x0E = 0x05 DS90UH926/8Q 0x1E = 0x05 0x1E = 0x03 DS90UH927Q 0x0D = 0x03 0x0D = 0x05 DS90UH926/8Q 0x1D = 0x05 0x1D = 0x03 Copyright © 1999-2012, Texas Instruments Incorporated 19 DS90UH927Q The input value present on GPIO[3:0] may also be read from register, or configured to local output mode (Table 5). GPIO[8:5] GPIO_REG[8:5] are register-only GPIOs and may be programmed as outputs or read as inputs through local register bits only. Where applicable, these bits are shared with I2S pins and will override I2S input if enabled into REG_GPIO mode. See Table 2 for GPIO enable and configuration. Note: Local GPIO value may be configured and read either through local register access, or remote register access through the Low-Speed Bidirectional Control Channel. Configuration and state of these pins are not transported from serializer to deserializer as is the case for GPIO[3:0]. TABLE 2. GPIO_REG and GPIO Local Enable and Configuration Description Register Configuration GPIO_REG8 0x11 = 0x01 Output, L 0x11 = 0x09 Output, H 0x11 = 0x03 Input, Read: 0x1D[0] GPIO_REG7 GPIO_REG6 GPIO_REG5 GPIO3 GPIO2 GPIO1 GPIO0 Function 0x10 = 0x01 Output, L 0x10 = 0x09 Output, H 0x10 = 0x03 Input, Read: 0x1C[7] 0x10 = 0x01 Output, L 0x10 = 0x09 Output, H 0x10 = 0x03 Input, Read: 0x1C[6] 0x0F = 0x01 Output, L 0x0F = 0x09 Output, H 0x0F = 0x03 Input, Read: 0x1C[5] 0x0F = 0x01 Output, L 0x0F = 0x09 Output, H 0x0F = 0x03 Input, Read: 0x1C[3] 0x0E = 0x01 Output, L 0x0E = 0x09 Output, H 0x0E = 0x03 Input, Read: 0x1C[2] 0x0E = 0x01 Output, L 0x0E = 0x09 Output, H 0x0E = 0x03 Input, Read: 0x1C[1] 0x0D = 0x01 Output, L 0x0D = 0x09 Output, H 0x0D = 0x03 Input, Read: 0x1C[0] I2S AUDIO INTERFACE The DS90UH927Q serializer features six I2S input pins that, when paired with a DS90UH928Q deserializer, supports surround sound audio applications. The bit clock (I2S_CLK) supports frequencies between 1MHz and the smaller of <PCLK/2 or <13MHz. Four I2S data inputs transport two channels of I2S-formatted digital audio each, with each channel delineated by the word select (I2C_WC) input. I2S audio transport is not available in Backwards Compatibility Mode (BKWD = 1). 30193011 FIGURE 15. I2S Connection Diagram 20 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q 30193012 FIGURE 16. I2S Frame Timing Diagram When paired with a DS90UH926Q, the DS90UH927Q I2S interface supports a single I2S data input through I2S_DA (24-bit video mode), or two I2S data inputs through I2S_DA and I2S_DB (18-bit video mode). Table 3 covers several common I2S sample rates: TABLE 3. Audio Interface Frequencies Sample Rate (kHz) I2S Data Word Size (bits) I2S CLK (MHz) 32 16 1.024 44.1 16 1.411 48 16 1.536 96 16 3.072 192 16 6.144 32 24 1.536 44.1 24 2.117 48 24 2.304 96 24 4.608 192 24 9.216 32 32 2.048 44.1 32 2.822 48 32 3.072 96 32 6.144 192 32 12.288 I2S TRANSPORT MODES By default, audio is packetized and transmitted during video blanking periods in dedicated Data Island Transport frames. Data Island frames may be disabled from control registers if Forward Channel Frame Transport of I2S data is desired. In this mode, only I2S_DA is transmitted to the DS90UH928Q deserializer. If connected to a DS90UH926Q deserializer, I2S_DA and I2S_DB are transmitted. Surround Sound Mode, which transmits all four I2S data inputs (I2S_D[A..D]), may only be operated in Data Island Transport mode. This mode is only available when connected to a DS90UH928Q deserializer. I2S REPEATER I2S audio may be fanned-out and propagated in the repeater application. By default, data is propagated via Data Island Transport on the FPD-Link interface during the video blanking periods. If frame transport is desired, then the I2S pins should be connected from the deserializer to all serializers. Activating surround sound at the top-level deserializer automatically configures downstream DS90UH927Q serializers and DS90UH928Q deserializers for surround sound transport utilizing Data Island Transport. If 4-channel operation utilizing I2S_DA and I2S_DB only is desired, this mode must be explicitly set in each serializer and deserializer control register throughout the repeater tree (Table 5). A DS90UH927Q serializer configured in repeater mode may also regenerate I2S audio from its I2S input pins in lieu of Data Island frames. See the HDCP Repeater Connection Diagram (Figure 19) and the I2C Control Registers (Table 5) for additional details. Copyright © 1999-2012, Texas Instruments Incorporated 21 DS90UH927Q HDCP The Cipher function is implemented in the serializer per HDCP v1.3 specification. The DS90UH927Q provides HDCP encryption of audiovisual content when connected to an HDCP capable FPD-Link III deserializer. HDCP authentication and shared key generation is performed using the HDCP Control Channel which is embedded in the forward and backward channels of the serial link. On-chip Non-Volatile Memory (NVM) is used to store the HDCP keys. The confidential HDCP keys are loaded by TI during the manufacturing process and are not accessible external to the device. The DS90UH927Q uses the Cipher engine to encrypt the data as per HDCP v1.3. The encrypted data is sent through the FPDLink III interface. HDCP REPEATER The supported HDCP Repeater application provides a mechanism to extend HDCP transmission over multiple links to multiple display devices. It authenticates all HDCP Receivers in the system and distributes protected content to the HDCP Receivers using the encryption mechanisms provided in the HDCP specification. REPEATER CONFIGURATION In HDCP repeater application, this document refers to the DS90UH927Q as the HDCP Transmitter (TX), and refers to the DS90UH928Q as the HDCP Receiver (RX). Figure 17 shows the maximum configuration supported for HDCP Repeater implementations using the DS90UH925/7Q (TX), and DS90UH926/8Q (RX). Two levels of HDCP Repeaters are supported with a maximum of three HDCP Transmitters per HDCP Receiver. To ensure parallel video interface compatibility, repeater nodes should feature either the DS90UH926Q/DS90UH925Q (RX/TX) chipset or the DS90UH927Q/DS90UH928Q (RX/TX) chipset. 30193010 FIGURE 17. HDCP Maximum Repeater Application In a repeater application, the I2C interface at each TX and RX may be configured to transparently pass I2C communications upstream or downstream to any I2C device within the system. This includes a mechanism for assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses. To support HDCP Repeater operation, the RX includes the ability to control the downstream authentication process, assemble the KSV list for downstream HDCP Receivers, and pass the KSV list to the upstream HDCP Transmitter. An I2C master within the RX communicates with the I2C slave within the TX. The TX handles authenticating with a downstream HDCP Receiver and makes 22 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q status available through the I2C interface. The RX monitors the transmit port status for each TX and reads downstream KSV and KSV list values from the TX. In addition to the I2C interface used to control the authentication process, the HDCP Repeater implementation includes two other interfaces. The FPD-Link LVDS interface provides the unencrypted video data in 24-bit RGB format and includes the DE/VS/HS control signals. In addition to providing the RGB video data, the LVDS interface communicates control information and packetized audio data during video blanking intervals. A separate I2S audio interface may optionally be used to send I2S audio data between the HDCP Receiver and HDCP Transmitter in place of using the packetized audio. All audio and video data is decrypted at the output of the HDCP Receiver and is re-encrypted by the HDCP Transmitter. Figure 18 provides more detailed block diagram of a 1:2 HDCP repeater configuration. If video data is output to a local display, White Balancing and Hi-FRC dithering functions should not be used as they will block encrypted I2S audio. 30193032 FIGURE 18. HDCP 1:2 Repeater Configuration REPEATER CONNECTIONS The HDCP Repeater requires the following connections between the HDCP Receiver and each HDCP Transmitter Figure 19. 1. 2. 3. 4. 5. 6. Video Data – Connect all FPD-Link data and clock pairs I2C – Connect SCL and SDA signals. Both signals should be pulled up to VDD33 or VDDIO = 3.0V to 3.6V with 4.7 kΩ resistors. Audio (optional) – Connect I2S_CLK, I2S_WC, and I2S_Dx signals. IDx pin – Each HDCP Transmitter and Receiver must have an unique I2C address. REPEAT pin — All HDCP Transmitters and Receivers must be set into Repeater Mode. Interrupt pin – Connect DS90UH928Q INTB_IN pin to DS90UH927Q INTB pin. The signal must be pulled up to VDDIO. Copyright © 1999-2012, Texas Instruments Incorporated 23 DS90UH927Q 30193042 FIGURE 19. HDCP Repeater Connection Diagram REPEATER FAN-OUT ELECTRICAL REQUIREMENTS Repeater applications requiring fan-out from one DS90UH928Q deserializer to up to three DS90UH927Q serializers requires special considerations for routing and termination of the FPD-Link differential traces. Figure 20 details the requirements that must be met for each signal pair: 30193003 FIGURE 20. FPD-Link Fan-Out Electrical Requirements 24 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q HDCP I2S AUDIO ENCRYPTION When HDCP is active, packetized Data Island Transport audio is also encrypted along with the video data per HDCP v.1.3. I2S audio transmitted in Forward Channel Frame Transport mode is not encrypted. Depending on the quality and specifications of the audiovisual source, HDCP encryption of digital audio may be required. System designers should consult the specific HDCP specifications to determine if encryption of digital audio is required by the specific application audiovisual source. Copyright © 1999-2012, Texas Instruments Incorporated 25 DS90UH927Q BUILT IN SELF TEST (BIST) An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high speed serial link and the low-speed back channel without external data connections. This is useful in the prototype stage, equipment production, in-system test, and system diagnostics. BIST CONFIGURATION AND STATUS The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may select either an external PCLK or the 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST configuration register. When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel frame. The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. LOCK status is valid throughout the entire duration of BIST. See Figure 21 for the BIST mode flow diagram. SAMPLE BIST SEQUENCE Step 1: For the DS90UH927Q paired with a FPD-Link III Deserializer, BIST Mode is enabled via the BISTEN pin of Deserializer. The desired clock source is selected through the deserializer BISTC pin. Step 2: The DS90UH927Q serializer is awakened through the back channel if it is not already on. An all-zeros pattern is balanced, scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate. Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will remain HIGH. If there one or more errors were detected, the PASS output will output constant LOW. The PASS output state is held until a new BIST is run, the device is RESET, or the device is powered down. BIST duration is user-controlled and may be of any length. The link returns to normal operation after the deserializer BISTEN pin is low. Figure 22 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or reducing signal condition enhancements (Rx Equalization). 30193043 FIGURE 21. BIST Mode Flow Diagram 26 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q FORWARD CHANNEL AND BACK CHANNEL ERROR CHECKING While in BIST mode, the serializer stops sampling the FPD-Link input pins and switches over to an internal all zeroes pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing, etc. and is transmitted over the serial link to the deserializer. The deserializer, on locking to the serial stream, compares the recovered serial stream with all-zeroes and records any errors in status registers. Errors are also dynamically reported on the PASS pin of the deserializer. The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream, as indicated by link detect status (register bit 0x0C[0] - Table 5). CRC errors are recorded in an 8-bit register in the deserializer. The register is cleared when the serializer enters the BIST mode. As soon as the serializer enters BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST mode CRC error register is active in BIST mode only and keeps the record of the last BIST run until cleared or the serializer enters BIST mode again. 30193064 FIGURE 22. BIST Waveforms INTERNAL PATTERN GENERATION The DS90UH927Q serializer provides an internal pattern generation feature. It allows basic testing and debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down mode, the test pattern will be displayed even if no input is applied. If no clock is received, the test pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to Application Note AN-2198. PATTERN OPTIONS The DS90UH927Q serializer pattern generator is capable of generating 17 default patterns for use in basic testing and debugging of panels. Each can be inverted using register bits (Table 5), shown below: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. White/Black (default/inverted) Black/White Red/Cyan Green/Magenta Blue/Yellow Horizontally Scaled Black to White/White to Black Horizontally Scaled Black to Red/Cyan to White Horizontally Scaled Black to Green/Magenta to White Horizontally Scaled Black to Blue/Yellow to White Vertically Scaled Black to White/White to Black Vertically Scaled Black to Red/Cyan to White Vertically Scaled Black to Green/Magenta to White Vertically Scaled Black to Blue/Yellow to White Custom Color (or its inversion) configured in PGRS Copyright © 1999-2012, Texas Instruments Incorporated 27 DS90UH927Q 15. Black-White/White-Black Checkerboard (or custom checkerboard color, configured in PGCTL) 16. YCBR/RBCY VCOM pattern, orientation is configurable from PGCTL 17. Color Bars (White, Yellow, Cyan, Green, Magenta, Red, Blue, Black) – Note: not included in the auto-scrolling feature Additionally, the Pattern Generator incorporates one user-configurable full-screen 24-bit color, which is controlled by the PGRS, PGGS, and PGBS registers. This is pattern #14. One of the pattern options is statically selected in the PGCTL register when AutoScrolling is disabled. The PGTSC and PGTSO1-8 registers control the pattern selection and order when Auto-Scrolling is enabled. COLOR MODES By default, the Pattern Generator operates in 24-bit color mode, where all bits of the Red, Green, and Blue outputs are enabled. 18-bit color mode can be activated from the configuration registers (Table 5). In 18-bit mode, the 6 most significant bits (bits 7-2) of the Red, Green, and Blue outputs are enabled; the 2 least significant bits will be 0. VIDEO TIMING MODES The Pattern Generator has two video timing modes – external and internal. In external timing mode, the Pattern Generator detects the video frame timing present on the DE and VS inputs. If Vertical Sync signaling is not present on VS, the Pattern Generator determines Vertical Blank by detecting when the number of inactive pixel clocks (DE = 0) exceeds twice the detected active line length. In internal timing mode, the Pattern Generator uses custom video timing as configured in the control registers. The internal timing generation may also be driven by an external clock. By default, external timing mode is enabled. Internal timing or Internal timing with External Clock are enabled by the control registers (Table 5). EXTERNAL TIMING In external timing mode, the Pattern Generator passes the incoming DE, HS, and VS signals unmodified to the video control outputs after a two pixel clock delay. It extracts the active frame dimensions from the incoming signals in order to properly scale the brightness patterns. If the incoming video stream does not use the VS signal, the Pattern Generator determines the Vertical Blank time by detecting a long period of pixel clocks without DE asserted. PATTERN INVERSION The Pattern Generator also incorporates a global inversion control, located in the PGCFG register, which causes the output pattern to be bitwise-inverted. For example, the full screen Red pattern becomes full-screen cyan, and the Vertically Scaled Black to Green pattern becomes Vertically Scaled White to Magenta. AUTO SCROLLING The Pattern Generator supports an Auto-Scrolling mode, in which the output pattern cycles through a list of enabled pattern types. A sequence of up to 16 patterns may be defined in the registers. The patterns may appear in any order in the sequence and may also appear more than once. ADDITIONAL FEATURES Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It consists of the Pattern Generator Indirect Address (PGIA reg_0x66 — Table 5) and the Pattern Generator Indirect Data (PGID reg_0x67 — Table 5). See TI application Note AN-2198. 28 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q Serial Control Bus The DS90UH927Q may also be configured by the use of a I2C compatible serial control bus. Multiple devices may share the serial control bus (up to 10 device addresses supported). The device address is set via a resistor divider (R1 and R2 — see Figure 23 below) connected to the IDx pin. 30193001 FIGURE 23. Serial Control Bus Connection The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pull-up resistor to VDD33 or VDDIO = 3.0V to 3.6V. For most applications, a 4.7kΩ pull-up resistor to VDD33 is recommended. However, the pull-up resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low. The IDx pin configures the control interface to one of 10 possible device addresses. A pull-up resistor and a pull-down resistor may be used to set the appropriate voltage ratio between the IDx input pin (VR2) and VDD33, each ratio corresponding to a specific device address. See Table 5 below. TABLE 4. Serial Control Bus Addresses for IDx # Ideal Ratio VR2 / VDD33 Ideal VR2 (V) Suggested Resistor R1 kΩ (1% tol) Suggested Resistor R2 kΩ (1% tol) Address 7'b Address 8'b 1 0 0 Open 40.2 or >10 0x0C 0x18 2 0.306 1.011 221 97.6 0x13 0x26 3 0.350 1.154 210 113 0x14 0x28 4 0.393 1.298 196 127 0x15 0x2A 5 0.440 1.452 182 143 0x16 0x2C 6 0.483 1.594 169 158 0x17 0x2E 7 0.529 1.745 147 165 0x18 0x30 8 0.572 1.887 143 191 0x19 0x32 9 0.618 2.040 121 196 0x1A 0x34 10 0.768 2.535 90.9 301 0x1B 0x36 The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See Figure 24 belowFigure 24 Copyright © 1999-2012, Texas Instruments Incorporated 29 DS90UH927Q 30193051 FIGURE 24. START and STOP Conditions To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 25 and a WRITE is shown in Figure 26. 30193038 FIGURE 25. Serial Control Bus — READ 30193039 FIGURE 26. Serial Control Bus — WRITE The I2C Master located at the DS90UH927Q serializer must support I2C clock stretching. For more information on I2C interface requirements and throughput considerations, please refer to TI Application Note SNLA131. 30 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q TABLE 5. Serial Control Bus Registers ADD (dec) ADD (hex) Register Name 0 0x00 I2C Device ID 1 0x01 Reset Bit(s) Register Type Default (hex) Function Description 7:1 RW IDx Device ID 7–bit address of Serializer Note: Read-only unless bit 0 is set 0 RW 7 RW ID Setting I2C ID Setting 0: Device ID is from IDx pin 1: Register I2C Device ID overrides IDx pin 0x00 Remote Auto Power Down 6:2 3 0x03 General Configuration Remote Auto Power Down 0: Do not power down when no Bidirectional Control Channel link is detected (default) 1: Enable power down when no Bidirectional Control Channel link is detected Reserved. 1 RW Digital RESET1 Reset the entire digital block including registers This bit is self-clearing. 0: Normal operation (default) 1: Reset 0 RW Digital RESET0 Reset the entire digital block except registers This bit is self-clearing 0: Normal operation (default) 1: Reset 7 RW Back channel CRC Checker Enable Back Channel Check Enable 0: Disable 1: Enable (default) 0xD2 6 Reserved. 5 RW I2C Remote Write Auto Acknowle dge Automatically Acknowledge I2C Remote Write When enabled, I2C writes to the Deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are immediately acknowledged without waiting for the Deserializer to acknowledge the write. This allows higher throughput on the I2C bus. Note: this mode will prevent any NACK or read/write error indication from a remote device from reaching the I2C master. 0: Disable (default) 1: Enable 4 RW Filter Enable HS, VS, DE two clock filter When enabled, pulses less than two full PCLK cycles on the DE, HS, and VS inputs will be rejected 0: Filtering disable 1: Filtering enable (default) 3 RW I2C Pass- I2C Pass-Through Mode through Read/Write transactions matching any entry in the DeviceAlias registers will be passed through to the remote deserializer I2C interface. 0: Pass-Through Disabled (default) 1: Pass-Through Enabled 1 RW PCLK Auto Switch over to internal OSC in the absence of PCLK 0: Disable auto-switch 1: Enable auto-switch (default) 0 RW TRFB Reserved 2 Copyright © 1999-2012, Texas Instruments Incorporated Reserved 31 DS90UH927Q ADD (dec) ADD (hex) Register Name 4 0x04 Mode Select Bit(s) Register Type Default (hex) 7 RW 0x80 Function Description Failsafe State Input Failsafe State 0: Failsafe to High 1: Failsafe to Low (default) 6 5 Reserved RW CRC Error Clear back channel CRC Error Counters Reset This bit is NOT self-clearing 0: Normal Operation (default) 1: Clear Counters 3 RW BKWD Backward Compatible mode set by BKWD pin or ModeOver register ride 0: BC mode is set by BKWD pin (default) 1: BC mode is set by register bit 2 RW BKWD Backward compatibility mode, device to pair with DS90UR906Q, DS90UR908Q, or DS90UR916Q 0: Normal HDCP device (default) 1: Compatible with 906/908/916 1 RW LFMODE Override Frequency mode set by LFMODE pin or register 0: Frequency mode is set by LFMODE pin (default) 1: Frequency mode is set by register bit 0 RW LFMODE Frequency mode select 4 Reserved 0: High frequency mode (15MHz ≤ RxCLKIN ≤ 85MHz) (default) 1: Low frequency mode (5MHz ≤ RxCLKIN < 15 MHz) 32 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q ADD (dec) ADD (hex) Register Name 5 0x05 I2C Control 6 0x06 DES ID Bit(s) Register Type 7:5 Default (hex) Function 0x00 Reserved 4:3 RW SDA Output Delay SDA output delay Configures output delay on the SDA output. Setting this value will increase output delay in units of 40ns. Nominal output delay values for SCL to SDA are: 00: 240ns (default) 01: 280ns 10: 320ns 11: 360ns 2 RW Local Write Disable Disable Remote Writes to Local Registers Setting this bit to a 1 will prevent remote writes to local device registers from across the control channel. This prevents writes to the Serializer registers from an I2C master attached to the Deserializer. Setting this bit does not affect remote access to I2C slaves at the Serializer. 0: Enable (default) 1: Disable 1 RW I2C Bus Timer Speedup Speed up I2C Bus Watchdog Timer 0: Watchdog Timer expires after ~1s (default) 1: Watchdog Timer expires after ~50µs 0 RW I2C Bus timer Disable Disable I2C Bus Watchdog Timer When the I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signaling occurs for approximately 1s, the I2C bus will be assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL 0: Enable (default) 1: Disable 7:1 RW DES Device ID 7-bit Deserializer Device ID Configures the I2C Slave ID of the remote Deserializer. A value of 0 in this field disables I2C access to the remote Deserializer. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but should also assert the FREEZE DEVICE ID bit to prevent overwriting by the Bidirectional Control Channel. 0x00 0 7 0x07 Slave ID 0 Description 7:1 0 Copyright © 1999-2012, Texas Instruments Incorporated Reserved RW 0X00 Slave Device ID 0 7-bit Remote Slave Device ID 0 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Device Alias ID 0, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. Reserved 33 DS90UH927Q ADD (dec) ADD (hex) Register Name Bit(s) Register Type Default (hex) 8 0x08 Slave Alias 0 7:1 RW 10 0x0A CRC Errors 7:0 11 0x0B 7:0 12 0x0C Function Description 0x00 Slave Device Alias ID 0 7-bit Remote Slave Device Alias ID 0 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 0 register. A value of 0 in this field disables access to the remote I2C Slave. R 0x00 CRC Error Number of Back Channel CRC errors – 8 least LSB significant bits. Cleared by 0x04[5] R 0x00 CRC Error Number of Back Channel CRC errors – 8 most MSB significant bits. Cleared by 0x04[5] 0 13 34 0x0D General Status GPIO0 Configuration Reserved 7:4 0x00 Reserved 3 R BIST CRC Back Channel CRC error during BIST Error communication with Deserializer. This bit is cleared upon loss of link, restart of BIST, or assertion of CRC ERROR RESET in register 0x04. 0: No CRC errors detected during BIST (default) 1: CRC Errors detected during BIST 2 R PCLK Detect 1 R DES Error CRC error during BIST communication with Deserializer. This bit is cleared upon loss of link or assertion of 0x04[5] 0: No CRC errors detected (default) 1: CRC errors detected 0 R LINK Detect LINK Detect Status 0: Cable link not detected (default) 1: Cable link detected 7:4 R Revision ID Revision ID: 0010: Production Device 3 RW GPIO0 Output Value Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled. 0: Output LOW (default) 1: Output HIGH 2 RW GPIO0 Remote Enable Remote GPIO Control 0: Disable GPIO control from remote Deserializer (default) 1: Enable GPIO control from remote Deserializer. The GPIO pin will be an output, and the value is received from the remote Deserializer. 1 RW GPIO0 Direction Local GPIO Direction 0: Output (default) 1: Input 0 RW GPIO0 Enable GPIO Function Enable 0: Enable normal operation (default) 1: Enable GPIO operation 0x20 Pixel Clock Status 0: Valid PCLK not detected (default) 1: Valid PCLK detected Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q ADD (dec) ADD (hex) Register Name 14 0x0E GPIO1 and GPIO2 Configuration 15 0x0F GPIO3 Configuration Bit(s) Register Type Default (hex) 7 RW 0x00 6 Function Description GPIO2 Output Value Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled. 0: Output LOW (default) 1: Output HIGH RW GPIO2 Remote Enable Remote GPIO Control 0: Disable GPIO control from remote Deserializer (default) 1: Enable GPIO control from remote Deserializer. The GPIO pin will be an output, and the value is received from the remote Deserializer. 5 RW GPIO2 Direction Local GPIO Direction 0: Output (default) 1: Input 4 RW GPIO2 Enable GPIO Function Enable 0: Enable normal operation (default) 1: Enable GPIO operation 3 RW GPIO1 Output Value Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled. 0: Output LOW (default) 1: Output HIGH 2 RW GPIO1 Remote Enable Remote GPIO Control 0: Disable GPIO control from remote Deserializer (default) 1: Enable GPIO control from remote Deserializer. The GPIO pin will be an output, and the value is received from the remote Deserializer. 1 RW GPIO1 Direction Local GPIO Direction 1: Input 0: Output 0 RW GPIO1 Enable GPIO function enable 1: Enable GPIO operation 0: Enable normal operation 7:4 0x00 Reserved 3 RW GPIO3 Output Value Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled. 0: Output LOW (default) 1: Output HIGH 2 RW GPIO3 Remote Enable Remote GPIO Control 0: Disable GPIO control from remote Deserializer (default) 1: Enable GPIO control from remote Deserializer. The GPIO pin will be an output, and the value is received from the remote Deserializer. 1 RW GPIO3 Direction Local GPIO Direction 0: Output (default) 1: Input 0 RW GPIO3 Enable GPIO Function Enable 0: Enable normal operation (default) 1: Enable GPIO operation Copyright © 1999-2012, Texas Instruments Incorporated 35 DS90UH927Q ADD (dec) ADD (hex) Register Name 16 0x10 GPIO_REG5 and GPIO_REG6 Configuration Bit(s) Register Type Default (hex) 7 RW 0x00 6 0x11 GPIO_REG7 and GPIO_REG8 Configuration GPIO_RE Local GPIO Output Value This value is output on G6 Output the GPIO pin when the GPIO function is enabled, Value and the local GPIO direction is Output. 0: Output LOW (default) 1: Output HIGH Reserved RW GPIO_RE Local GPIO Direction G6 0: Output (default) Direction 1: Input 4 RW GPIO_RE GPIO Function Enable G6 Enable 0: Enable normal operation (default) 1: Enable GPIO operation 3 RW GPIO_RE Local GPIO Output Value This value is output on G5 Output the GPIO pin when the GPIO function is enabled, Value and the local GPIO direction is Output. 0: Output LOW (default) 1: Output HIGH Reserved 1 RW GPIO_RE GPIO Function Enable G5 0: Enable normal operation (default) Direction 1: Enable GPIO operation 0 RW GPIO_RE GPIO Function Enable G5 Enable 0: Enable normal operation (default) 1: Enable GPIO operation 7 RW 6 0x00 GPIO_RE Local GPIO Output Value This value is output on G8 Output the GPIO pin when the GPIO function is enabled, Value and the local GPIO direction is Output. 0: Output LOW (default) 1: Output HIGH Reserved 5 RW GPIO_RE Local GPIO Direction G8 0: Output (default) Direction 1: Input 4 RW GPIO_RE GPIO Function Enable G8 Enable 0: Enable normal operation (default) 1: Enable GPIO operation 3 RW GPIO_RE Local GPIO Output Value This value is output on G7 Output the GPIO pin when the GPIO function is enabled, Value and the local GPIO direction is Output. 0: Output LOW (default) 1: Output HIGH 1 RW GPIO_RE Local GPIO Direction G7 0: Output (default) Direction 1: Input 0 RW GPO_RE GPIO Function Enable G7 Enable 0: Enable normal operation (default) 1: Enable GPIO operation 2 36 Description 5 2 17 Function Reserved Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q ADD (dec) ADD (hex) Register Name 18 0x12 Data Path Control Bit(s) Register Type 7 Default (hex) Function 0x00 Description Reserved 6 RW Pass RGB Pass RGB on DE Setting this bit causes RGB data to be sent independent of DE in DS90UH927, which can be used to allow DS90UH927 to interoperate with DS90UB926, DS90UB928, and DS90UR906. However, setting this bit prevents HDCP operation and blocks packetized audio. This bit does not need to be set in Backward Compatibility mode. 0: Normal operation (default) 1: Pass RGB independent of DE 5 RW DE Polarity This bit indicates the polarity of the DE (Data Enable) signal. 0: DE is positive (active high, idle low) (default) 1: DE is inverted (active low, idle high) 4 RW I2S Repeater Regen Regenerate I2S Data From Repeater I2S Pins 0: Repeater pass through I2S from video pins (default) 1: Repeater regenerate I2S from I2S pins 3 RW I2S I2S Channel B Override Channel B 0: Set I2S Channel B Disabled (default) Enable 1: Set I2S Channel B Enable from reg_12[0] Override 2 RW 18-bit Video Select Video Color Depth Mode 0: Select 24-bit video mode (default) 1: Select 18-bit video mode 1 RW I2S Transport Select Select I2S Transport Mode 0: Enable I2S Data Island Transport (default) 1: Enable I2S Data Forward Channel Frame Transport 0 RW I2S I2S Channel B Enable Channel B 0: I2S Channel B disabled (default) Enable 1: Enable I2S Channel B Copyright © 1999-2012, Texas Instruments Incorporated 37 DS90UH927Q ADD (dec) ADD (hex) Register Name 19 0x13 General Purpose Control Bit(s) Register Type Default (hex) 7 R 0x10 6 5 Function Description MAPSEL Mode Returns Map Select Mode (MAPSEL) pin status RW MAPSEL Override FPD-Link Map Select (MAPSEL) set by input pin or register 0: Map Select is set by input pin (default) 1: Map Select is set by register bit 0x13[5] RW MAPSEL Value FPD-Link Map Select (MAPSEL) value when 0x13 [6] is set 0: LSBs on RxIN3± (default) 1: MSBs on RxIN3± 4 3 Reserved R LFMODE Status Low Frequency Mode (LFMODE) pin status 0: 15 ≤ RxCLKIN ≤ 85MHz (default) 1: 5 ≤ RxCLKIN < 15MHz 20 22 38 0x14 0x16 BIST Control BCC Watchdog Control 2 R REPEAT Status Repeater Mode (REPEAT) pin Status 0: Non-repeater (default) 1: Repeater 1 R BKWD Status Backward Compatible Mode (BKWD) Status 0: Compatible to DS90UB926/8Q (default) 1: Backward compatible to DS90UR906/8Q 0 R I2S_DB Status I2S Channel B Mode (I2S_DB) Status 0: I2S_DB inactive (default) 1: I2S_DB active 7:3 0x00 Reserved 2:1 RW OSC Clock Source Internal OSC clock select for Functional Mode or BIST. Functional Mode when PCLK is not present and 0x03[1]=1. 00: 33 MHz Oscillator (default) 01: 33 MHz Oscillator Clock Source in BIST mode 00: External Pixel Clock (default) 01: 33 MHz Oscillator Note: In LFMODE=1, the internal oscillator is 12.5MHz 0 R BIST Enable BIST Control 0: Disabled (default) 1: Enabled 7:1 RW Timer Value The watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. This field sets the Bidirectional Control Channel Watchdog Timeout value in units of 2 milliseconds. This field should not be set to 0. 0 RW Timer Control Disable BCC Watchdog Timer 0: Enable BCC Watchdog Timer operation (default) 1: Disable BCC Watchdog Timer operation 0xFE Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q ADD (dec) ADD (hex) Register Name 23 0x17 I2C Control Bit(s) Register Type Default (hex) 7 RW 0x1E 6:4 RW SDA Hold Internal SDA Hold Time Time Configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 40 nanoseconds. 3:0 RW I2C Filter Depth Function Description I2C Pass All Pass All 0: Enable Forward Control Channel pass-through only of I2C accesses to I2C Slave IDs matching either the remote Deserializer Slave ID or the remote Slave ID. (default) 1: Enable Forward Control Channel pass-through of all I2C accesses to I2C Slave IDs that do not match the Serializer I2C Slave ID. Configures the maximum width of glitch pulses on the SCL and SDA inputs that will be rejected. Units are 5 nanoseconds. 24 0x18 SCL High Time 7:0 RW 0xA1 SCL HIGH I2C Master SCL High Time Time This field configures the high pulse width of the SCL output when the Serializer is the Master on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency. 25 0x19 SCL Low Time 7:0 RW 0xA5 SCL LOW I2C SCL Low Time Time This field configures the low pulse width of the SCL output when the Serializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 40 ns for the nominal oscillator clock frequency. 26 0x1A Data Path Control 2 7 RW 0x00 Block I2S Auto Config 6:1 27 0x1B BIST BC Error Count Reserved 0 RW 7:0 R Copyright © 1999-2012, Texas Instruments Incorporated Block automatic I2S mode configuration (repeater only) 0: I2S mode (2-channel, 4-channel, or surround) is detected from the in-band audio signaling 1: Disable automatic detection of I2S mode 0x00 I2S Surround Enable 5.1- or 7.1-channel I2S audio transport 0: 2-channel or 4-channel I2S audio is enabled as configured in register 0x12 bits 3 and 0 (default) 1: 5.1- or 7.1-channel audio is enabled Note that I2S Data Island Transport is the only option for surround audio. Also note that in a repeater, this bit may be overridden by the in-band I2S mode detection. BIST BC Errorr BIST Back Channel CRC Error Counter This register stores the back-channel CRC error count during BIST Mode (saturates at 255 errors). Clears when a new BIST is initiated or by 0x04[5] 39 DS90UH927Q ADD (dec) ADD (hex) Register Name 28 0x1C GPIO Pin Status 1 Bit(s) Register Type Default (hex) 7 R 0x00 6 R GPIO_RE GPIO_REG6 Input Pin Status G6 Pin Status valid only if set to GPI (input) mode Status 5 R GPIO_RE GPIO_REG5 Input Pin Status G5 Pin Status valid only if set to GPI (input) mode Status 3 R GPIO3 Pin GPIO3 Input Pin Status Status Status valid only if set to GPI (input) mode 2 R GPIO2 Pin GPIO2 Input Pin Status Status Status valid only if set to GPI (input) mode 1 R GPIO1 Pin GPIO1 Input Pin Status Status Status valid only if set to GPI (input) mode 0 R GPIO0 Pin GPIO0 Input Pin Status Status Status valid only if set to GPI (input) mode 4 29 30 40 0x1D 0x1F Function Description GPIO_RE GPIO_REG7 Input Pin Status G7 Pin Status valid only if set to GPI (input) mode Status Reserved GPIO Pin Status 2 7:1 0 R 0x00 Frequency Counter 7:0 RW Reserved GPIO_RE GPIO_REG8 Input Pin Status G8 Pin Status valid only if set to GPI (input) mode Status 0x00 Frequency Frequency Counter Control Counter Write: Measure number of pixel clock periods in written interval (40ns units) Read: Return number of pixel clock periods counted Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q ADD (dec) ADD (hex) Register Name 32 0x20 Deserializer Capabilities Bit(s) Register Type Default (hex) 7 RW 0x00 Function Description Freeze Freeze Deserializer Capabilities DES CAP Prevent auto-loading of the Deserializer Capabilities by the Bidirectional Control Channel. The Capabilities will be frozen at the values written in registers 0x20 and 0x21. 0: Normal operation (default) 1: Freeze 6:2 Reserved 1 RW HD Audio Deserializer supports 24-bit video concurrently with HD audio This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel. 0: Normal operation (default) 1: Freeze 0 RW FC GPIO Deserializer supports GPIO in the Forward Channel Frame This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel. 0: Normal operation (default) 1: Freeze Copyright © 1999-2012, Texas Instruments Incorporated 41 DS90UH927Q ADD (dec) ADD (hex) Register Name 100 0x64 Pattern Generator Control Bit(s) Register Type Default (hex) 7:4 RW 0x10 Function Pattern Fixed Pattern Select Generator Selects the pattern to output when in Fixed Pattern Select Mode. Scaled patterns are evenly distributed across the horizontal or vertical active regions. This field is ignored when Auto-Scrolling Mode is enabled. xxxx: normal/inverted 0000: Checkerboard 0001: White/Black (default) 0010: Black/White 0011: Red/Cyan 0100: Green/Magenta 0101: Blue/Yellow 0110: Horizontal Black-White/White-Black 0111: Horizontal Black-Red/White-Cyan 1000: Horizontal Black-Green/White-Magenta 1001: Horizontal Black-Blue/White-Yellow 1010: Vertical Black-White/White— Black 1011: Vertically Scaled Black to Red/White to Cyan 1100: Vertical Black-Green/White-Magenta 1101: Vertical Black-Blue/White-Yellow 1110: Custom color (or its inversion) configured in PGRS, PGGS, PGBS registers 1111: VCOM See TI App Note AN-2198. 3 42 Description Reserved 2 RW Color Bars Enable Color Bars Pattern 0: Color Bars disabled (default) 1: Color Bars enabled Overrides the selection from reg_0x64[7:4] 1 RW VCOM Pattern Reverse 0 RW Pattern Pattern Generator Enable Generator 0: Disable Pattern Generator (default) Enable 1: Enable Pattern Generator Reverse order of color bands in VCOM pattern 0: Color sequence from top left is (YCBR) (default) 1: Color sequence from top left is (RBCY) Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q ADD (dec) ADD (hex) Register Name 101 0x65 Pattern Generator Configuration 102 0x66 PGIA Bit(s) Register Type 7 Default (hex) Function 0x00 Description Reserved 6 RW Checkerb Scale Checkered Patterns: oard Scale 0: Normal operation (each square is 1x1 pixel) (default) 1: Scale checkered patterns (VCOM and checkerboard) by 8 (each square is 8x8 pixels) Setting this bit gives better visibility of the checkered patterns. 5 RW Custom Checkerb oard 4 RW PG 18–bit 18-bit Mode Select: Mode 0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of brightness. (default) 1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels of brightness and the R, G, and B outputs use the six most significant color bits. 3 RW External Clock Select External Clock Source: 0: Selects the internal divided clock when using internal timing (default) 1: Selects the external pixel clock when using internal timing. This bit has no effect in external timing mode (PATGEN_TSEL = 0). 2 RW Timing Select Timing Select Control: 0: the Pattern Generator uses external video timing from the pixel clock, Data Enable, Horizontal Sync, and Vertical Sync signals. (default) 1: The Pattern Generator creates its own video timing as configured in the Pattern Generator Total Frame Size, Active Frame Size. Horizontal Sync Width, Vertical Sync Width, Horizontal Back Porch, Vertical Back Porch, and Sync Configuration registers. See TI App Note AN-2198. 1 RW Color Invert Enable Inverted Color Patterns: 0: Do not invert the color output. (default) 1: Invert the color output. See TI App Note AN-2198. 0 RW Auto Scroll Auto Scroll Enable: 0: The Pattern Generator retains the current pattern. (default) 1: The Pattern Generator will automatically move to the next enabled pattern after the number of frames specified in the Pattern Generator Frame Time (PGFT) register. See TI App Note AN-2198. 7:0 RW Copyright © 1999-2012, Texas Instruments Incorporated 0x00 PG Indirect Address Use Custom Checkerboard Color 0: Use white and black in the Checkerboard pattern (default) 1: Use the Custom Color and black in the Checkerboard pattern This 8-bit field sets the indirect address for accesses to indirectly-mapped registers. It should be written prior to reading or writing the Pattern Generator Indirect Data register. See TI App Note AN-2198 43 DS90UH927Q ADD (dec) ADD (hex) Register Name Bit(s) Register Type Default (hex) 103 0x67 PGID 7:0 RW 112 0x70 Slave ID[1] 7:1 113 0x71 Slave ID[2] 7:1 Function Description 0x00 PG Indirect Data When writing to indirect registers, this register contains the data to be written. When reading from indirect registers, this register contains the read back value. See TI App Note AN-2198 RW 0x00 Slave ID 1 7-bit Remote Slave Device ID 1 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID1, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. RW 0x00 Slave ID 2 7-bit Remote Slave Device ID 2 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID2, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. 0 Reserved 0 114 0x72 Slave ID[3] 7:1 115 0x73 Slave ID[4] 7:1 116 0x74 Slave ID[5] 7:1 Reserved RW 0x00 Slave ID 3 7-bit Remote Slave Device ID 3 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID3, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. RW 0x00 Slave ID 4 7-bit Remote Slave Device ID 4 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID4, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. RW 0x00 Slave ID 5 7-bit Remote Slave Device ID 5 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID5, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. 0 Reserved 0 0 44 Reserved Reserved Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q ADD (dec) ADD (hex) Register Name Bit(s) Register Type Default (hex) 117 0x75 Slave ID[6] 7:1 RW 0x00 Slave ID 6 7-bit Remote Slave Device ID 6 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID6, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. 118 0x76 Slave ID[7] 7:1 RW 0x00 Slave ID 7 7-bit Remote Slave Device ID 7 Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID7, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. Function 0 Reserved 0 119 0x77 Slave Alias[1] 7:1 Reserved RW 0x00 Slave Alias ID 1 0 120 0x78 Slave Alias[2] 7:1 121 0x79 Slave Alias[3] 7:1 122 0x7A Slave Alias[4] 7:1 RW 0x00 Slave Alias ID 2 RW 0x00 Slave Alias ID 3 RW 0x00 Slave Alias ID 4 7-bit Remote Slave Device Alias ID 2 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID2 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved 0 Copyright © 1999-2012, Texas Instruments Incorporated 7-bit Remote Slave Device Alias ID 1 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID1 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved 0 0 Description 7-bit Remote Slave Device Alias ID 3 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID3 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved 7-bit Remote Slave Device Alias ID 4 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID4 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved 45 DS90UH927Q ADD (dec) ADD (hex) Register Name Bit(s) Register Type Default (hex) 123 0x7B Slave Alias[5] 7:1 RW 124 0x7C Slave Alias[6] 7:1 125 0x7D Slave Alias[7] 7:1 128 0x80 RX_BKSV0 129 0x81 130 Function Description 0x00 Slave Alias ID 5 7-bit Remote Slave Device Alias ID 5 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID5 register. A value of 0 in this field disables access to the remote I2C Slave. RW 0x00 Slave Alias ID 6 RW 0x00 Slave Alias ID 7 7:0 R 0x00 RX BKSV0 BKSV0: Value of byte 0 of the Deserializer KSV RX_BKSV1 7:0 R 0x00 RX BKSV1 BKSV1: Value of byte 1 of the Deserializer KSV 0x82 RX_BKSV2 7:0 R 0x00 RX BKSV2 BKSV2: Value of byte 2 of the Deserializer KSV 131 0x83 RX_BKSV3 7:0 R 0x00 RX BKSV3 BKSV3: Value of byte 3of the Deserializer KSV. 132 0x84 RX_BKSV4 7:0 R 0x00 RX BKSV4 BKSV4: Value of byte 4of the Deserializer KSV. 144 0x90 TX_KSV0 7:0 R 0x00 TX KSV0 KSV0: Value of byte 0 of the Serializer KSV. 145 0x91 TX_KSV1 7:0 R 0x00 TX KSV1 KSV1: Value of byte 1 of the Serializer KSV. 146 0x92 TX_KSV2 7:0 R 0x00 TX KSV2 KSV2: Value of byte 2 of the Serializer KSV. 147 0x93 TX_KSV3 7:0 R 0x00 TX KSV3 KSV3: Value of byte 3 of the Serializer KSV. 148 0x94 TX_KSV4 7:0 R 0x00 TX KSV4 KSV4: Value of byte 4 of the Serializer KSV. 152 0x98 TX_AN0 7:0 R 0x00 TX AN0 TX_AN0: Value of byte 0 of the Serializer AN Value 153 0x99 TX_AN1 7:0 R 0x00 TX AN1 TX_AN1: Value of byte 1 of the Serializer AN Value 154 0x9A TX_AN2 7:0 R 0x00 TX AN2 TX_AN2: Value of byte 2 of the Serializer AN Value 155 0x9B TX_AN3 7:0 R 0x00 TX AN3 TX_AN3: Value of byte 3 of the Serializer AN Value 156 0x9C TX_AN4 7:0 R 0x00 TX AN4 TX_AN4: Value of byte 4 of the Serializer AN Value 157 0x9D TX_AN5 7:0 R 0x00 TX AN5 TX_AN5: Value of byte 5 of the Serializer AN Value 158 0x9E TX_AN6 7:0 R 0x00 TX AN6 TX_AN6: Value of byte 6 of the Serializer AN Value 0 Reserved 0 Reserved 0 46 7-bit Remote Slave Device Alias ID 6 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID6 register. A value of 0 in this field disables access to the remote I2C Slave. 7-bit Remote Slave Device Alias ID 7 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID7 register. A value of 0 in this field disables access to the remote I2C Slave. Reserved Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q ADD (dec) ADD (hex) Register Name Bit(s) Register Type Default (hex) 159 0x9F TX_AN7 7:0 R 0x00 160 0xA0 RX BCAPS 7 Function Description TX AN7 TX_AN7: Value of byte 7 of the Serializer AN Value 0x00 Reserved 6 R Repeater 5 R KSV FIFO KSV FIFO Ready Indicates the receiver has built the list of attached KSVs and computed the verification value 1 R Features HDCP v1.1_Features The HDCP Receiver supports the Enhanced Encryption Status Signaling (EESS), Advance Cipher, and Enhanced Link Verification options. 0 R Fast Reauth The HDCP Receiver is capable of receiving (unencrypted) video signal during the session reauthentication. 7 R Max Devices Maximum Devices Exceeded: Indicates a topology error was detected. Indicates the number of downstream devices has exceeded the depth of the Repeater's KSV FIFO 6:0 R Device Count Total number of attached downstream device. For a Repeater, this will indicate the number of downstream devices, not including the Repeater. For an HDCP Receiver that is not also a Repeater, this field will be 0 4:2 161 162 163 0xA1 0xA2 0xA3 RX BSTATUS0 RX BSTATUS1 KSV FIFO Indicates if the attached Receiver supports downstream connections. This bit is valid once the Bksv is ready as indicated by the BKSV_RDY bit in the HDCP Reserved 7:4 0x00 0x00 Reserved 3 R Max Cascade Maximum Cascade Exceeded: Indicates a topology error was detected — more than seven levels of repeaters have been cascaded together 2:0 R Cascade Depth Indicates the number of attached levels of devices for the Repeater 7:0 R Copyright © 1999-2012, Texas Instruments Incorporated 0x00 KSV FIFO KSV FIFO Each read of the KSV FIFO returns one byte of the KSV FIFO list composed by the downstream Receiver. 47 DS90UH927Q 48 ADD (dec) ADD (hex) Register Name 192 0xC0 HDCP DBG Bit(s) Register Type 7:4 Default (hex) Function 0x00 Description Reserved 3 RW RGB CHKSUM Enable RGB video line checksum Enables sending of ones-complement checksum for each 8-bit RGB data channel following end of each video data line 2 RW Fast LV Fast Link Verification HDCP periodically verifies that the HDCP Receiver is correctly synchronized. Setting this bit will increase the rate at which synchronization is verified. When set to a 1, Pj is computed every 2 frames and Ri is computed every 16 frames. When set to a 0, Pj is computed every 16 frames and Ri is computed every 128 frames. 1 RW TMR Timer Speedup Speed Up Speed up HDCP authentication timers. 0 RW HDCP I2C HDCP I2C Fast Mode Enable Fast Setting this bit to a 1 will enable the HDCP I2C Master in the HDCP Receiver to operate with Fast mode timing. If set to a 0, the I2C Master will operate with Standard mode timing. This bit is mirrored in the IND_STS register Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q ADD (dec) ADD (hex) Register Name 194 0xC2 HDCP CFG Bit(s) Register Type Default (hex) 7 RW 0x80 6 Function Description ENH LV Enable Enhanced Link Verification Allows checking of the encryption Pj value on every 16th frame 0: Enhanced Link Verification disabled 1: Enhanced Link Verification enabled (default) RW HDCP EESS Enables Enhanced Encryption Status Signaling (EESS) instead of the Original Encryption Status Signaling (OESS) 0: OESS mode enabled (default) 1: EESS mode enabled 5 RW TX RPTR Transmit Repeater Enable Enables the transmitter to act as a repeater. In this mode, the HDCP Transmitter incorporates the additional authentication steps required of an HDCP Repeater. 0: Transmit Repeater mode disabled (default) 1: Transmit Repeater mode enabled 4:3 RW ENC Mode Encryption Control Mode Determines mode for controlling whether encryption is required for video frames 00: Enc_Authenticated (default) 01: Enc_Reg_Control 10: Enc_Always 11: Enc_InBand_Control (per frame) If the Repeater strap option is set at power-up, Enc_InBand_Control (ENC_MODE == 11) will be selected. Otherwise, the default will be Enc_Authenticated mode (ENC_MODE == 00). 2 RW Wait Enable 100 ms Wait: The HDCP 1.3 specification allows for a 100 ms wait to allow the HDCP Receiver to compute the initial encryption values. The FPD-Link III implementation guarantees that the Receiver will complete the computations before the HDCP Transmitter. Thus the timer is unnecessary. 0: 100 ms timer disabled (default) 1: 100 ms timer enabled 1 RW RX DET SEL RX Detect Select: Controls assertion of the Receiver Detect Interrupt. 0: The Receiver Detect Interrupt will be asserted on detection of an FPD-Link III Receiver. (default) 1: the Receiver Detect Interrupt will also require a receive lock indication from the receiver. 0 RW HDCP AV Enable AVMUTE This bit may only be set if the MUTE HDCP_EESS bit is also set. 0: Resume normal operation (default) 1: Initiate AVMUTE operation. The transmitter will ignore encryption status controls while in this state. Copyright © 1999-2012, Texas Instruments Incorporated 49 DS90UH927Q ADD (dec) ADD (hex) Register Name 195 0xC3 HDCP CTL Bit(s) Register Type Default (hex) 7 RW 0x00 Function Description HDCP RST HDCP Reset Setting this bit will reset the HDCP transmitter and disable HDCP authentication. This bit is selfclearing. 6 50 Reserved 5 RW KSV List Valid The controller sets this bit after validating the Repeater’s KSV List against the Key revocation list. This allows completion of the Authentication process. This bit is self-clearing 4 RW KSV Valid The controller sets this bit after validating the Receiver’s KSV against the Key revocation list. This allows continuation of the Authentication process. This bit will be cleared upon assertion of the KSV_RDY flag in the HDCP_STS register. Setting this bit to a 0 will have no effect 3 RW HDCP ENC DIS HDCP Encrypt Disable Disables HDCP encryption. Setting this bit to a 1 will cause video data to be sent without encryption. Authentication status will be maintained. This bit is self-clearing 2 RW HDCP ENC EN HDCP Encrypt Enable Enables HDCP encryption. When set, if the device is authenticated, encrypted data will be sent. If device is not authenticated, a blue screen will be sent. Encryption should always be enabled when video data requiring content protection is being supplied to the transmitter. When this bit is not set, video data will be sent without encryption. Note that when CFG_ENC_MODE is set to Enc_Always, this bit will be read only with a value of 1 1 RW HDCP DIS HDCP Disable Disables HDCP authentication. Setting this bit to a 1 will disable the HDCP authentication. This bit is self-clearing 0 RW HDCP EN HDCP Enable/Restart Enables HDCP authentication. If HDCP is already enabled, setting this bit to a 1 will restart authentication. Setting this bit to a 0 will have no effect. A register read will return the current HDCP enabled status Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q ADD (dec) ADD (hex) Register Name 196 0xC4 HDCP STS Bit(s) Register Type Default (hex) 7 R 0x00 6 Function Description I2C ERR DET HDCP I2C Error Detected This bit indicates an error was detected on the embedded communications channel with the HDCP Receiver. Setting of this bit might indicate that a problem exists on the link between the HDCP Transmitter and HDCP Receiver. This bit will be cleared on read R RX INT RX Interrupt Status of the RX Interrupt signal. The signal is received from the attached HDCP Receiver and is the status on the INTB_IN pin of the HDCP Receiver. The signal is active low, a 0 indicates an interrupt condition 5 R RX Lock DET Receiver Lock Detect This bit indicates that the downstream Receiver has indicated Receive Lock to incoming serial data 4 R DOWN HPD Downstream Hot Plug Detect This bit indicates the local device or a downstream repeater has reported a Hot Plug event, indicating addition of a new receiver. This bit will be cleared on read 3 R RX DET Receiver Detect This bit indicates that a downstream Receiver has been detected 2 R KSV LIST HDCP Repeater KSV List Ready RDY This bit indicates that the Receiver KSV list has been read and is available in the KSV_FIFO registers. The device will wait for the controller to set the KSV_LIST_VALID bit in the HDCP_CTL register before continuing. This bit will be cleared once the controller sets the KSV_LIST_VALID bit. 1 R KSV RDY HDCP Receiver KSV Ready This bit indicates that the Receiver KSV has been read and is available in the HDCP_ BKSV registers. If the device is not a Repeater, it will wait for the controller to set the KSV_VALID bit in the HDCP_CTL register before continuing. This bit will be cleared once the controller sets the KSV_VALID bit.. The bit will also be cleared if authentication fails. 0 R AUTHED Copyright © 1999-2012, Texas Instruments Incorporated HDCP Authenticated Indicates the HDCP authentication has completed successfully. The controller may now send video data requiring content protection. This bit will be cleared if authentication is lost or if the controller restarts authentication 51 DS90UH927Q ADD (dec) ADD (hex) Register Name 198 0xC6 HDCP ICR 199 52 0xC7 HDCP ISR Bit(s) Register Type Default (hex) 7 RW 0x00 6 RW IE RXDET Interrupt on Receiver Detect INT Enables interrupt on detection of a downstream Receiver. If HDCP_CFG:RX_DET_SEL is set to a 1, the interrupt will wait for Receiver Lock Detect. 5 RW IS_RX_IN Interrupt on Receiver interrupt T Enables interrupt on indication from the HDCP Receiver. Allows propagation of interrupts from downstream devices 4 RW IE LIST RDY Interrupt on KSV List Ready Enables interrupt on KSV List Ready 3 RW IE KSV RDY Interrupt on KSV Ready Enables interrupt on KSV Ready 2 RW IE AUTH FAIL Interrupt on Authentication Failure Enables interrupt on authentication failure or loss of authentication 1 RW IE AUTH PASS Interrupt on Authentication Pass Enables interrupt on successful completion of authentication 0 RW INT Enable Global Interrupt Enable Enables interrupt on the interrupt signal to the controller. 7 R IS IND ACC Interrupt on Indirect Access Complete Indirect Register Access has completed 6 R INT Detect Interrupt on Receiver Detect interrupt A downstream receiver has been detected 5 R IS RX INT Interrupt on Receiver interrupt Receiver has indicated an interrupt request from downstream device 4 R IS LIST RDY Interrupt on KSV List Ready The KSV list is ready for reading by the controller 3 R IS KSV RDY Interrupt on KSV Ready The Receiver KSV is ready for reading by the controller 2 R IS AUTH FAIL Interrupt on Authentication Failure Authentication failure or loss of authentication has occurred 1 R IS AUTH PASS Interrupt on Authentication Pass Authentication has completed successfully 0 R INT Global Interrupt Set if any enabled interrupt is indicated 0x00 Function Description IE IND ACC Interrupt on Indirect Access Complete Enables interrupt on completion of Indirect Register Access Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q ADD (dec) ADD (hex) Register Name Bit(s) Register Type Default (hex) Function Description 208 0xD0 IND STS 7 RW 0x00 IA Reset Indirect Access Reset Setting this bit to a 1 will reset the I2C Master in the HDCP Receiver. As this may leave the I2C bus in an indeterminate state, it should only be done if the Indirect Access mechanism is not able to complete due to an error on the destination I2C bus. 6 Reserved 5 RW I2C TO DIS I2C Timeout Disable Setting this bit to a 1 will disable the bus timeout function in the I2C master. When enabled, the bus timeout function allows the I2C master to assume the bus is free if no signaling occurs for more than 1 second. 4 RW I2C Fast I2C Fast mode Enable Setting this bit to a 1 will enable the I2C Master in the HDCP Receiver to operation with Fast mode timing. If set to a 0 (default), the I2C Master will operate with Standard mode timing. 1 R IA ACK Indirect Access Acknowledge The acknowledge bit indicates that a valid acknowledge was received upon completion of the I2C read or write to the slave. A value of 0 (default) indicates the read/write did not complete successfully. 0 R IA DONE Indirect Access Done Set to a 1 to indicate completion of Indirect Register Access. This bit will be cleared or read or by start of a new Indirect Register Access. 7:1 RW 0 RW 3:2 209 0xD1 IND SAR Reserved 0x00 IA SADDR Indirect Access Slave Address This field should be programmed with the slave address for the I2C slave to be accessed IA RW Indirect Access Read/Write 0: Write (default) 1: Read 210 0xD2 IND OAR 7:0 RW 0x00 IA Offset Indirect Access Offset It is programmed with the register address for the I2C indirect access. 211 0xD3 IND DATA 7:0 RW 0x00 IA Data Indirect Access Data For an indirect write, It is written with the write data. For an indirect read, it contains the result of a successful read. 240 0xF0 HDCP TX ID 7:0 R 0x5F ID0 First byte ID code, ‘_’ 241 0xF1 7:0 R 0x55 ID1 Second byte of ID code, ‘U’ 242 0xF2 7:0 R 0x48 ID2 Third byte of ID code. ‘H' 243 0xF3 7:0 R 0x39 ID3 Forth byte of ID code: ‘9’ 244 0xF4 7:0 R 0x32 ID4 Fifth byte of ID code: “2” 245 0xF5 7:0 R 0x37 ID5 Sixth byte of ID code: “7” Copyright © 1999-2012, Texas Instruments Incorporated 53 DS90UH927Q Applications Information DISPLAY APPLICATION The DS90UH927Q, in conjunction with the DS90UH928Q or DS90UH926Q, is intended for interface between a HDCP compliant host (graphics processor) and a display supporting 24-bit color depth (RGB888) and high definition (720p) digital video format. It can receive an 8-bit RGB stream with a pixel clock rate up to 85 MHz together with three control bits (VS, HS and DE) and four I2S audio streams. The included HDCP 1.3 compliant cipher block allows the authentication of the HDCP Deserializer, which decrypts both video and audio contents. The HDCP keys are pre-loaded by TI into Non-Volatile Memory (NVM) for maximum security. TYPICAL APPLICATION CONNECTION Figure 27 shows a typical application of the DS90UH927Q serializer for an 85 MHz 24-bit Color Display Application. The 5 LVDS input pairs require external 100Ω terminations. The CML outputs must have an external 0.1µF AC coupling capacitor on the high speed serial lines. The serializer has internal CML termination on its high speed outputs. Bypass capacitors should be placed near the power supply pins. At a minimum, four (4) 4.7µF capacitors should be used for local device bypassing. Ferrite beads are placed on the two sets of supply pins (VDD33 and VDDIO) for effective noise suppression. The interface to the graphics source is LVDS. The VDDIO pins may be connected to 3.3V or 1.8V. A capacitor and resistor are placed on the PDB pin to delay the enabling of the device until power is stable. 30193044 FIGURE 27. Typical Connection Diagram 54 Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q POWER UP REQUIREMENTS AND PDB PIN The power supply ramp (VDD33 and VDDIO) should be faster than 1.5ms with a monotonic rise. A large capacitor on the PDB pin is needed to ensure PDB arrives after all the supply pins have settled to the recommended operating voltage. When PDB pin is pulled up to VDD33, a 10kΩ pull-up and a >10μF capacitor to GND are required to delay the PDB input signal rise. All inputs must not be driven until both VDD33 and VDDIO has reached steady state. Pins VDD33_A and VDD33_B should both be externally connected, bypassed, and driven to the same potential (they are not internally connected). PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the LVDS serializer and deserializer devices should be designed to provide low-noise power to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray noise, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mil) for power / ground sandwiches. This arrangement utilizes the plane capacitance for the PCB power system and has low-inductance, which has proven effectiveness especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01μF to 10μF. Tantalum capacitors may be in the 2.2μF to 10μF range. The voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used. MLCC surface mount capacitors are recommended due to their smaller parasitic properties. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommended at the point of power entry. This is typically in the 50μF to 100μF range and will smooth low frequency switching noise. It is recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path. A small body size X7R chip capacitor, such as 0603 or 0805, is recommended for external bypass. A small body sized capacitor has less inductance. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20MHz-30MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. For DS90UH927Q, only one common ground plane is required to connect all device related ground pins. Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100Ω are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise will appear as common mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less. At least 9 thermal vias are necessary from the device center DAP to the ground plane. They connect the device ground to the PCB ground plane, as well as conduct heat from the exposed pad of the package to the PCB ground plane. More information on the LLP style package, including PCB design and manufacturing requirements, is provided in TI Application Note: AN-1187. CML INTERCONNECT GUIDELINES See AN-1108 and AN-905 for full details. • Use 100Ω coupled differential pairs • Use the S/2S/3S rule in spacings – S = space between the pair – 2S = space between pairs – 3S = space to LVCMOS signal • Minimize the number of Vias • Use differential connectors when operating above 500Mbps line speed • Maintain balance of the traces • Minimize skew within the pair • Terminate as close to the TX outputs and RX inputs as possible Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas Instruments web site at: http://www.ti.com/lit/ml/snla187/snla187.pdf Copyright © 1999-2012, Texas Instruments Incorporated 55 DS90UH927Q Revision • 56 October 26, 2012 — Initial Release Copyright © 1999-2012, Texas Instruments Incorporated DS90UH927Q Physical Dimensions inches (millimeters) unless otherwise noted 40–pin LLP Package (6.0 mm X 6.0 mm X 0.8 mm, 0.5 mm pitch) TI Package Number SQA40A Copyright © 1999-2012, Texas Instruments Incorporated 57 Notes Copyright © 1999-2012, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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