Product Folder Sample & Buy Support & Community Tools & Software Technical Documents DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 DS90UB91xQ-Q1 10- to 100-MHz, 10- and 12-Bit DC-Balanced FPD-Link III Serializer and Deserializer With Bidirectional Control Channel 1 Features 2 Applications • • • • 1 • • • • • • • • • • • • • • 10-MHz to 100-MHz Input Pixel Clock Support Single Differential Pair Interconnect Programmable Data Payload: – 10-bit Payload up to 100 MHz – 12-bit Payload up to 75 MHz Continuous Low Latency Bidirectional Control Interface Channel With I2C Support at 400 kHz 2:1 Multiplexer to Choose Between Two Input Imagers Embedded Clock With DC-Balanced Coding to Support AC-Coupled Interconnects Capable of Driving up to 25 Meters Shielded Twisted-Pair Receive Equalizer Automatically Adapts for Changes in Cable Loss Four Dedicated General-Purpose Input/Output Pins (GPIO) Available on Both Serializer and Deserializer LOCK Output Reporting Pin and AT-SPEED BIST Diagnosis Feature to Validate Link Integrity 1.8-V, 2.8-V or 3.3-V Compatible Parallel Inputs on Serializer Single Power Supply at 1.8 V ISO 10605 and IEC 61000-4-2 ESD Compliant Automotive-Grade Product: AEC-Q100 Grade 2 Qualified Temperature Range −40°C to +105°C Small Serializer Footprint (5 mm × 5 mm) EMI/EMC Mitigation on Deserializer – Programmable Spread Spectrum (SSCG) Outputs – Receiver Staggered Outputs • Front- or Rear-View Camera for Collision Mitigation Surround View for Parking Assistance 3 Description The DS90UB91xQ-Q1 chipset offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB91xQ-Q1 chipsets incorporate differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer and deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This chipset is ideally suited for driving video data that requires up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus. There is a multiplexer at the deserializer to choose between two input imagers. The deserializer can have only one active input imager. The primary video transport converts 10- and 12-bit data over a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port and is independent of video blanking period. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DS90UB913Q-Q1 WQFN (32) 5.00 mm × 5.00 mm DS90UB914Q-Q1 WQFN (48) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit Parallel Data In 10 or 12 Parallel Data Out 10 or 12 FPD-Link III 2 Megapixel Imager/Sensor HSYNC, VSYNC 2 DS90UB913Q Bidirectional Control Channel 4 GPO 2 Bidirectional Control Bus DS90UB914Q Serializer HSYNC, VSYNC 4 DSP, FPGA/ µ-Processor/ ECU GPIO 2 Deserializer Bidirectional Control Bus 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description continued ........................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 9 8.1 8.2 8.3 8.4 8.5 8.6 Absolute Maximum Ratings ...................................... 9 ESD Ratings.............................................................. 9 Recommended Operating Conditions....................... 9 Thermal Information ................................................ 10 Electrical Characteristics ........................................ 10 Timing Requirements: Recommended for Serializer PCLK ....................................................................... 14 8.7 AC Timing Specifications (SCL, SDA) - I2C Compliant ................................................................. 15 8.8 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C Compliant..................................... 15 8.9 Switching Characteristics: Serializer ....................... 16 8.10 Switching Characteristics: Deserializer................. 17 8.11 Typical Characteristics .......................................... 19 9 Parameter Measurement Information ................ 20 9.1 AC Timing Diagrams and Test Circuits................... 20 10 Detailed Description ........................................... 25 10.1 10.2 10.3 10.4 10.5 Overview ............................................................... Functional Block Diagram ..................................... Feature Description............................................... Device Functional Modes...................................... Register Maps ....................................................... 25 25 26 33 41 11 Application and Implementation........................ 56 11.1 Applications Information........................................ 56 11.2 Typical Application ................................................ 56 12 Power Supply Recommendations ..................... 60 13 Layout................................................................... 60 13.1 Layout Guidelines ................................................. 60 13.2 Layout Example .................................................... 61 14 Device and Documentation Support ................. 63 14.1 14.2 14.3 14.4 14.5 14.6 Documentation Support ....................................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 63 63 63 63 63 63 15 Mechanical, Packaging, and Orderable Information ........................................................... 63 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (January 2014) to Revision D Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • Updated datasheet to new TI layout....................................................................................................................................... 1 • Added text and graphic to Power Up Requirements ........................................................................................................... 39 Changes from Revision B (April 2013) to Revision C Page • Changed "PCLK from imager mode" value in DS90UB913Q Serializer MODE Resistor Value table from 0 kΩ to 100 kΩ ......................................................................................................................................................................................... 35 • Changed Falling to Rising in RRFB...................................................................................................................................... 47 • Changed Rising to Falling in RRFB...................................................................................................................................... 47 Changes from Revision A (April 2013) to Revision B • 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 61 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 5 Description continued Using TI’s embedded-clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing paths, which reduces PCB layers, cable width, connector size and pins. In addition, the deserializer inputs provide adaptive equalization to compensate for loss from the media over longer distances. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. The Serializer is offered in a 32-pin WQFN package and the deserializer is offered in a 48-pin WQFN package. 6 Device Comparison Table PART NUMBER FPD-III FUNCTION PACKAGE TRANSMISSION MEDIA PCLK FREQUENCY DS90UB913Q-Q1 Serializer 32-Pin RTV (WQFN) STP 10 to 100 MHz DS90UB913A-Q1 Serializer 32-Pin RTV (WQFN) Coax or STP 25 to 100 MHz DS90UB914Q-Q1 Deserializer 48-Pin RHS (WQFN) STP 10 to 100 MHz DS90UB914A-Q1 Deserializer 48-Pin RHS (WQFN) Coax or STP 25 to 100 MHz Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 3 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com 7 Pin Configuration and Functions DIN[1] 21 20 16 GPO[1] DIN[6] 26 15 GPO[0] DIN[7] 27 14 VDDCML VDDD 28 13 DOUT+ DIN[8] 29 12 DOUT- DIN[9] 11 VDDT 10 VDDPLL 9 17 30 18 31 VDDIO 19 GPO[2]/ CLKOUT DIN[2] 22 GPO[3]/ CLKIN DIN[3] 23 DIN[0] DIN[4] 24 25 DIN[5] RTV Package 32-Pin WQFN Top View PDB DS90UB913Q Serializer 2 3 4 5 6 7 PCLK SCL SDA ID[x] RES 8 MODE 1 VSYNC DIN[11] HSYNC 32 DIN[10] DAP = GND DS90UB913Q-Q1 Serializer Pin Functions PIN NAME I/O NO. DESCRIPTION LVCMOS PARALLEL INTERFACE 19, 20, 21, 22, 23, 24, 26, 27, 29, 30, 31, 32 Inputs, LVCMOS with pulldown Parallel data inputs HSYNC 1 Inputs, LVCMOS with pulldown Horizontal SYNC input PCLK 3 Input, LVCMOS with pulldown VSYNC 2 Inputs, LVCMOS with pulldown DIN[0:11] 4 Submit Documentation Feedback Pixel clock input pin Strobe edge set by TRFB control register. Vertical SYNC input Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 DS90UB913Q-Q1 Serializer Pin Functions (continued) PIN NAME I/O DESCRIPTION Output, LVCMOS General-purpose output pins can be configured as outputs; used to control and respond to various commands. GPO[0:1] can be configured to be the outputs for input signals coming from GPIO[0:1] pins on the deserializer or can be configured to be outputs of the local register on the serializer. Output, LVCMOS GPO2 pin can be configured to be the output for input signal coming from the GPIO2 pin on the deserializer or can be configured to be the output of the local register on the serializer. It can also be configured to be the output clock pin when the DS90UB913QQ1 device is used in the External Oscillator mode. See Applications Information for a detailed description of the DS90UB91xQ-Q1 chipsets working with the external oscillator. Input/Output, LVCMOS GPO3 can be configured to be the output for input signals coming from the GPIO3 pin on the deserializer or can be configured to be the output of the local register setting on the serializer. It can also be configured to be the input clock pin when the DS90UB913Q-Q1 serializer is working with an external oscillator. See Applications Information section for a detailed description of the DS90UB91xQ-Q1 chipsets working with an external oscillator. NO. GENERAL-PURPOSE OUTPUT (GPO) GPO[1:0] GPO[2]/ CLKOUT GPO[3]/ CLKIN 16, 15 17 18 BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE SCL 4 Input/Output, Open-Drain Clock line for the bidirectional control bus communication SCL requires an external pullup resistor to VDDIO. SDA 5 Input/Output, Open-Drain Data line for the bidirectional control bus communication SDA requires an external pullup resistor to VDDIO. MODE 8 Input, LVCMOS with pulldown ID[x] 6 Input, analog Device mode select Resistor to Ground and 10-kΩ pullup to 1.8-V rail. MODE pin on the serializer can be used to select whether the system is running off the PCLK from the imager or an external oscillator. See details in Table 3. Device ID address select The ID[x] pin on the serializer is used to assign the I2C device address. Resistor to Ground and 10-kΩ pullup to 1.8-V rail. See Table 1. CONTROL AND CONFIGURATION PDB 9 Input, LVCMOS with pulldown RES 7 Input, LVCMOS with pulldown Power down Mode Input Pin PDB = H, serializer is enabled and is ON. PDB = L, Serailizer is in power-down mode. When the serializer is in power-down, the PLL is shutdown, and IDD is minimized. Programmed control register data are NOT retained and reset to default values Reserved This pin MUST be tied LOW. FPD-Link III INTERFACE DOUT+ 13 Input/Output, CML Noninverting differential output, bidirectional control channel input. The interconnect must be AC-coupled with a 100-nF capacitor. DOUT– 12 Input/Output, CML Inverting differential output, bidirectional control channel input. The interconnect must be AC-coupled with a 100-nF capacitor. POWER AND GROUND VDDPLL 10 Power, Analog PLL Power, 1.8 V ±5% VDDT 11 Power, Analog Tx Analog Power, 1.8 V ±5% VDDCML 14 Power, Analog CML and bidirectional channel driver power, 1.8 V ±5% VDDD 28 Power, Digital Digital power, 1.8 V ±5% VDDIO 25 Power, Digital Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO. VDDIO can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10% DAP Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 9 vias. VSS Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 5 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com MODE 37 CMLOUTP 38 VDDR IDx[0] IDx[1] RIN1- RIN1+ VDDCML1 PDB VDDIO1 GPIO[0] GPIO[1] GPIO[2] GPIO[3] 36 35 34 33 32 31 30 29 28 27 26 25 RHS Package 48-Pin WQFN Top View 24 DAP = GND ROUT[0] 23 ROUT[1] 39 22 ROUT[2] 40 21 ROUT[3] RIN0+ 41 20 VDDIO2 RIN0- 42 19 ROUT[4] 18 ROUT[5] CMLOUTN VDDCML0 DS90UB914Q Deserializer RES 43 RES 44 17 VDDD VDDPLL 45 16 ROUT[6] 12 ROUT[10] 9 VSYNC 11 8 PCLK 10 7 VDDIO3 HSYNC 6 ROUT[11] 5 OEN BISTEN ROUT[9] 4 13 OSS_SEL 48 3 LOCK VDDSSCG ROUT[8] 2 ROUT[7] 14 SCL 15 47 1 46 SDA SEL PASS DS90UB914Q-Q1 Deserializer Pin Functions PIN NAME I/O NO. DESCRIPTION LVCMOS PARALLEL INTERFACE 11, 12, 13, 14, 15, 16, 18, 19, 21, 22, 23, 24 Outputs, LVCMOS Parallel data outputs HSYNC 10 Output, LVCMOS Horizontal SYNC output PCLK 8 Output, LVCMOS Pixel clock output pin Strobe edge set by RRFB control register VSYNC 9 Output, LVCMOS Vertical SYNC output ROUT[11:0] GENERAL-PURPOSE INPUT/OUTPUT (GPIO) GPIO[1:0] GPIO[3:2] 6 27, 28 Digital Input/Output, LVCMOS General-purpose input/output pins can be used to control and respond to various commands. They may be configured to be the input signals for the corresponding GPOs on the serializer or they may be configured to be outputs to follow local register settings. 25, 26 Digital Input/Output LVCMOS General-purpose input/output pins GPO[2:3] can be configured to be input signals for GPOs on the serializer. In addition they can also be configured to be outputs to follow the local register settings. When the SerDes chipsets are working with an external oscillator, these pins can be configured only to be outputs to follow the local register settings. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 DS90UB914Q-Q1 Deserializer Pin Functions (continued) PIN NAME NO. I/O DESCRIPTION BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE SCL 2 Input/Output, Open-Drain Clock line for the bidirectional control bus communication SCL requires an external pullup resistor to VDDIO. SDA 1 Input/Output, Open-Drain Data line for bidirectional control bus communication SDA requires an external pullup resistor to VDDIO. MODE IDx[0:1] 37 35, 34 Device mode select pin Resistor-to-Ground and 10-kΩ pullup to 1.8-V rail. The MODE pin on the deserializer can be used to configure the serializer and deserializer to work in different input PCLK range. See details in Table 8. 12-bit low-frequency mode (10- to 50-MHz operation): In this mode, the serializer and deserializer can accept up to 12 bits DATA+2 SYNC. Input PCLK range is from 10 MHz to 50 MHz. Input, LVCMOS 12-bit high-frequency mode (15- to 75-MHz operation): In this mode, the with pullup serializer and deserializer can accept up to 12 bits DATA + 2 SYNC. Input PCLK range is from 15 MHz to 75 MHz. 10-bit mode (20- to 100-MHz operation): In this mode, the serializer and deserializer can accept up to 10 bits DATA + 2 SYNC. Input PCLK frequency can range from 20 MHz to 100 MHz. Refer to Table 4 in the Applications Information section on how to configure the MODE pin on the deserializer. Input, analog The IDx[0] and IDx[1] pins on the deserializer are used to assign the I2C device address. Resistor-to-Ground and 10-kΩ pullup to 1.8-V rail. See Table 2 Input pin to select the slave device address. Input is connect to external resistor divider to set programmable Device ID address. CONTROL AND CONFIGURATION Power-down mode input pin PDB = H, deserializer is enabled and is ON. Input, LVCMOS PDB = L, deserializer is in sleep (power-down mode). When the deserializer is in with pulldown sleep, programmed control register data are NOT retained and reset to default values. PDB 30 LOCK 48 Output, LVCMOS BISTEN 6 Input LVCMOS with pulldown PASS 47 Output, LVCOMS OEN 5 Input LVCMOS with pulldown Output enable input Refer to Table 5 OSS_SEL 4 Input LVCMOS with pulldown Output sleep state select pin Refer to Table 5 46 Input LVCMOS with pulldown MUX select line SEL = L, RIN0± input. This selects input A as the active channel on the deserializer. SEL = H, RIN1± input. This selects input B as the active channel on the deserializer. SEL Copyright © 2012–2015, Texas Instruments Incorporated LOCK status output pin LOCK = H, PLL is Locked, outputs are active LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by OSS_SEL control register. May be used as link status. BIST enable pin BISTEN=H, BIST mode enabled BISTEN=L, BIST mode is disabled PASS output pin for BIST mode. PASS = H, ERROR FREE transmission PASS = L, one or more errors were detected in the received payload. See Built-In Self Test section for more information. Leave open if unused. Route to test point (pad) recommended. Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 7 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com DS90UB914Q-Q1 Deserializer Pin Functions (continued) PIN NAME I/O NO. DESCRIPTION FPD-LINK III INTERFACE RIN0+ 41 Input/Output, CML Noninverting differential input, bidirectional control channel. The IO must be AC coupled with a 100-nF capacitor RIN0- 42 Input/Output, CML Inverting differential input, bidirectional control channel. The IO must be AC coupled with a 100-nF capacitor RIN1+ 32 Input/Output, CML Noninverting differential input, bidirectional control channel. The IO must be AC coupled with a 100-nF capacitor RIN1- 33 Input/Output, CML Inverting differential input, bidirectional control channel. The IO must be AC coupled with a 100-nF capacitor RES 43, 44 — Reserved; This pin must always be tied low. CMLOUTP/N 38, 39 — Route to test point or leave open if unused POWER AND GROUND VDDIO1/2/3 29, 20, 7 Power, Digital LVCMOS I/O buffer power, The single-ended outputs and control input are powered from VDDIO. VDDIO can be connected to a 1.8 V ±5% or 3.3 V ±10% VDDD 17 Power, Digital Digital core power, 1.8 V ±5% VDDSSCG 3 Power, Analog SSCG PLL power, 1.8 V ±5% VDDR 36 Power, Analog RX analog power, 1.8 V ±5% 40, 31 Power, Analog CML and bidirectional control channel drive power, 1.8 V±5% 45 Power, Analog PLL Power, 1.8 V ±5% DAP Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 16 vias. VDDCML0/1 VDDPLL VSS 8 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX UNIT Supply voltage – VDDn (1.8 V) −0.3 2.5 V Supply voltage – VDDIO −0.3 4.0 V LVCMOS input voltage −0.3 VDDIO + 0.3 V CML driver I/O voltage (VDD) −0.3 VDD + 0.3 V CML receiver I/O voltage (VDD) −0.3 VDD + 0.3 V 150 °C 1/θJA above +25° °C/W Junction temperature Maximum package power dissipation capacity package Air discharge (DOUT+, DOUT–, RIN+, RIN–) −25 25 kV Contact discharge (DOUT+, DOUT–, RIN+, RIN–) −7 7 kV Storage temperature Tstg −65 150 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications. For soldering specifications: see product folder at www.ti.com and SNOA549. 8.2 ESD Ratings VALUE Human body model (HBM), per AEC Q100-002 (1) ±8000 Charged-device model (CDM), per AEC Q100-011 ±1000 Machine model (MM) V(ESD) Electrostatic discharge IEC 61000-4-2 (2) ISO10605 (3) (4) (1) (2) (3) (4) UNIT ±250 ≥±25 000 Air Discharge (DOUT+, DOUT-, RIN+, RIN-) V ≥±7000 Contact Discharge (DOUT+, DOUT-, RIN+, RIN-) ≥±15 000 Air Discharge ≥±8000 Contact Discharge AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. RD = 330 Ω, CS = 150 pF RD = 330 Ω, CS = 150 / 330 pF RD = 2 KΩ, CS = 150 / 330 pF 8.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage (VDDn) 1.71 1.8 1.89 V LVCMOS supply voltage (VDDIO) OR 1.71 1.8 1.89 LVCMOS supply voltage (VDDIO) OR 3.0 3.3 3.6 2.52 2.8 3.08 LVCMOS supply voltage (VDDIO) only serializer Supply noise (1) VDDn (1.8 V) 25 VDDIO (1.8 V) 25 VDDIO (3.3 V) Operating free-air temperature (TA) (1) mVp-p 50 –40 PCLK clock frequency V 25 10 105 °C 100 MHz Supply noise testing was done with minimum capacitors (as shown on Figure 49 and Figure 48) on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8-V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency on the serializer is less than 1 MHz. The deserializer on the other hand shows no error when the noise frequency is less than 750 kHz. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 9 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com 8.4 Thermal Information THERMAL METRIC (1) DS90UB913Q-Q1 DS90UB914Q-Q1 RTV (WQFN) RHS (WQFN) 32 PINS 48 PINS UNIT RθJA Junction-to-ambient thermal resistance 38.4 26.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 6.9 4.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 8.5 Electrical Characteristics over recommended operating supply and temperature ranges unless otherwise specified. (1) PARAMETER TEST CONDITIONS MIN (2) (3) TYP MAX UNIT LVCMOS DC SPECIFICATIONS 3.3V I/O (SERIALIZER INPUTS, DESERIALIZER OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS) VIH High level input voltage VIN = 3 V to 3.6 V 2 VIN V VIL Low level input voltage VIN = 3 V to 3.6 V GND 0.8 V IIN Input current VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V 20 µA VOH High level output voltage VDDIO = 3 V to 3.6 V, IOH = −4 mA 2.4 VDDIO V VOL Low level output voltage VDDIO = 3 V to 3.6 V, IOL = +4 mA GND 0.4 V IOS Output short circuit current VOUT = 0 V TRI-STATE output current PDB = 0 V, VOUT = 0 V or VDD IOZ −20 ±1 Serializer GPO outputs –15 Deserializer LVCMOS outputs –35 LVCMOS outputs mA –20 20 µA LVCMOS DC SPECIFICATIONS 1.8V I/O (SERIALIZER INPUTS, DESERIALIZER OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS) VIH High level input voltage VIN = 1.71 V to 1.89 V 0.65 VIN VIN VIL Low level input voltage VIN = 1.71 V to 1.89 V GND 0.35 VIN IIN Input current VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V VOH High level output voltage VDDIO = 1.71 V to 1.89 V, IOH = −4 mA VOL Low level output voltage VDDIO = 1.71 V to 1.89 V IOL = 4 mA IOS Output short circuit current VOUT = 0 V TRI-STATE output current PDB = 0 V, VOUT = 0 V or VDD IOZ (1) (2) (3) 10 V Deserializer LVCMOS outputs –20 ±1 20 µA VDDIO – 0.45 VDDIO V GND 0.45 V Serializer GPO outputs –11 Deserializer LVCMOS outputs –17 LVCMOS outputs mA –20 20 µA The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at the time of product characterization and are not specified. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Electrical Characteristics (continued) over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVCMOS DC SPECIFICATIONS 2.8-V I/O (SERIALIZER INPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS) VIH High level input voltage VIN = 2.52 V to 3.08 V 0.7 VIN VIN VIL Low level input voltage VIN = 2.52 V to 3.08 V GND 0.3 VIN IIN Input current VIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V VOH High level output voltage VDDIO = 2.52 V to 3.08 V, IOH = −4 mA VOL Low level output voltage VDDIO =2.52 V to 3.08 V IOL = 4 mA IOS Output short circuit current VOUT = 0 V TRI-STATE output current PDB = 0 V, VOUT = 0 V or VDD IOZ V Deserializer LVCMOS outputs −20 ±1 20 µA VDDIO – 0.4 VDDIO V GND 0.4 V Serializer GPO outputs −11 Deserializer LVCMOS outputs −20 LVCMOS outputs mA −20 20 µA 340 412 mV 1 50 mV CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT–) |VOD| Output differential voltage RL = 100 Ω (see Figure 9) ΔVOD Output differential voltage unbalance RL = 100 Ω VOS Output differential offset voltage RL = 100 Ω (see Figure 9) ΔVOS Offset voltage unbalance RL = 100 Ω IOS Output short circuit current DOUT± = 0 V RT Differential internal termination resistance Differential across DOUT+ and DOUT– 268 VDD – VOD/2 1 V 50 –26 mV mA 80 100 120 Ω −20 1 20 µA 80 100 120 Ω CML RECEIVER DC SPECIFICATIONS (RIN0+, RIN0–, RIN1+, RIN1– ) IIN Input current VIN = VDD or 0 V, VDD = 1.89 V RT Differential internal termination resistance Differential across RIN+ and RIN- CML RECEIVER AC SPECIFICATIONS (RIN0+, RIN0–, RIN1+, RIN1– ) |Vswing| Minimum allowable swing for 1010 pattern (4) Line rate = 1.4 Gbps (see Figure 11) 135 mV CML MONITOR OUTPUT DRIVER SPECIFICATIONS (CMLOUTP, CMLOUTN) Ew Differential output eye opening EH Differential output eye height (4) RL = 100 Ω Jitter frequency > f / 40 (see Figure 20) 0.45 UI 200 mV Specification is ensured by characterization and is not tested in production. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 11 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Electrical Characteristics (continued) over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3) PARAMETER TEST CONDITIONS MIN TYP MAX VDDn = 1.89 V VDDIO = 3.6 V f = 100 MHz, 10-bit mode default registers 61 80 VDDn = 1.89 V VDDIO = 3.6 V f = 75 MHz, 12-bit high-frequency mode default registers 61 80 VDDn = 1.89 V VDDIO = 3.6 V f = 50 MHz, 12-bit low-frequency mode default registers 61 VDDn = 1.89 V VDDIO = 3.6 V f = 100 MHz, 10-bit mode default registers 54 VDDn = 1.89 V VDDIO = 3.6 V f = 75 MHz, 12-bit high-frequency mode default registers 54 VDD = 1.89 V VDDIO = 3.6 V f = 50 MHz, 12-bit low-frequency mode default registers 54 VDDIO = 1.89 V f = 75 MHz, 12-bit high-freq mode default registers 1.5 UNIT SERIALIZER AND DESERIALIZER SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD RL = 100 Ω WORST CASE pattern (see Figure 6) IDDT Serializer (TX) VDDn supply current (includes load current) RL = 100 Ω RANDOM PRBS-7 pattern IDDIOT IDDTZ IDDIOTZ 12 Serializer (TX) VDDIO supply current (includes load current) RL = 100 Ω WORST CASE pattern (see Figure 6) Serializer (TX) supply current power-down PDB = 0 V; all other LVCMOS inputs = 0 V Serializer (TX) VDDIO supply current power-down PDB = 0 V; All other LVCMOS Inputs = 0 V Submit Documentation Feedback mA mA 80 mA 3 mA VDDIO = 3.6 V f = 75 MHz, 12-bit high-frequency mode default registers 5 8 VDDIO = 1.89 V Default registers 300 900 µA VDDIO = 3.6 V Default registers 300 900 µA VDDIO = 1.89 V Default registers 15 100 µA VDDIO = 3.6 V Default registers 15 100 µA Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Electrical Characteristics (continued) over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3) PARAMETER TEST CONDITIONS VDDIO = 1.89 V CL = 8 pF WORST CASE pattern VDDIO = 1.89 V CL=8pF Random pattern VDDIO = 3.6 V CL = 8 pF WORST CASE pattern VDDIO = 3.6 V CL = 8 pF Random pattern IDDIOR Deserializer (RX) total supply current (includes load current) VDDIO = 1.89 V CL = 4 pF WORST CASE pattern VDDIO = 1.89 V CL = 4 pF Random pattern VDDIO = 3.6 V CL = 4 pF WORST CASE pattern VDDIO = 3.6 V CL = 4 pF Random pattern Copyright © 2012–2015, Texas Instruments Incorporated MIN TYP MAX f = 100 MHz, 10-bit mode 22 42 f = 75 MHz, 12-bit highfreq mode 19 39 f = 50 MHz, 12-bit lowfreq mode 21 32 f = 100 MHz, 10–bit mode 15 f = 75 MHz, 12-bit highfreq mode 12 f = 50 MHz, 12-bit lowfreq mode 14 f = 100 MHz, 10-bit mode 42 55 f = 75 MHz, 12-bit highfreq mode 37 50 f = 50 MHz, 12-bit lowfreq mode 25 38 f = 100 MHz, 10-bit mode 35 f = 75 MHz, 12-bit highfreq mode 30 f = 50 MHz, 12-bit lowfreq mode 18 f = 100 MHz, 10-bit mode 15 f = 75 MHz, 12-bit highfreq mode 11 f = 50 MHz, 12-bit lowfreq mode 16 f = 100 MHz, 10-bit mode 8 f = 75 MHz, 12-bit highfreq mode 4 f = 50 MHz, 12-bit lowfreq mode 9 f = 100 MHz, 10-bit mode 36 f = 75 MHz, 12-bit highfreq mode 29 f = 50 MHz, 12-bit lowfreq mode 20 f = 100 MHz, 10-bit mode 29 f = 75 MHz, 12-bit highfreq mode 22 f = 50 MHz, 12-bit lowfreq mode 13 UNIT mA mA mA mA mA mA mA mA Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 13 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Electrical Characteristics (continued) over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3) PARAMETER TEST CONDITIONS TYP MAX f = 100 MHz, 10-bit mode 64 110 f = 75 MHz, 12-bit high-frequency mode 67 114 f = 50 MHz, 12-bit low-frequency mode 63 96 f = 100 MHz, 10-bit mode 57 f = 75 MHz, 12–bit high-frequency mode 60 f = 50 MHz, 12-bit low-frequency mode 56 PBB = 0 V, all other LVCMOS Inputs=0 V VDDIO = 1.89 V Default registers 42 400 PBB = 0 V, all other LVCMOS Inputs=0 V VDDIO = 3.6 V Default registers 42 400 VDDn = 1.89 V CL = 4 pF WORST CASE pattern IDDR Deserializer (RX) VDDn supply current (includes load current) VDDn = 1.89 V CL = 4 pF Random pattern IDDRZ IDDIORZ Deserializer (RX) supply current power-down Deserializer (RX) VDD supply current power-down PDB = 0 V, all other LVCMOS Inputs = 0 V MIN UNIT mA µA VDDIO = 1.89 V 8 40 360 800 MIN NOM MAX 10 T 50 13.33 T 66.66 20 T 100 VDDIO = 3.6 V µA 8.6 Timing Requirements: Recommended for Serializer PCLK over recommended operating supply and temperature ranges unless otherwise specified. (1) TEST CONDITIONS PIN/FREQ 10-bit mode tTCP Transmit clock period 12-bit high-frequency mode 12-bit low-frequency mode UNIT ns tTCIH Transmit clock input high time 0.4T 0.5T 0.6T ns tTCIL Transmit clock input low time 0.4T 0.5T 0.6T ns 20 MHz–100 MHz, 10-bit mode 0.5T 2.5T 0.3T 15 MHz to 75 MHz, 12-bit high-frequency mode 0.5T 2.5T 0.3T 10 MHz to 50 MHz, 12-bit low-frequency mode 0.5T 2.5T 0.3T tCLKT PCLK input transition time (Figure 12) ns tJIT0 PCLK input jitter (PCLK from imager mode) Refer to jitter freq > f / 40 f = 10 to 100 MHz 0.1T ns tJIT1 PCLK input jitter (external Refer to jitter freq > f / 40 oscillator mode) f = 10 to 100 MHz 1T ns tJIT2 External oscillator jitter 0.1 UI (1) 14 Recommended input timing requirements are input specifications and not tested in production. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 AC Timing Specifications (SCL, SDA) - I2C Compliant 8.7 over recommended supply and temperature ranges unless otherwise specified. (See Figure 5) TEST CONDITIONS MIN NOM MAX UNIT RECOMMENDED INPUT TIMING REQUIREMENTS Standard mode >0 100 Fast mode >0 400 Standard mode 4.7 Fast mode 1.3 Standard mode 4.0 Fast mode 0.6 fSCL SCL clock frequency tLOW SCL low period tHIGH SCL high period tHD:STA Hold time for a start or a repeated start condition Standard mode Fast mode 0.6 tSU:STA Setup time for a start or a repeated start condition Standard mode 4.7 Fast mode 0.6 tHD:DAT Data hold time tSU:DAT Data setup time tSU:STO Setup time for STOP condition Standard mode Fast mode 0.6 tBUF Bus free time between stop and start Standard mode 4.7 Fast mode 1.3 tr SCL and SDA rise time tf SCL and SDA fall time kHz µs µs 4 µs µs Standard mode 0 3.45 Fast mode 0 900 Standard mode 250 Fast mode 100 µs ns 4 µs µs Standard mode 1000 Fast mode 300 Standard mode 300 Fast mode 300 ns ns Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C Compliant 8.8 over recommended supply and temperature ranges unless otherwise specified (1) TEST CONDITIONS MIN NOM MAX UNIT VDDIO V RECOMMENDED INPUT TIMING REQUIREMENTS VIH Input high level SDA and SCL 0.7 × VDDIO VIL Input low level SDA and SCL GND VHY Input hysteresis VOL Output low level SDA, IOL = 0.5 mA IIN Input current SDA or SCL, VIN = VDDOP OR GND tR SDA rise time-READ ns SDA fall time-READ SDA, RPU = 10 kΩ, Cb ≤ 400 pF (see Figure 5) 430 tF 20 ns tSU;DAT See Figure 5 560 ns tHD;DAT See Figure 5 615 ns 0.3 × VDDIO >50 0 0.4 V −10 10 µA tSP CIN (1) V mV SDA or SCL 50 ns <5 pF Specification is ensured by design. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 15 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com 8.9 Switching Characteristics: Serializer over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tLHT CML low-to-high transition RL = 100 Ω (see Figure 7) time 150 330 ps tHLT CML high-to-low transition RL = 100 Ω (see Figure 7) time 150 330 ps tDIS Data input setup to PCLK tDIH Data input hold from PCLK Serializer data inputs (see Figure 13) tPLD Serializer PLL lock time RL = 100 Ω (1) tSD Serializer delay (2) 2 ns 2 ns (2) , (see Figure 14) RT = 100 Ω, 10-bit mode Register 0x03h b[0] (TRFB = 1) (see Figure 15) 32.5T RT = 100 Ω, 12-bit mode Register 0x03h b[0] (TRFB = 1) (see Figure 15) 11.75T 1 2 38T 44T ms ns 13T 15T tJIND Serializer output deterministic jitter Serializer output intrinsic deterministic jitter. Measured (cycle-cycle) with PRBS-7 test pattern (3) (4) 0.13 UI tJINR Serializer output random jitter Serializer output intrinsic random jitter (cyclecycle). Alternating-1,0 pattern. (3) (4) 0.04 UI tJINT Peak-to-peak serializer output jitter Serializer output peak-to-peak jitter includes deterministic jitter, random jitter, and jitter transfer from serializer input. Measured (cycle-cycle) with PRBS-7 test pattern. (3) (4) 0.396 UI λSTXBW δSTX δSTXf (1) (2) (3) (4) (5) 16 Serializer jitter transfer function –3-dB bandwidth (5) Serializer jitter transfer function (peaking) (5) Serializer jitter transfer function (peaking frequency) (5) PCLK = 100 MHz 10-bit mode. Default registers 2.2 PCLK = 75 MHz 12-bit high-frequency mode. Default registers 2.2 PCLK = 50 MHz 12-bit low-frequency mode. Default registers 2.2 PCLK = 100 MHz 10-bit mode. Default Registers 1.06 PCLK = 75 MHz 12-bit high-frequency mode. Default registers 1.09 PCLK = 50 MHz 12-bit low-frequency mode. Default registers 1.16 PCLK = 100 MHz 10-bit mode. Default registers 400 PCLK = 75 MHz 12-bit high-frequency mode. Default registers 500 PCLK = 50 MHz 12-bit low-frequency mode. Default registers 600 MHz dB kHz tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK Specification is ensured by design. Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the recommended operation conditions at the time of product characterization and are not specified. UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency. Specification is ensured by characterization and is not tested in production. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 8.10 Switching Characteristics: Deserializer over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER TEST CONDITIONS PIN/FREQ 10-bit mode Receiver output clock period tRCP 12-bit high-frequency mode PCLK (see Figure 19) 12-bit low-frequency mode 10-bit mode tPDC PCLK duty cycle 12-bit high-frequency mode PCLK 12-bit low-frequency mode tCLH LVCMOS low-to-high transition time tCHL LVCMOS high-to-low transition time tCLH LVCMOS low-to-high transition time tCHL LVCMOS high-to-low transition time tROS ROUT setup data to PCLK tROH ROUT hold data to PCLK tDD Deserializer delay tDDLT tRCJ tDPJ (1) (2) Deserializer data lock time Receiver clock jitter Deserializer period jitter VDDIO: 1.71 V to 1.89 V or 3.0 V to 3.6 V, CL = 8 pF (lumped load) PCLK Default registers (see Figure 17) (1) VDDIO: 1.71 V to 1.89 V or 3.0 V to 3.6 V, ROUT[11:0], HS, CL = 8 pF (lumped load) VS Default registers (1) (see Figure 17) VDDIO: 1.71 V to 1.89 V or 3.0 V to 3.6 V, ROUT[11:0], HS, CL = 8 pF (lumped load) VS Default registers (see Figure 19) Default registers Register 0x03h b[0] (RRFB = 1) (see Figure 18) (1) With Adaptive Equalization (see Figure 16) PCLK SSCG[3:0] = OFF (1) PCLK SSCG[3:0] = OFF (1) (2) MIN TYP MAX 10 50 13.33 66.66 10 100 UNIT ns 45% 50% 55% 40% 50% 60% 40% 50% 60% 1.3 2 2.8 ns 1.3 2 2.8 ns 1 2.5 4 ns 1 2.5 4 ns 0.38T 0.5T ns 0.38T 0.5T ns 10-bit mode 154T 158T 12-bit lowfrequency mode 109T 112T 12-bit highfrequency mode 73T 75T 10-bit mode 15 22 12-bit lowfrequency mode 15 22 12-bit highfrequency mode 15 22 10-bit mode PCLK = 100 MHz 20 30 12-bit lowfrequency mode PCLK = 50 MHz 22 35 12-bit highfrequency mode PCLK = 75 MHz 45 90 10-bit mode PCLK = 100 MHz 170 815 12-bit lowfrequency mode PCLK= 50 MHz 180 330 12-bit highfrequency mode PCLK= 75 MHz 300 515 ns ms ps ps Specification is ensured by characterization and is not tested in production. tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 17 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Switching Characteristics: Deserializer (continued) over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER tDCCJ fdev fmod (3) 18 Deserializer cycle-tocycle clock jitter TEST CONDITIONS PCLK SSCG[3:0] = OFF (1) Spread spectrum clocking LVCMOS output bus deviation frequency SSC[3:0] = ON (see Spread spectrum clocking Figure 24) (1) modulation frequency (3) PIN/FREQ MIN TYP MAX 10-bit mode PCLK = 100 MHz 440 1760 12-bit lowfrequency mode PCLK = 50 MHz 460 730 12-bit highfrequency mode PCLK = 75 MHz 565 985 10 MHz–100 MHz ±0.5 to ±1.5% 10 MHz–100 MHz 5 to 50 UNIT ps kHz tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 8.11 Typical Characteristics 4 0.65 2 JITTER AMPLITUDE (UI) JITTER TRANSFER (dB) 0 -2 -4 -6 -8 -10 -12 -14 0.60 0.55 0.50 - 16 - 18 1.0E+04 1.0E+05 1.0E+06 0.45 1E+04 1.0E+07 1E+05 1E+06 1E+07 MODULATION FREQUENCY ( Hz) JITTER FREQUENCY (Hz) Figure 1. Typical Serializer Jitter Transfer Function at 100 MHz Figure 2. Typical Deserializer Input Jitter Tolerance Curve at 1.4-Gbps Line Rate 18 25 16 EFFECTIVE GAIN (dB) EQUALIZER GAIN (dB) 20 14 12 10 8 6 15 914 Equalizer Gain (dB) VOD-Vswing Loss 10 Allowable Interconnect Loss 5 4 0 100 2 0 100 200 300 400 500 600 700 SERIAL LINE FREQUENCY (MHz) 200 300 400 500 600 700 SERIAL LINE FREQUENCY (MHz) Figure 3. Maximum Equalizer Gain vs. Line Frequency Copyright © 2012–2015, Texas Instruments Incorporated Figure 4. Adaptive Equalizer – Interconnect Loss Compensation Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 19 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com 9 Parameter Measurement Information 9.1 AC Timing Diagrams and Test Circuits SDA tf tHD;STA tLOW tr tBUF tr tf SCL tSU;STA tHD;STA tHIGH tSU;STO tSU;DAT tHD;DAT START STOP REPEATED START START Figure 5. Bidirectional Control Bus Timing Signal Pattern Device Pin Name T PCLK (RFB = H) DIN/ROUT Figure 6. Worst Case Test Pattern 80% Vdiff 80% 20% Vdiff = 0V 20% tLHT tHLT Vdiff = (DOUT+) - (DOUT-) Figure 7. Serializer CML Output Load and Transition Times DOUT+ 100 nF 50: ZDiff = 100: SCOPE BW 8 4.0 GHz 100: 50: DOUT- 100 nF 10/12, HS,VS DIN PARALLEL-TO-SERIAL Figure 8. Serializer CML Output Load and Transition Times DOUT+ RL DOUT- PCLK Figure 9. Serializer VOD Diagram 20 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 AC Timing Diagrams and Test Circuits (continued) Single Ended | VOS DOUTV V OD V OD+ OD- DOUT+ Differential V OD+ 0V (DOUT+)-(DOUT-) V OD- Figure 10. Serializer VOD Diagram RIN- Single Ended Vswing- Vswing+ RIN+ 0V Differential Vswing+ (RIN+)-(RIN-) 0V Vswing- Figure 11. Differential Vswing Diagram 80% VDD 80% tTCP PCLK 20% 20% tCLKT 0V PCLK VDDIO/2 VDDIO/2 VDDIO/2 tCLKT tDIS tDIH VDDIO DINn VDDIO/2 Setup Hold VDDIO/2 0V Figure 12. Serializer Input Clock Transition Times PDB Figure 13. Serializer Set-Up and Hold Times VDDIO/2 PCLK tPLD DOUT± TRI-STATE Output Active TRI-STATE Figure 14. Serializer PLL Lock Time Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 21 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com SYMBOL N+2 | | SYMBOL N+1 | | SYMBOL N | | DIN | | AC Timing Diagrams and Test Circuits (continued) SYMBOL N+3 tSD VDDIO/2 SYMBOL N-3 SYMBOL N-2 SYMBOL N-1 | | | | | | DOUT+- SYMBOL N | | SYMBOL N-4 | | | | | | PCLK 0V Figure 15. Serializer Delay PDB VDDIO/2 | | tDDLT RIN± LOCK TRI-STATE | VDDIO/2 Figure 16. Deserializer Data Lock Time 80% 80% Deserializer 20% 8 pF lumped 20% tCLH tCHL SYMBOL N + 3 | | 0V SYMBOL N + 3 | | SYMBOL N + 2 | | RIN± SYMBOL N + 1 | | SYMBOL N | | Figure 17. Deserializer LVCMOS Output Load and Transition Times tDD PCLK SYMBOL N - 1 | || SYMBOL N - 2 | || SYMBOL N - 3 | || | || | || ROUTn VDDIO/2 SYMBOL N SYMBOL N+1 Figure 18. Deserializer Delay tRCP PCLK VDDIO 1/2 VDDIO 1/2 VDDIO 0V VDDIO ROUT[n], VS, HS 1/2 VDDIO 1/2 VDDIO 0V tROS tROH Figure 19. Deserializer Output Set-Up and Hold Times 22 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 AC Timing Diagrams and Test Circuits (continued) Ew VOD (+) EH 0V EH VOD (-) tBIT (1 UI) Figure 20. CML Output Driver PDB= H OEN VIH VIL VIH OSS_SEL VIL RIN (Diff.) 'RQ¶W&DUH tSEH tONS LOCK tSES TRI-STATE TRI-STATE PASS LOW tONH ACTIVE HIGH ROUT[0:11], HS, VS TRI-STATE LOW PCLK (RFB = L) TRI-STATE LOW TRI-STATE LOW HIGH HIGH ACTIVE ACTIVE LOW TRI-STATE LOW TRI-STATE Figure 21. Output State (Set-Up and Hold) Times Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 23 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com AC Timing Diagrams and Test Circuits (continued) 4 0.65 2 JITTER AMPLITUDE (UI) JITTER TRANSFER (dB) 0 -2 -4 -6 -8 -10 -12 0.60 0.55 0.50 -14 - 16 - 18 1.0E+04 1.0E+05 1.0E+06 0.45 1E+04 1.0E+07 1E+05 1E+06 1E+07 JITTER FREQUENCY (Hz) MODULATION FREQUENCY ( Hz) Figure 22. Typical Serializer Jitter Transfer Function at 100 MHz Figure 23. Typical Deserializer Input Jitter Tolerance Curve at 1.4-Gbps Line Rate Frequency fdev (max) FPCLK+ fdev FPCLK fdev (min) FPCLK- Time 1 / fmod Figure 24. Spread Spectrum Clock Output Profile 24 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 10 Detailed Description 10.1 Overview The DS90UB91xQ-Q1 FPD-Link III chipsets are intended to link megapixel camera imagers and video processors in ECUs. The serializer and deserializer chipset can operate from 10-MHz to 100-MHz pixel clock frequency. The DS90UB913Q-Q1 device transforms a 10- and 12-bit wide parallel LVCMOS data bus along with a bidirectional control channel control bus into a single high-speed differential pair. The high-speed serial bit stream contains an embedded clock and DC-balanced information which enhances signal quality to support AC coupling. The DS90UB914Q-Q1 device receives the single serial data stream and converts it back into a 10- and 12-bit wide parallel data bus together with the control channel data bus. The DS90UB91xQ-Q1 chipsets can accept up to: • 12 bits of DATA+2 bits SYNC for an input PCLK range of 10 MHz-50 MHz in the 12-bit low-frequency mode • 12 bits DATA + 2 SYNC bits for an input PCLK range of 15 MHz to 75 MHz in the 12-bit high-frequency mode • 10 bits DATA + 2 SYNC bits for an input PCLK range of 20 MHz to 100 MHz in the 10-bit mode. The DS90UB914Q-Q1 chipset has a 2:1 multiplexer that allows customers to select between two serializer inputs. The control channel function of the DS90UB91xQ-Q1 chipset provides bidirectional communication between the image sensor and ECUs. The integrated bidirectional control channel transfers data bidirectionally over the same differential pair used for video data interface. This interface offers advantages over other chipsets by eliminating the need for additional wires for programming and control. The bidirectional control channel bus is controlled through an I2C port. The bidirectional control channel offers asymmetrical communication and is not dependent on video blanking intervals. The DS90UB91xQ-Q1 chipset offer customers the choice to work with different clocking schemes. The DS90UB91xQ-Q1 chipsets can use an external oscillator as the reference clock source for the PLL or PCLK from the imager as primary reference clock to the PLL. 10.2 Functional Block Diagram RIN0+ RT RT DOUTPCLK PLL RIN0- 2:1 GPO[3:0] Output Latch DOUT+ Decoder RT Deserializer RT Adaptive Eq. Serializer 4 Encoder DIN HSYNC VSYNC Input Latch 10 or 12 10 or 12 ROUT HSYNC VSYNC 4 GPIO[3:0] RIN1+ Clock Gen PCLK LOCK Clock Gen CDR PASS RIN1- Encoder Encoder ID[x] MODE SEL Decoder SCL FIFO SDA I2C Controller OEN MODE DS90UB913Q - SERIALIZER Copyright © 2012–2015, Texas Instruments Incorporated I2C Controller Timing and Control PDB BISTEN FIFO Timing and Control Decoder PDB SDA SCL IDx[0] IDx[1] DS90UB914Q - DESERIALIZER Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 25 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com 10.3 Feature Description 10.3.1 Serial Frame Format The high-speed forward channel is composed of 28 bits of data containing video data, sync signals, I2C and parity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized, balanced and scrambled. The 28-bit frame structure changes in the 12-bit low-frequency mode, 12-bit high frequency mode and the 10-bit mode internally and is seamless to the customer. The bidirectional control channel data is transferred over the single serial link along with the high-speed forward data. This architecture provides a full duplex low-speed forward and backward path across the serial link together with a high-speed forward channel without the dependence on the video blanking phase. 10.3.2 Line Rate Calculations for the DS90UB91xQ The DS90UB913Q-Q1 device divides the clock internally by divide-by-1 in the 12-bit low-frequency mode, by divide-by-2 in the 10-bit mode and by divide-by-1.5 in the 12-bit high-frequency mode. Conversely, the DS90UB914Q-Q1 multiplies the recovered serial clock to generate the proper pixel clock output frequency. Thus the maximum line rate in the three different modes remains 1.4 Gbps. The following are the formulae used to calculate the maximum line rate in the different modes. • For 12-bit low-frequency mode, Line rate = fPCLK × 28; that is, fPCLK= 50 MHz, line rate = 50 × 28 = 1.4 Gbps • For 10-bit mode, Line rate = fPCLK / 2 × 28; that is, fPCLK= 100 MHz, line rate = (100 / 2) × 28 = 1.4 Gbps • For the 12-bit high-frequency mode, Line rate = fPCLK × (2 / 3) × 28; that is, fPCLK= 75 MHz, line rate = (75) × (2 / 3) × 28 = 1.4 Gbps 10.3.3 Deserializer Multiplexer Input The DS90UB914Q-Q1 offers a 2:1 multiplexer that can be used to select which camera is used as the input. Figure 25 shows the operation of the 2:1 multiplexer in the deserializer. The selection of the camera can be pin controlled as well as register controlled. Both the deserializer inputs cannot be enabled at the same time. If the Serializer A is selected as the active serializer, the back-channel for Deserializer A turns ON and vice versa. To switch between the two cameras, first the Serializer B has to be selected using the SEL pin/register on the deserializer. After that the back channel driver for Deserializer B has to be enabled using the register in the deserializer. Serializer A DS90UB913Q Camera A DATA PCLK DATA PCLK 2 I C Serializer B DS90UB913Q Camera B GPIO GPIO FSYNC CMOS Image Sensor DS90UB914Q 2:1 CMOS Image Sensor FSYNC 2 I C Deserializer A ECU Module DATA PCLK GPIO FSYNC 2 I C PC Serializer B Figure 25. Using the Multiplexer on the Deserializer to Enable a Two-Camera System 26 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Feature Description (continued) 10.3.4 Error Detection The chipset provides error detection operations for validating data integrity in long distance transmission and reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data transmission error checking. The error detection operating modes support data validation of the following signals: • Bidirectional control channel data across the serial link • Parallel video/sync data across the serial link The chipset provides one parity bit on the forward channel and 4 CRC bits on the back channel for error detection purposes. The DS90UB91xQ-Q1 chipset checks the forward and back channel serial links for errors and stores the number of detected errors in two 8-bit registers in the serializer and the deserializer respectively. To check parity errors on the forward-channel, monitor registers 0x1A and 0x1B on the deserializer. If there is a loss of LOCK, then the counters on registers 0x1A and 0x1B are reset. NOTE Whenever there is a parity error on the forward channel, the PASS pin will go low. To check CRC errors on the back-channel, monitor registers 0x0A and 0x0B on the serializer. 10.3.5 Description of Bidirectional Control Bus and I2C Modes SDA Line Register Address Slave Address 7-bit Address S Stop Bus Activity: Master Start The I2C-compatible interface allows programming of the DS90UB913Q-Q1, DS90UB914Q-Q1, or an external remote device (such as image sensor) through the bidirectional control channel. Register programming transactions to/from the DS90UB913xQ-Q1 chipset are employed through the clock (SCL) and data (SDA) lines. These two signals have open-drain I/Os and both lines must be pulled up to VDDIO by an external resistor. Pullup resistors or current sources are required on the SCL and SDA busses to pull them high when they are not being driven low. A logic LOW is transmitted by driving the output low. Logic HIGH is transmitted by releasing the output and allowing it to be pulled up externally. The appropriate pullup resistor values will depend upon the total bus capacitance and operating speed. The DS90UB91xQ-Q1 I2C bus data rate supports up to 400 kbps according to I2C fast mode specifications. Data P 0 A C K A C K A C K Bus Activity: Slave S Register Address Slave Address 7-bit Address S 0 A C K Bus Activity: Slave N A C K Slave Address 7-bit Address A C K Stop SDA Line Start Bus Activity: Master Start Figure 26. Write Byte P 1 A C K Data Figure 27. Read Byte Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 27 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Feature Description (continued) SDA 1 2 6 MSB R/W Direction Bit Acknowledge from the Device 7-bit Slave Address SCL ACK LSB MSB 7 8 9 LSB N/ACK Data Byte *Acknowledge or Not-ACK 1 8 2 Repeated for the Lower Data Byte and Additional Data Transfers START 9 STOP Figure 28. Basic Operation SDA SCL S P STOP condition START condition, or START repeat condition Figure 29. Start and Stop Conditions 10.3.6 Slave Clock Stretching The I2C-compatible interface allows programming of the DS90UB913Q-Q1, DS90UB914Q-Q1, or an external remote device (such as image sensor) through the bidirectional control. NOTE To communicate and synchronize with remote devices on the I2C bus through the bidirectional control channel/MCU, the chipset utilizes bus clock stretching (holding the SCL line low) during data transmission where the I2C slave pulls the SCL line low on the 9th clock of every I2C transfer (before the ACK signal). The slave device will not control the clock and only stretches it until the remote peripheral has responded. The I2C master must support clock stretching to operate with the DS90UB91xQ-Q1 chipset. 10.3.7 I2C Pass-Through I2C pass-through provides an alternative means to independently address slave devices. The mode enables or disables I2C bidirectional control channel communication to the remote I2C bus. This option is used to determine whether or not an I2C instruction is to be transferred over to the remote I2C device. When enabled, the I2C bus traffic will continue to pass through, I2C commands will be excluded to the remote I2C device. The pass-through function also provides access and communication to only specific devices on the remote bus. See Figure 30 for an example of this function. If master controller transmits I2C transaction for address 0xA0, the SER A with I2C pass-through enabled will transfer I2C commands to remote Camera A. The SER B with I2C pass-through disabled, any I2C commands will be bypassed on the I2C bus to Camera B. 28 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Feature Description (continued) DS90UB913Q CMOS Image Sensor DS90UB914Q DIN[11:0] ,HS,VS PCLK ROUT[11:0], HS,VS, PCLK 2 SDA SCL Camera A Slave ID: (0xA0) I C SER A: I2C _MASTER I2C_PASS_THRU Enabled DS90UB913Q CMOS Image Sensor SDA SCL 2 I C DES A: I2C_SLAVE DS90UB914Q DIN[11:0] ,HS,VS PCLK SDA SCL Camera B Slave ID: (0xA0) ECU Module ROUT[11:0], HS,VS, PCLK 2 SDA SCL 2 I C I C SER B: I2C_MASTER I2C_PASS_THRU Disabled PC Master DES B: I2C_SLAVE Figure 30. I2C Pass-Through 10.3.8 ID[x] Address Decoder on the Serializer The ID[x] pin on the serializer is used to decode and set the physical slave address of the serializer (I2C only) to allow up to five devices on the bus connected to the serializer using only a single pin. The pin sets one of the 5 possible addresses for each serializer device. The pin must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor and a pulldown resistor (RID) of the recommended value to set the physical device address. The recommended maximum resistor tolerance is 1%. 1.8V 10k VDDIO ID[x] RPU HOST RPU RID DS90UB913Q SCL SCL SDA SDA To other Devices Figure 31. ID[x] Address Decoder on the Serializer Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 29 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Table 1. ID[x] Resistor Value for DS90UB913Q-Q1 Serializer ID[x] Resistor Value — DS90UB913Q-Q1 Serializer Resistor RID0 Ω (1% Tolerance) Address 7'b Address 8'b 0 appended (WRITE) 0k 0x58 0xB0 2k 0x59 0xB2 4.7 k 0x5A 0xB4 8.2 k 0x5B 0xB6 14 k 0x5C 0xB8 100 k 0x5D 0xBA 10.3.9 ID[x] Address Decoder on the Deserializer The IDx[0] and IDx[1] pins on the deserializer are used to decode and set the physical slave address of the deserializer (I2C only) to allow up to 16 devices on the bus using only two pins. The pins set one of 16 possible addresses for each deserializer device. As there will be more deserializer devices connected on the same board than serializers, more I2C device addresses have been defined for the DS90UB914Q-Q1 deserializer than the DSDS90UB913Q-Q1 serializer. The pins must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor and two pulldown resistors (RID0 and RID1) of the recommended value to set the physical device address. The recommended maximum resistor tolerance is 1%. 1.8V 1.8V 10k 10k RID1 RID0 VDDIO IDx[0] RPU IDx[1] RPU HOST DS90UB914Q SCL SCL SDA SDA To other Devices Figure 32. ID[x[ Address Decoder on the Deserializer Table 2. Resistor Values for IDx[0] and IDx[1] on DS90UB914Q-Q1 Deserializer ID[X] RESISTOR VALUE — DS90UB913Q SERIALIZER 30 RESISTOR RID1 Ω (1%TOLERANCE) RESISTOR RID0 Ω (1%TOLERANCE) ADDRESS 7'b ADDRESS 8'b 0 APPENDED (WRITE) 0k 0k 0x60 0xC0 0k 3k 0x61 0xC2 0k 11 k 0x62 0xC4 0k 100 k 0x63 0xC6 3k 0k 0x64 0xC8 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Table 2. Resistor Values for IDx[0] and IDx[1] on DS90UB914Q-Q1 Deserializer (continued) ID[X] RESISTOR VALUE — DS90UB913Q SERIALIZER 3k 3k 0x65 0xCA 3k 11 k 0x66 0XCC 3k 100 k 0x67 0XCE 11 k 0k 0x68 0XD0 11 k 3k 0x69 0XD2 11 k 11 k 0x6A 0XD4 11 k 100 k 0x6B 0XD6 100 k 0k 0x6C 0XD8 100 k 3k 0x6D 0XDA 100 k 11 k 0x6E 0XDC 100 k 100 k 0x6F 0XDE 10.3.10 Programmable Controller An integrated I2C slave controller is embedded in the DS90UB913Q-Q1 serializer as well as the DS90UB914QQ1 deserializer. It must be used to configure the extra features embedded within the programmable registers or it can be used to control the set of programmable GPIOs. 10.3.11 Synchronizing Multiple Cameras For applications requiring multiple cameras for frame-synchronization, TI recommends to utilize the GeneralPurpose Input/Output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To synchronize the cameras properly, the system controller needs to provide a field sync output (such as a vertical or frame sync signal) and the cameras must be set to accept an auxiliary sync input. The vertical synchronize signal corresponds to the start and end of a frame and the start and end of a field. NOTE this form of synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from the bidirectional control channel, there will be a time variation of the GPIO signals arriving at the different target devices (between the parallel links). The maximum latency delta (t1) of the GPIO data transmitted across multiple links is 25 µs. NOTE The user must verify that the timing variations between the different links are within their system and timing specifications. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 31 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com See Figure 33 for an example of synchronizing multiple cameras. The maximum time (t1) between the rising edge of GPIO (that is, sync signal) arriving at Camera A and Camera B is 25 µs. DS90UB913Q Camera A CMOS Image Sensor DS90UB914Q DATA PCLK DATA PCLK 2 I C Serializer A FSYNC FSO GPIO GPO FSIN FSYNC 2 I C Deserializer A ECU Module Camera B CMOS Image Sensor DS90UB913Q DS90UB914Q DATA PCLK DATA PCLK 2 I C Serializer B FSYNC FSO GPIO GPO FSIN FSYNC 2 PC I C Deserializer B Figure 33. Synchronizing Multiple Cameras DES A GPIO[n] Input SER B GPIO[n] Output | SER A GPIO[n] Output | DES B GPIO[n] Input t1 Figure 34. GPIO Delta Latency 10.3.12 General-Purpose I/O (GPIO) Descriptions There are 4 GPOs on the serializer and 4 GPIOs on the deserializer when the DS90UB91xQ-Q1 chipsets are run off the pixel clock from the imager as the reference clock source. The GPOs on the serializer can be configured as outputs for the input signals that are fed into the deserializer GPIOs. In addition, the GPOs on the serializer can behave as outputs of the local register on the serializer. The GPIOs on the deserializer can be configured to be the input signals feeding the output of the GPOs on the serializer. In addition the GPIOs on the deserializer can be configured to behave as outputs of the local register on the deserializer. If the DS90UB91xQ-Q1 chipsets are run off the external oscillator source as the reference clock, then GPO3 on the serializer is automatically configured to be the input for the external clock and GPIO2 on the deserializer is configured to be the output of the divide-by-2 clock which is fed into the imager as its reference clock. In this case, the GPIO2 and GPIO3 on the deserializer can only behave as outputs of the local register on the deserializer. The GPIO maximum switching rate is up to 66 kHz when configured for communication between deserializer GPIO to serializer GPO. 32 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 10.3.13 LVCMOS VDDIO Option 1.8-V, 2.8-V, and 3.3-V serializer inputs and 1.8-V and 3.3-V deserializer outputs are user configurable to provide compatibility with 1.8-V, 2.8-V and 3.3-V system interfaces. 10.3.14 Deserializer – Adaptive Input Equalization (AEQ) The receiver inputs provide an adaptive input equalization filter in order to compensate for loss from the media. The level of equalization can also be manually selected through register controls. The fully-adaptive equalizer output can be seen using the CMLOUTP/CMLOUTN pins in the deserializer. 18 EQUALIZER GAIN (dB) 16 14 12 10 8 6 4 2 0 100 200 300 400 500 600 700 SERIAL LINE FREQUENCY (MHz) Figure 35. Maximum Equalizer Gain vs. Line Frequency 10.3.15 EMI Reduction 10.3.15.1 Deserializer Staggered Output The receiver staggers output switching to provide a random distribution of transitions within a defined window. Outputs transitions are distributed randomly. This minimizes the number of outputs switching simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall EMI. 10.3.15.2 Spread Spectrum Clock Generation (SSCG) on the Deserializer The DS90UB914Q-Q1 parallel data and clock outputs have programmable SSCG ranges from 10 MHz to 100 MHz. The modulation rate and modulation frequency variation of output spread is controlled through the SSC control registers on the DS90UB914Q-Q1 device. SSC profiles can be generated using bits [3:0] in register 0x02 in the deserializer. 10.4 Device Functional Modes 10.4.1 DS90UB91xQ-Q1 Operation With External Oscillator as Reference Clock In some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance of the DS90UB91xQ-Q1 chipsets. In this case, the DS90UB913Q-Q1 device should be operated by using an external clock source as the reference clock for the DS90UB91xQ-Q1 chipsets. This is the recommended operating mode. The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB913Q-Q1 serializer and this divided clock output is used as the reference clock for the imager. The output data and pixel clock from the imager are then fed into the DS90UB913Q-Q1 device. Figure 36 shows the operation of the DS90UB1xQ-Q1 chipsets while using an external automotive grade oscillator. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 33 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Device Functional Modes (continued) DS90UB913Q Serializer FPD Link IIIHigh Speed Camera Data DOUT+ 10 or 12 Image Sensor DATA HSYNC DIN[11:0] or DIN[9:0] HSYNC, VSYNC DOUT- VSYNC Pixel Clock DS90UB914Q Deserializer Camera Data RIN+ RIN- 10 or 12 ROUT[11:0] or ROUT[9:0] HSYNC, VSYNC Bi-Directional Control Channel PCLK PCLK DATA HSYNC VSYNC Pixel Clock ECU Module SDA SDA SCL 2 SCL PLL GPIO[3:0] GPO[1:0] GPO[1:0] SDA Camera Unit Reference Clock (Ext. OSC/2) 4 GPO[3:0] SCL Microcontroller SDA SCL GPO3 ÷2 GPO2 External Oscillator Figure 36. DS90UB91xQ-Q1 Operation in the External Oscillator Mode When the DS90UB913Q-Q1 device is operated using an external oscillator, the GPO3 pin on the DS90UB913Q-Q1 is the input pin for the external oscillator. In applications where the DS90UB913Q-Q1 device is operated from an external oscillator, the divide-by-2 circuit in the DS90UB913Q-Q1 device feeds back the divided clock output to the imager device through GPO2 pin. The pixel clock to external oscillator ratios needs to be fixed for the 12-bit high-frequency mode and the 10-bit mode. NOTE In the 10-bit mode, the pixel clock frequency divided by the external oscillator frequency must be 2. In the 12-bit high-frequency mode, the pixel clock frequency divided by the external oscillator frequency must be 1.5. For example, if the external oscillator frequency is 48 MHz in the 10-bit mode, the pixel clock frequency of the imager needs to be twice of the external oscillator frequency, that is, 96 MHz. If the external oscillator frequency is 48 MHz in the 12-bit high-frequency mode, the pixel clock frequency of the imager needs to be 1.5 times of the external oscillator frequency, that is, 72 MHz. In this mode, GPO2 and GPO3 on the serializer cannot act as the output of the input signal coming from GPIO2 or GPIO3 on the deserializer. 10.4.2 DS90UB91xQ-Q1 Operation With Pixel Clock from Imager as Reference Clock The DS90UB91xQ-Q1 chipsets can be operated by using the pixel clock from the imager as the reference clock.Figure 37 shows the operation of the DS90UB91xQ-Q1 chipsets using the pixel clock from the imager. If the DS90UB913Q-Q1 device is operated using the pixel clock from the imager as the reference clock, then the imager uses an external oscillator as its reference clock. There are 4 GPIOs on the serializer and 4 GPIOs on the deserializer in this mode. 34 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Device Functional Modes (continued) DS90UB914Q Deserializer DS90UB913Q FPD-Link III Camera Data Image Sensor Camera Data DOUT+ 10 or 12 DIN[11:0] or DIN[9:0] FV,LV YUV HSYNC VSYNC ROUT[11:0] or ROUT[9:0] FV, LV DOUT- SDA SCL YUV HSYNC RIN0- VSYNC Bi-Directional Back Channel SDA SCL 10 or 12 RIN0+ PCLK Pixel Clock 4 GPO[3:0] GPIO[3:0] GPO Pixel Clock Camera Unit ECU Module RIN1+ GPIO RIN1- PLL 4 SDA PCLK SCL Microcontroller SDA SCL Ext. Oscillator Figure 37. DS90UB91xQ-Q1 Operation in PCLK mode 10.4.3 MODE Pin on Serializer The mode pin on the serializer can be configured to select if the DS90UB913Q-Q1 device is to be operated from the external oscillator or the PCLK from the imager. The pin must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor and a pulldown resistor (RMODE) of the recommended value to set the modes shown in Figure 38. The recommended maximum resistor tolerance is 1%. 1.8V 10k VDDIO MODE RPU RPU RMODE DS90UB913Q HOST SCL SCL SDA SDA To other Devices Figure 38. MODE Pin Configuration on DS90UB913Q-Q1 Table 3. DS90UB913Q-Q1 Serializer MODE Resistor Value MODE SELECT RMODE RESISTOR VALUE PCLK from imager mode 100 kΩ External Oscillator mode 4.7 kΩ Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 35 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com 10.4.4 MODE Pin on Deserializer The mode pin on the deserializer can be used to configure the device to work in the 12-bit low-frequency mode, 12-bit high frequency mode or the 10-bit mode of operation. Internally, the DS90UB91xQ-Q1 chipset operates in a divide-by-1 mode in the 12-bit low-frequency mode, divide-by-2 mode in the 10-bit mode and a divide-by-1.5 mode in the 12-bit high-frequency mode. The pin must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor and a pulldown resistor (RMODE) of the recommended value to set the different modes in the deserializer as mentioned in Table 4. The deserializer automatically configures the serializer to correct mode through the backchannel. The recommended maximum resistor tolerance is 1% . 1.8V 10k VDDIO MODE RPU HOST RPU RMODE DS90UB914Q SCL SCL SDA SDA To Other Devices Figure 39. Mode Pin Configuration on DS90UB914Q-Q1 Deserializer Table 4. DS90UB914Q-Q1 Deserializer MODE Resistor Value DS90UB914Q-Q1 DESERIALIZER MODE RESISTOR VALUE 36 MODE SELECT RMODE RESISTOR VALUE 12-bit low-frequency mode 10 to 50 MHz PCLK 10 to 12 bit DATA + 2 SYNC 0Ω 12-bit low-frequency mode 15 to 75 MHz PCLK 10 to 12 bit DATA + 2 SYNC 3 kΩ 10-bit mode 20 to 100 MHz PCLK 10 to 10 bit DATA + 2 SYNC 11 kΩ Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 10.4.5 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL) When PDB is driven HIGH, the CDR PLL of the deserializer begins locking to the serial input and LOCK is TRISTATE or LOW (depending on the value of the OEN setting). After the DS90UB914Q-Q1 completes its lock sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available on the parallel bus and PCLK outputs. The states of the outputs are based on the OEN and OSS_SEL setting (Table 3). See Figure 20. Table 5. Output States INPUTS OUTPUTS SERIAI INPUTS PDB OEN OSS LOCK PASS DATA, GPIO, I2S CLK X 0 X X 1 0 X Z Z Z Z 0 L or H L L X 1 L 0 1 L or H Z Z Z Static 1 1 0 L L L L/Osc (Register Bit Enable) Static 1 1 1 H Previous State L L Active 1 1 0 H L L L Active 1 1 1 H Valid Valid Valid 10.4.6 Multiple Device Addressing Some applications require multiple camera devices with the same fixed address to be accessed on the same I2C bus. The DS90UB91xQ-Q1 provides slave ID matching/aliasing to generate different target slave addresses when connecting more than two identical devices together on the same bus. This allows the slave devices to be independently addressed. Each device connected to the bus is addressable through a unique ID by programming of the SLAVE_ID_MATCH register on deserializer. This will remap the SLAVE_ID_MATCH address to the target SLAVE_ID_INDEX address; up to 8 ID indexes are supported. The ECU Controller must keep track of the list of I2C peripherals in order to properly address the target device. See Figure 40 for an example of multiple device addressing. • ECU is the I2C master and has an I2C master interface • The I2C interfaces in DES A and DES B are both slave interfaces • The I2C protocol is bridged from DES A to SER A and from DES B to SER B • The I2C interfaces in SER A and SER B are both master interfaces If master controller transmits I2C slave 0xA0, the DES A address 0xC0 will forward the transaction to remote Camera A. If the controller transmits slave address 0xA4, the DES B 0xC2 will recognize that 0xA4 is mapped to 0xA0 and will be transmitted to the remote Camera B. If controller sends command to address 0xA6, the DES B 0xC2 will forward transaction to slave device 0xA2. The Slave ID index/match is supported only in the camera mode (SER: MODE pin = L; DES: MODE pin = H). For Multiple device addressing in display mode (SER: MODE pin = H; DES: MODE pin = L), use the I2C passthrough function. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 37 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Camera A DS90UB913Q Slave ID: (0xA0) CMOS Image Sensor DS90UB914Q ROUT[11:0], HS, VS, PCLK DIN[11:0] , HS, VS, PCLK SDA SCL 2 I C SER A: ID[x](0xB0) PC/ EEPROM Slave ID: (0xA2) Camera B DS90UB913Q Slave ID: (0xA0) DES A: ID[x](0xC0) SLAVE_ID1_MATCH(0xA0) SLAVE_ID1_INDEX(0xA0) SLAVE_ID2_MATCH(0xA2) SLAVE_ID2_INDEX(0xA2) SDA SCL ROUT[11:0], HS, VS, PCLK 2 I C SER B: ID[x](0xB2) PC/ EEPROM ECU Module DS90UB914Q DIN[11:0] , HS, VS, PCLK CMOS Image Sensor SDA SCL 2 I C Slave ID: (0xA2) SDA SCL 2 I C DES B: ID[x](0xC2) SLAVE_ID2_MATCH(0xA4) SLAVE_ID2_INDEX(0xA0) SLAVE_ID2_MATCH(0xA6) SLAVE_ID2_INDEX(0xA2) PC Master Figure 40. Multiple Device Addressing 10.4.7 Powerdown The SER has a PDB input pin to ENABLE or Powerdown (SLEEP) the device. The modes can be controlled by the host and is used to disable the Link to save power when the remote device is not operational. In this mode, if the PDB pin is tied High and the SER will enter SLEEP when the PCLK stops. When the PCLK starts again, the SER will then lock to the valid input PCLK and transmit the data to the DES. In SLEEP mode, the high-speed driver outputs are static (High). The DES has a PDB input pin to ENABLE or Powerdown (SLEEP) the device. This pin can be controlled by the system and is used to disable the DES to save power. An auto mode is also available. In this mode, the PDB pin is tied High and the DES will enter SLEEP when the serial stream stops. When the serial stream starts up again, the DES will lock to the input stream and assert the LOCK pin and output valid data. In SLEEP mode, the Data and PCLK outputs are set by the OSS_SEL configuration. 10.4.8 Pixel Clock Edge Select (TRFB / RRFB) The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0, data is strobed on the falling edge of the PCLK. PCLK DIN/ ROUT TRFB/RRFB: 0 TRFB/RRFB: 1 Figure 41. Programmable PCLK Strobe Select 38 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 10.4.9 Power-Up Requirements and PDB Pin When power is applied, the VDDIO supply needs to reach the expected operating voltage (1.8 V to 3.3 V) before the other supplies (VDDn) begin to ramp. It is required to delay and release the PDB Signal after VDD (VDDn and VDDIO) power supplies have settled to the recommended operating voltage. An external RC network can be connected to the PDB pin to ensure PDB arrives after all the VDD has stabilized. 1.8V OR 3.3V VDDIO 1.8V VDD_CORE, All other 1.8V Supplies 1.8V OR 3.3V PDB Figure 42. Power-Up Sequencing 10.4.10 Built-In Self Test An optional AT-Speed, Built-In Self Test (BIST) feature supports the testing of the high-speed serial link and lowspeed back channel. This is useful in the prototype stage, equipment production, and in-system test and also for system diagnostics. 10.4.11 BIST Configuration and Status The chipset can be programmed into BIST mode using either pins or registers. By default BIST configuration is controlled through pins. BIST can be configured through registers using BIST Control register (0x24). Pin based configuration is defined as follows: • BISTEN : Enable the BIST Process • GPIO0 and GPIO1 : Defines the BIST clock source (PCLK vs. various frequencies of internal OSC Table 6. BIST Configuration DESERIALIZER GPIO[0:1] OSCILLATOR SOURCE BIST FREQUENCY (MHZ) 00 External PCLK PCLK or External Oscillator 01 Internal 50 10 Internal 25 11 Internal 12.5 The BIST mode provides various options for source PCLK. Using external pins, GPIO0 and GPIO1 or using registers, customer can program the BIST mode to use external PCLK or various OSC frequencies. The BIST status can be monitored real time on PASS pin. For every frame with error(s), PASS pin toggles low for half PCLK period. If two consecutive frames have errors, PCLK will toggle twice to allow counting of frames with errors. Once the BIST is done, the PASS pin reflects the pass/fail status of the last BIST run. The status can also be read through I2C for the number of frames in errors. BIST status on PASS pin remains until it is changed by a new BIST session or a reset. The BIST status on PASS pin is not maintained till RX loses LOCK after BISTEN is deassserted. To evaluate BIST in the external oscillator mode, both external oscillator and PCLK need to be present. The BIST status on PASS pin is not maintained till RX loses LOCK after BISTEN is deassserted. So for all practical purposes, the BIST status can be monitored from register 0x25, that is, BIST Error Count on the DS90UB914Q-Q1 deserializer. To evaluate BIST in the external oscillator mode, both external oscillator and PCLK need to be present. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 39 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com 10.4.11.1 Sample BIST Sequence Step 1. For the DS90UB91xQ-Q1 FPD-Link III chipset, BIST Mode is enabled through the BISTEN pin of DS90UB914Q-Q1 FPD-Link III deserializer. The desired clock source is selected through the GPIO0 and GPIO1 pins as shown in Table 4. Step 2. The DS90UB913Q-Q1 serializer is woken up through the back channel if it is not already on. The SSO pattern on the data pins is send through the FPD-Link III to the deserializer. Once the serializer and deserializer are in the BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking data stream. If an error in the payload is detected the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate. Step 3. To stop the BIST mode, the deserializer BISTEN pin is set low. The deserializer stops checking the data. The final test result is not maintained on the PASS pin. To monitor the BIST status, check the BIST Error Count register, 0x25 on the deserializer. Step 4. The link returns to normal operation after the deserailzer BISTEN pin is low. Figure 44 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data transmission, and so forth), thus they may be introduced by greatly extending the cable length, faulting the interconnect, or by reducing signal condition enhancements (RX equalization). Normal Step 1: DES in BIST BIST Wait Step 2: Wait, SER in BIST BIST start Step 3: DES in Normal Mode - check PASS BIST stop Step 4: DES/SER in Normal Figure 43. AT-Speed BIST System Flow Diagram DES Outputs BISTEN (DES) LOCK PCLK (RFB = L) ROUT[0:11], HS, VS Case 1 - Pass SSO DATA (internal) PASS Prior Result PASS PASS X X Case 2 - Fail X = bit error(s) DATA (internal) X FAIL Prior Result Normal BIST Result Held BIST Test BIST Duration Normal Figure 44. BIST Timing Diagram 40 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 10.5 Register Maps Table 7. DS90UB913Q-Q1 Control Registers ADDR (HEX) 0x00 0x01 NAME BITS FIELD R/W DESCRIPTION 7-bit address of serializer; 0x58'h (0101_1000X'b) default 7:1 DEVICE ID 0 SER ID SEL 0: Device ID is from ID[x] 1: Register I2C Device ID overrides ID[x] 7 RSVD Reserved 6 RDS RW 0 Digital Output Drive Strength 1: High Drive Strength 0: Low Drive Strength 5 VDDIO Control RW 1 Auto Voltage Control 1: Enable 0: Disable 4 VDDIO MODE RW 1 VDDIOVoltage set 0: 1.8V 1: 3.3V 2 I C Device ID RW 0x58'h 3 ANAPWDN RW 0 This register can be set only through local I2C access 1: Analog power-down : Powers Down the analog block in the serializer 0: No effect 2 RSVD RW 0 Reserved 1 DIGITAL RESET1 RW 0 1: Resets the digital block except for register values values. Does not affect device I2C Bus or Device ID. This bit is self-clearing. 0: Normal Operation 0 DIGITAL RESET0 RW 1 1: Digital Reset, resets the entire digital block including all register values.This bit is self-clearing. 0: Normal Operation. Power and Reset 0x02 0x03 DEFAULT RESERVED General Configuration 7 RX CRC Checker Enable RW 1 Back-channel CRC Checker Enable 1:Enabled 0:Disabled 6 TX Parity Generator Enable RW 1 Forward channel Parity Generator Enable 1: Enable 0: Disable 5 CRC Error Reset RW 0 Clear CRC Error Counters. This bit is NOT self-clearing. 1: Clear Counters 0: Normal Operation 0 Automatically Acknowledge I2C Remote Write The mode works when the system is LOCKed. 1: Enable: When enabled, I2C writes to the deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are immediately acknowledged without waiting for the deserializer to acknowledge the write. The accesses are then re-mapped to address specified in 0x06. 0: Disable 4 I2C Remote Write Auto Acknowledge RW 3 I2C Pass All RW 0 1: Enable Forward Control Channel pass-through of all I2C accesses to I2C Slave IDs that do not match the Serializer I2C Slave ID. The I2C accesses are then remapped to address specified in register 0x06. 0: Enable Forward Control Channel pass-through only of I2C accesses to I2C Slave IDs matching either the remote Deserializer Slave ID or the remote Slave ID. 2 I2C PASSTHROUGH RW 1 I2C Pass-Through Mode 0: Pass-Through Disabled 1: Pass-Through Enabled Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 41 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Register Maps (continued) Table 7. DS90UB913Q-Q1 Control Registers (continued) ADDR (HEX) NAME BITS 1 0x03 FIELD OV_CLK2PLL R/W RW RW 7 RSVD RW 0 Reserved 6 RSVD RW 0 Reserved. RW 0 Allows overriding mode select bits coming from backchannel 1: Overrides MODE select bits 0: Does not override MODE select bits RESERVED Mode Select 5 MODE_OVERRIDE 4 MODE_UP To DATE R 0 Indicates that the status of mode select from deserializer is up to date 3 Pin_MODE_12–bit High Frequency R 0 1: 12-bit high-frequency mode is selected. 0: 12-bit high-frequency mode is not selected. 2 Pin_MODE_10–bit mode R 0 1: 10-bit mode is selected. 0: 10-bit mode is not selected. DESAlias 7:1 0 SlaveID 7:1 0 42 RSVD Reserved Desializer Device ID RW 0x00 7-bit Deserializer Device ID configures the I2C Slave ID of the remote deserializer. A value of 0 in this field disables I2C access to the remote deserializer. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but should also assert the FREEZE DEVICE ID bit to prevent overwriting by the Bidirectional Control Channel. Freeze Device ID RW 0 1: Prevents auto-loading of the Deserializer Device ID by the bidirectional control channel. The ID will be frozen at the value written. 0: Update 0 7-bit Remote Deserializer Device Alias ID Configures the decoder for detecting transactions designated for an I2C deserializer device. The transaction will be remapped to the address specified in the DES ID register. A value of 0 in this field disables access to the remote I2C Slave. DES ID 0 0x08 1 Pixel Clock Edge Select 1: Parallel Interface Data is strobed on the Rising Clock Edge. 0: Parallel Interface Data is strobed on the Falling Clock Edge. TRFB 7:1 0x07 0 0 1:0 0x06 DESCRIPTION 1:Enabled : When enabled this registers overrides the clock to PLL mode (External Oscillator mode or Direct PCLK mode) defined through MODE pin and allows selection through register 0x35 in the serializer 0: Disabled : When disabled, Clock to PLL mode (External Oscillator mode or Direct PCLK mode) is defined through MODE pin on the serializer. General Configuration 0x04 0x05 DEFAULT Deserializer ALIAS ID RW RSVD Reserved SLAVE ID 7-bit Remote Slave Device ID Configures the physical I2C address of the remote I2C Slave device attached to the remote deserializer. If an I2C transaction is addressed to the Slave Alias ID, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the deserializer. A value of 0 in this field disables access to the remote I2C slave. RSVD Submit Documentation Feedback RW 0x00 Reserved Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Register Maps (continued) Table 7. DS90UB913Q-Q1 Control Registers (continued) ADDR (HEX) 0x09 NAME SlaveAlias BITS 7:1 0 FIELD SLAVE ALIAS ID R/W RW DEFAULT DESCRIPTION 0x00 7-bit Remote Slave Device Alias ID Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote deserializer. The transaction will be remapped to the address specified in the Slave ID register. A value of 0 in this field disables access to the remote I2C Slave. RSVD Reserved 0x0A CRC Errors 7:0 CRC Error Byte 0 R 0 Number of back-channel CRC errors during normal operation. Least Significant byte 0x0B CRC Errors 7:0 CRC Error Byte 1 R 0 Number of back-channel CRC errors during normal operation. Most Significant byte 7:5 Rev-ID R 0 Revision ID 0x00: Production 4 RX Lock Detect R 0 1: RX LOCKED 0: RX not LOCKED 3 BIST CRC Error Status R 0 1: CRC errors in BIST mode 0: No CRC errors in BIST mode 2 PCLK Detect R 0 1: Valid PCLK detected 0: Valid PCLK not detected 0 1: CRC error is detected during communication with deserializer. This bit is cleared upon loss of link or assertion of CRC ERROR RESET in register 0x04. 0: No effect R 0 1: Cable link detected 0: Cable link not detected This includes any of the following faults — Cable Open — + and - shorted — Short to GND — Short to battery RW 0 Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled. 0x0C General Status 1 0x0D GPO[0] and GPO[1] Configuration DES Error R 0 LINK Detect 7 GPO1 Output Value 6 GPO1 Remote Enable RW 1 Remote GPIO Control 1: Enable GPIO control from remote deserializer. The GPIO pin needs to be an output, and the value is received from the remote deserializer. 0: Disable GPIO control from remote deserializer. 5 GPO1 Direction RW 0 1: Input 0: Output 4 GPO0 Enable RW 1 1: GPIO enable 0: Tri-state 0 Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled. 3 GPO0 Output Value RW 2 GPO0 Remote Enable RW 1 Remote GPIO Control 1: Enable GPIO control from remote deserializer. The GPIO pin needs to be an output, and the value is received from the remote deserializer. 0: Disable GPIO control from remote deserializer. 1 GPO0 Direction RW 0 1: Input 0: Output 0 GPO0 Enable RW 1 1: GPIO enable 0: Tri-state Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 43 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Register Maps (continued) Table 7. DS90UB913Q-Q1 Control Registers (continued) ADDR (HEX) 0x0E NAME GPO[2] and GPO[3] Configuration BITS DEFAULT DESCRIPTION 0 RW 0 Remote GPIO Control 1: Enable GPIO control from remote deserializer. The GPIO pin needs to be an output, and the value is received from the remote deserializer. 0: Disable GPIO control from remote deserializer. GPO3 Direction RW 1 1: Input 0: Output 4 GPO3 Enable RW 1 1: GPIO enable 0: Tri-state 3 GPO2 Output Value RW 0 Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled. 2 GPO2 Remote Enable RW 1 Remote GPIO Control 1: Enable GPIO control from remote deserializer. The GPIO pin needs to be an output, and the value is received from the remote deserializer. 0: Disable GPIO control from remote deserializer. 1 GPO2 Direction RW 0 1: Input 0: Output 0 GPO2 Enable RW 1 1: GPIO enable 0: Tri-state 7 GPO3 Output Value 6 GPO3 Remote Enable 5 4:3 2 RW RSVD Reserved SDA Output Delay 00 SDA Output Delay This field configures output delay on the SDA output. Setting this value will increase output delay in units of 50 ns. Nominal output delay values for SCL to SDA are: 00 : 350 ns 01: 400 ns 10: 450 ns 11: 500 ns 0 Disable Remote Writes to Local Registers Setting this bit to a 1 will prevent remote writes to local device registers from across the control channel. This prevents writes to the serializer registers from an I2C master attached to the deserializer. Setting this bit does not affect remote access to I2C slaves at the serializer. 0 Speed up I2C Bus Watchdog Timer 1: Watchdog Timer expires after approximately 50 microseconds 0: Watchdog Timer expires after approximately 1 second. 0 1. Disable I2C Bus Watchdog Timer When the I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signaling occurs for approximately 1 second, the I2C bus will assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL 0: No effect Local Write Disable RW RW I2C Master Config 1 0 44 R/W Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled. 7:5 0x0F FIELD I2C Bus Timer Speed up I2C Bus Timer Disable Submit Documentation Feedback RW RW Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Register Maps (continued) Table 7. DS90UB913Q-Q1 Control Registers (continued) ADDR (HEX) NAME BITS 7 0x10 0x11 2 FIELD R/W DEFAULT RSVD Reserved 6:4 SDA Hold Time RW 0x1 Internal SDA Hold Time. This field configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 50 ns. 3:0 I2C Filter Depth RW 0x7 I2C Glitch Filter Depth This field configures the maximum width of glitch pulses on the SCL and SDA inputs that will be rejected. Units are 10 ns. 0x82 I2C Master SCL High Time This field configures the high pulse width of the SCL output when the serializer is the Master on the local I2C bus. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum (4µs + 1µs of rise time for cases where rise time is very fast) SCL high time with the internal oscillator clock running at 26MHz rather than the nominal 20 MHz. I2C SCL Low Time This field configures the low pulse width of the SCL output when the serializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum (4.7 µs + 0.3 µs of fall time for cases where fall time is very fast) SCL low time with the internal oscillator clock running at 26 MHz rather than the nominal 20 MHz. I C Control SCL High Time DESCRIPTION 7:0 SCL High Time RW 0x12 SCL LOW Time 7:0 SCL Low Time RW 0x82 0x13 General-Purpose Control 7:0 GPCR[7:0] RW 0 7:3 RSVD Reserved 2:1 Clock Source RW 0x0 Allows choosing different OSC clock frequencies for forward channel frame. OSC Clock Frequency in Functional Mode when OSC mode is selected or when the selected clock source is not present, for example, missing PCLK/ External Oscillator. See Table 9 for oscillator clock frequencies when PCLK/ External Clock is missing. 0 BIST Enable RW 0 0x14 BIST Control 0x15 0x1D 0x1E BIST Control: 1: Enable BIST mode 0: Disable BIST mode RESERVED 7:1 BCC Watchdog Timer RW 0x7F The watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. This field sets the Bidirectional Control Channel Watchdog Timeout value in units of 2ms. This field should not be set to 0. 0 BCC Watchdog Timer Disable RW 0 Disable Bidirectional Control Channel Watchdog Timer 1: Disables BCC Watchdog Timer operation 0: Enables BCC Watchdog Timer operation BCC Watchdog Control 0x1F0x29 0x2A 1: High 0: Low RESERVED CRC Errors 7:0 BIST Mode CRC Errors Count Copyright © 2012–2015, Texas Instruments Incorporated R 0 Number of CRC Errors in the back channel when in BIST mode Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 45 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Register Maps (continued) Table 7. DS90UB913Q-Q1 Control Registers (continued) ADDR (HEX) NAME BITS FIELD R/W 0x2B 0x34 DESCRIPTION RESERVED 7:4 0x35 DEFAULT PLL Clock Overwrite RSVD Reserved 3 PIN_LOCK to External Oscillator RW 0 Status of mode select pin 1: Indicates External Oscillator mode is selected by mode-resistor 0: External Oscillator mode is not selected by moderesistor 2 PIN_LOCK to Oscillator RW 0 Status of mode select pin 1: Indicates PCLK mode is selected by mode-resistor 0: PCLK mode not selected by mode-resistor 1 LOCK to External Oscillator 0 Affects only when 0x03[1]=1 (OV_CLK2PLL) and 0x35[0]=0. 1: Routes GPO3 directly to PLL 0: Allows PLL to lock to PCLK" 0 RSVD RW Reserved Table 8. DS90UB914Q-Q1 Control Registers ADDR (HEX) NAME BITS 7:1 0x00 I2C Device ID 0 7:6 5 4:2 0x01 46 FIELD R/W DEFAULT DEVICE ID RW 0x60'h Deserializer ID Select RW 0 DESCRIPTION 7-bit address of deserializer; 0x60h 0: Deserializer Device ID is set using address coming from CAD 1: Register I2C Device ID overrides ID[x] RSVD Reserved ANAPWDN This register can be set only through local I2C access 1: Analog power-down : Powers down the analog block in the serializer 0: No effect RW 0 RSVD Reserved Reset 1 Digital Reset 1 RW 0 Digital Reset Resets the entire digital block except registers. This bit is self-clearing. 1: Reset 0: No effect 0 Digital Reset 0 RW 0 Digital Reset Resets the entire digital block including registers. This bit is self-clearing. 1: Reset 0: No effect Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Table 8. DS90UB914Q-Q1 Control Registers (continued) ADDR (HEX) 0x02 NAME BITS 0x03 R/W DEFAULT DESCRIPTION 7 RSVD Reserved 6 RSVD Reserved 5 Auto-Clock RW 0 1: Output PCLK or OSC clock when not LOCKED 0: Only PCLK 4 SSCG LFMODE RW 0 1: Selects 8x mode for 10-18 MHz frequency range in SSCG 0: SSCG running at 4X mode SSCG RW 0 SSCG Select 0000: Normal Operation, SSCG OFF 0001: fmod (kHz) PCLK/2168, fdev ±0.50% 0010: fmod (kHz) PCLK/2168, fdev ±1.00% 0011: fmod (kHz) PCLK/2168, fdev ±1.50% 0100: fmod (kHz) PCLK/2168, fdev ±2.00% 0101: fmod (kHz) PCLK/1300, fdev ±0.50% 0110: fmod (kHz) PCLK/1300, fdev ±1.00% 0111: fmod (kHz) PCLK/1300, fdev ±1.50% 1000: fmod (kHz) PCLK/1300, fdev ±2.00% 1001: fmod (kHz) PCLK/868, fdev ±0.50% 1010: fmod (kHz) PCLK/868, fdev ±1.00% 1011: fmod (kHz) PCLK/868, fdev ±1.50% 1100: fmod (kHz) PCLK/868, fdev ±2.00% 1101: fmod (kHz) PCLK/650, fdev ±0.50% 1110: fmod (kHz) PCLK/650, fdev ±1.00% 1111: fmod (kHz) PCLK/650, fdev ±1.50% Note: This register should be changed only after disabling SSCG. 7 RX Parity Checker Enable RW 1 Forward-Channel Parity Checker Enable 1: Enable 0: Disable 6 TX CRC Checker Enable RW 1 Back-Channel CRC Generator Enable 1: Enable 0: Disable 5 VDDIO Control RW 1 Auto voltage control 1: Enable (auto-detect mode) 0: Disable 4 VDDIO Mode RW 0 VDDIO voltage set 1: 3.3 V 0: 1.8 V 3 I2C Passthrough RW 1 I2C Pass-Through Mode 1: Pass-Through Enabled 0: Pass-Through Disabled General Configuration 0 3:0 0x03 FIELD General Configuration 1 2 AUTO ACK RW 0 Automatically Acknowledge I2C Remote Write When enabled, I2C writes to the deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are immediately acknowledged without waiting for the deserializer to acknowledge the write. The accesses are then remapped to address specified in 0x06. This allows I2C bus without LOCK. 1: Enable 0: Disable 1 Parity Error Reset RW 0 Parity Error Reset, This bit is self-clearing. 1: Parity Error Reset 0: No effect 1 Pixel Clock Edge Select 1: Parallel Interface Data is strobed on the Rising Clock Edge. 0: Parallel Interface Data is strobed on the Falling Clock Edge. General Configuration 1 0 RRFB Copyright © 2012–2015, Texas Instruments Incorporated RW Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 47 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Table 8. DS90UB914Q-Q1 Control Registers (continued) ADDR (HEX) 0x04 NAME EQ Feature Control 1 BITS FIELD 7:0 EQ level - when AEQ bypass is enabled EQ setting is provided by this register RW 7:1 Remote ID RW 0x05 0x06 R/W DEFAULT 0x00 SER ID 0 Freeze Device ID Serializer Alias ID SER Alias 0 0x08 Slave ID[0] 7:1 0 0x09 Slave ID[1] 7:1 0 0x0A Slave ID[2] 7:1 0 0x0B Slave ID[3] 7:1 0 48 Equalization gain 0x00 = ~0.0 dB 0x01 = ~4.5 dB 0x03 = ~6.5 dB 0x07 = ~7.5 dB 0x0F = ~8.0 dB 0x1F = ~11.0 dB 0x3F = ~12.5 dB RESERVED RW 0x0C 0 7:1 0x07 DESCRIPTION RW 0x00 Remote Serializer ID Freeze Serializer Device ID Prevent autoloading of the serializer Device ID from the Forward Channel. The ID will be frozen at the value written. 7-bit Remote Serializer Device Alias ID Configures the decoder for detecting transactions designated for an I2C deserializer device. The transaction will be remapped to the address specified in the SER ID register. A value of 0 in this field disables access to the remote I2C Slave. RSVD Reserved Slave ID0 7-bit Remote Slave Device ID 0 Configures the physical I2C address of the remote I2C Slave device attached to the remote serializer. If an I2C transaction is addressed to the Slave Alias ID0, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the serializer. RW 0 RSVD Reserved Slave ID1 7-bit Remote Slave Device ID 1 Configures the physical I2C address of the remote I2C Slave device attached to the remote serializer. If an I2C transaction is addressed to the Slave Alias ID1, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the serializer. RW 0 RSVD Reserved Slave ID2 7-bit Remote Slave Device ID 2 Configures the physical I2C address of the remote I2C Slave device attached to the remote serializer. If an I2C transaction is addressed to the Slave Alias ID2, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the serializer. RW 0x00 RSVD Reserved Slave ID3 7-bit Remote Slave Device ID 3 Configures the physical I2C address of the remote I2C Slave device attached to the remote serializer. If an I2C transaction is addressed to the Slave Alias ID3, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the serializer. RSVD Submit Documentation Feedback RW 0 Reserved Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Table 8. DS90UB914Q-Q1 Control Registers (continued) ADDR (HEX) 0x0C NAME Slave ID[4] BITS 7:1 0 0x0D Slave ID[5] 7:1 0 0x0E Slave ID[6] 7:1 0 0x0F Slave ID[7] 7:1 0 0x10 Slave Alias[0] 7:1 0 0x11 Slave Alias[1] 7:1 0 FIELD Slave ID4 R/W RW DEFAULT DESCRIPTION 0 7-bit Remote Slave Device ID 4 Configures the physical I2C address of the remote I2C Slave device attached to the remote serializer. If an I2C transaction is addressed to the Slave Alias ID4, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the serializer. RSVD Reserved Slave ID5 7-bit Remote Slave Device ID 5 Configures the physical I2C address of the remote I2C Slave device attached to the remote serializer. If an I2C transaction is addressed to the Slave Alias ID5 , the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the serializer. RW 0x00 RSVD Reserved Slave ID6 7-bit Remote Slave Device ID 6 Configures the physical I2C address of the remote I2C Slave device attached to the remote serializer. If an I2C transaction is addressed to the Slave Alias ID6, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the serializer. RW 0 RSVD Reserved Slave ID7 7-bit Remote Slave Device ID 7 Configures the physical I2C address of the remote I2C Slave device attached to the remote serializer. If an I2C transaction is addressed to the Slave Alias ID7, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the serializer. RW 0x00 RSVD Reserved Slave Alias ID0 7-bit Remote Slave Device Alias ID 0 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote serializer. The transaction will be remapped to the address specified in the Slave ID0 register. A value of 0 in this field disables access to the remote I2C Slave. RW 0x00 RSVD Reserved Slave Alias ID1 7-bit Remote Slave Device Alias ID 1 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote serializer. The transaction will be remapped to the address specified in the Slave ID1 register. A value of 0 in this field disables access to the remote I2C Slave. RSVD Copyright © 2012–2015, Texas Instruments Incorporated RW 0x00 Reserved Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 49 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Table 8. DS90UB914Q-Q1 Control Registers (continued) ADDR (HEX) 0x12 NAME Slave Alias[2] BITS 7:1 0 0x13 Slave Alias[3] 7:1 0 0x14 Slave Alias[4] 7:1 0 0x15 Slave Alias[5] 7:1 0 0x16 Slave Alias[6] 7:1 0 0x17 Slave Alias[7] 7:1 0 0x18 50 Parity Errors Threshold 7:0 FIELD Slave Alias ID2 R/W RW DEFAULT DESCRIPTION 0x00 7-bit Remote Slave Device Alias ID 2 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote serializer. The transaction will be remapped to the address specified in the Slave ID2 register. A value of 0 in this field disables access to the remote I2C Slave. RSVD Reserved Slave Alias ID3 7-bit Remote Slave Device Alias ID 3 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote serializer. The transaction will be remapped to the address specified in the Slave ID3 register. A value of 0 in this field disables access to the remote I2C Slave. RW 0x00 RSVD Reserved Slave Alias ID4 7-bit Remote Slave Device Alias ID 4 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote serializer. The transaction will be remapped to the address specified in the Slave ID4 register. A value of 0 in this field disables access to the remote I2C Slave. RW 0x00 RSVD Reserved Slave Alias ID5 7-bit Remote Slave Device Alias ID 5 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote serializer. The transaction will be remapped to the address specified in the Slave ID5 register. A value of 0 in this field disables access to the remote I2C Slave. RW 0x00 RSVD Reserved Slave Alias ID6 7-bit Remote Slave Device Alias ID 6 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote serializer. The transaction will be remapped to the address specified in the Slave ID6 register. A value of 0 in this field disables access to the remote I2C Slave. RW 0x00 RSVD Reserved Slave Alias ID7 7-bit Remote Slave Device Alias ID 7 Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote serializer. The transaction will be remapped to the address specified in the Slave ID7 register. A value of 0 in this field disables access to the remote I2C Slave. RW 0x00 RSVD Reserved Parity Error Threshold Byte 0 Parity errors threshold on the Forward channel during normal information. This sets the maximum number of parity errors that can be counted using register 0x1A. Least significant Byte. Submit Documentation Feedback RW 0 Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Table 8. DS90UB914Q-Q1 Control Registers (continued) ADDR (HEX) NAME 0x19 Parity Errors Threshold 0x1A 0x1B 0x1C BITS FIELD R/W DEFAULT DESCRIPTION 7:0 Parity Error Threshold Byte 1 RW 0 Parity errors threshold on the Forward channel during normal operation. This sets the maximum number of parity errors that can be counted using register 0x1B. Most significant Byte Parity Errors 7:0 Parity Error Byte 0 RW 0 Number of parity errors in the Forward channel during normal operation. Least significant Byte Parity Errors 7:0 Parity Error Byte 1 RW 0 Number of parity errors in the Forward channel during normal operation Most significant Byte 7:4 Rev-ID R 0 Revision ID 0x0000: Production 3 RSVD 2 Parity Error R 1 Signal Detect R 0 Lock R 7 GPIO1 Output Vaue 6 RSVD Reserved 0 General Status 0 0 0 RW 0x1D 0x1D GPIO[1] and GPIO[0] Config 5 1: Serial input detected 0: Serial input not detected Deserializer CDR, PLL's clock to recovered clock frequency 1: Deserializer locked to recovered clock 0: Deserializer not locked Local GPIO Output Value This value is the output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output. Reserved GPIO1 Direction GPIO[1] and GPIO[0] Config Parity Error detected 1: Parity Errors detected 0: No Parity Errors 1 RW Local GPIO Direction 1: Input 0: Output 4 GPIO1 Enable RW 1 GPIO Function Enable 1: Enable GPIO operation 0: Enable normal operation 3 GPIO0 Output Value RW 0 Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output. 2 RSVD 1 GPIO0 Direction RW 1 Local GPIO Direction 1: Input 0: Output 0 GPIO0 Enable RW 1 GPIO Function Enable 1: Enable GPIO operation 0: Enable normal operation Copyright © 2012–2015, Texas Instruments Incorporated Reserved Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 51 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Table 8. DS90UB914Q-Q1 Control Registers (continued) ADDR (HEX) 0x1E 0x1F NAME BITS FIELD R/W DEFAULT DESCRIPTION 7 GPIO3 Output Vaue RW 0 Local GPIO Output Value This value is the output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output. 6 RSVD 5 GPIO3 Direction RW 1 Local GPIO Direction 1: Input 0: Output 4 GPIO3 Enable RW 1 GPIO Function Enable 1: Enable GPIO operation 0: Enable normal operation 3 GPIO2 Output Value RW 0 Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output. 2 RSVD 1 GPIO2 Direction RW 1 Local GPIO Direction 1: Input 0: Output 0 GPIO2 Enable RW 1 GPIO Function Enable 1: Enable GPIO operation 0: Enable normal operation GPIO[3] and GPIO[2] Config Mode and OSS Select 7 OEN_OSS Override RW 0 6 OEN Select RW 0 OEN configuration from register 5 OSS Select R 0 OSS_SEL configuration from register 4 MODE_OVERRIDE RW 0 Allows overriding mode select bits coming from back-channel 1: Overrides MODE select bits 0: Does not override MODE select bits 3 PIN_MODE_12–bit HF mode R 0 2 PIN_MODE_10-bit mode R 0 0 52 Reserved Allows overriding OEN and OSS select coming from Pins 1: Overrides OEN/OSS_SEL selected by pins 0: Does NOT override OEN/OSS_SEL select by pins 1 0x20 Reserved MODE_12–bit High Frequency MODE_10–bit mode 7:1 BCC Watchdog timer 0 BCC Watchdog Timer Disable RW RW RW Submit Documentation Feedback Status of mode select pin 0 Selects 12-bit high-frequency mode. This bit is automatically updated by the mode settings from RX unless MODE_OVERRIDE is SET 1: 12-bit high-frequency mode is selected. 0: 12-bit high-frequency mode is not selected. 0 Selects 10-bit mode. This bit is automatically updated by the mode settings from RX unless MODE_OVERRIDE is SET 1: Enables 10-bit mode. 0: Disables 10-bit mode. 0 The watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. This field sets the Bidirectional Control Channel Watchdog Timeout value in units of 2ms. This field should not be set to 0. 0 Disable Bidirectional Control Channel Watchdog Timer 1: Disables BCC Watchdog Timer operation 0: Enables BCC Watchdog Timer operation BCC Watchdog Control RW Status of mode select pin Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Table 8. DS90UB914Q-Q1 Control Registers (continued) ADDR (HEX) 0x21 NAME I2C Control 1 BITS FIELD R/W DEFAULT 7 I2C pass-through all RW 0 I2C Pass-Through All Transactions 0: Disabled 1: Enabled 6:4 I2C SDA Hold RW 0 Internal SDA Hold Time This field configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 50ns. 3:0 I2C Filter Depth RW 0 I2C Glitch Filter Depth This field configures the maximum width of glitch pulses on the SCL and SDA inputs that will be rejected. Units are 10ns. Control Channel Sequence Error Detected This bit indicates a sequence error has been detected in forward control channel. 1: If this bit is set, an error may have occurred in the control channel operation 0: No forward channel errors have been detected on the control channel 7 Forward Channel Sequence Error R 0 6 Clear Sequence Error RW 0 5 RSVD Reserved SDA Output Delay 0 SDA Output Delay This field configures output delay on the SDA output. Setting this value will increase output delay in units of 50 ns. Nominal output delay values for SCL to SDA are: 00 : 350ns 01: 400ns 10: 450ns 11: 500ns 0 Disable Remote Writes to local registers Setting this bit to a 1 will prevent remote writes to local device registers from across the control channel. This prevents writes to the deserializer registers from an I2C master attached to the serializer. Setting this bit does not affect remote access to I2C slaves at the deserializer. 0 Speed up I2C Bus Watchdog Timer 1: Watchdog Timer expires after approximately 50 µs 0: Watchdog Timer expires after approximately 1 s. Disable I2C Bus Watchdog Timer When the I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signaling occurs for approximately 1 second, the I2C bus will assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL 4:3 0x22 RW I2C Control 2 2 Local Write Disable RW 2 1 General-Purpose Control RW RW 0 7:0 GPCR RW 0 7:4 RSVD Reserved BIST Pin Configuration RW 1 Bist Configured through Pin. 1: Bist configured through pin. 0: Bist configured through register bit "reg_24[0]" BIST Clock Source RW 00 BIST Clock Source See Table 10 BIST Enable RW 0 BIST Control 1: Enabled 0: Disabled 3 0x24 I C Bus Timer Speed up Clears the Sequence Error Detect bit I2C Bus Timer Disable 0 0x23 DESCRIPTION BIST Control 2:1 0 Copyright © 2012–2015, Texas Instruments Incorporated Scratch Register Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 53 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Table 8. DS90UB914Q-Q1 Control Registers (continued) ADDR (HEX) NAME BITS 0x25 Parity Error Count 7:0 FIELD BIST Error Count R/W DEFAULT DESCRIPTION R 0 Number of Forward channel Parity errors in the BIST mode. 0x26 0x3B RESERVED 7:2 0x3C Oscillator output divider select 1:0 RSVD Reserved OSC OUT DIVIDER SEL Selects the divider for the OSC clock out on PCLK when system is not locked and selected by OEN/OSSSEL 0x02[5] 00: 50M (± 30%) 01: 25M (± 30%) 1X: 12.5M (± 30%) RW 0x3D 0x3E RESERVED 7:5 0x3F CML Output Enable 4 3:0 0x40 0x41 0x42 SCL High Time SCL Low Time 7:0 RSVD CML OUT Enable Reserved RW 0x4E 54 1 0: CML Loop-through Driver is powered up 1: CML Loop-through Driver is powered down. RSVD Reserved SCL High Time 0x82 I2C Master SCL High Time This field configures the high pulse width of the SCL output when the deserializer is the Master on the local I2C bus. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum (4μs + 0.3μs of rise time for cases where rise time is very fast) SCL high time with the internal oscillator clock running at 26MHz rather than the nominal 20MHz. 0x82 I2C SCL Low Time This field configures the low pulse width of the SCL output when the deserializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum (4.7µs + 0.3µs of fall time for cases where fall time is very fast) SCL low time with the internal oscillator clock running at 26MHz rather than the nominal 20MHz. 7:0 SCL Low Time 7:2 RSVD RW RW Reserved 1 Force Back Channel Error RW 0 1: This bit introduces multiple errors into Back channel frame. 0: No effect 0 Force One Back Channel Error RW 0 1: This bit introduces ONLY one error into Back channel frame. Self clearing bit 0: No effect CRC Force Error 0x43 0x4C 0x4D 0 RESERVED AEQ Test Mode Select EQ Value 7 RSVD 6 AEQ Bypass 5:0 RSVD 7:0 AEQ / Manual Eq Readback Submit Documentation Feedback Reserved RW 0 Bypass AEQ and use set manual EQ value using register 0x04 Reserved R 0 Read back the adaptive and manual Equalization value Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Table 9. Clock Sources for Forward Channel Frame on the Serializer During Normal Operation DS90UB913Q REG 0x14 [2:1] 10-BIT MODE 12-BIT HIGH-FREQUENCY MODE 12-BIT LOW-FREQUENCY MODE 00 50 MHz 37.5 MHz 25 MHz 01 100 MHz 75 MHz 50 MHz 10 50 MHz 37.5 MHz 25 MHz 11 25MHz 18.75 MHz 12.5 MHz Table 10. BIST Clock Sources DS90UB914Q REG 0x24 [2:1] 10-BIT MODE 12-BIT HIGH-FREQUENCY MODE 12-BIT LOW-FREQUENCY MODE 00 PCLK PCLK PCLK 01 100 MHz 75 MHz 50 MHz 10 50 MHz 37.5 MHz 25 MHz 11 25MHz 18.75 MHz 12.5 MHz Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 55 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com 11 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 11.1 Applications Information The serializer and deserializer support only AC-coupled interconnects through an integrated DC-balanced decoding scheme. External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in Figure 45. DOUT+ RIN+ DOUT- RIN- D R Figure 45. AC-Coupled Connection For high-speed FPD-Link III transmissions, the smallest available package should be used for the AC-coupling capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/Os require a 100-nF AC-coupling capacitors to the line. 11.2 Typical Application DS90UB913Q Serializer DS90UB914Q Deserializer FPD-Link III Camera Data DOUT+ 10 or 12 Image Sensor DATA HSYNC DIN[11:0] or DIN[9:0] HSYNC, VSYNC VSYNC Pixel Clock 4 PCLK DOUT- Camera Data 10 or 12 RIN+ RIN- ROUT[11:0] or ROUT[9:0] HSYNC, VSYNC Bi-Directional Control Channel PCLK GPO[3:0] GPIO[3:0] GPO[3:0] SDA Camera Unit SCL DATA HSYNC VSYNC Pixel Clock 4 GPIO[3:0] SDA SDA SCL SCL ECU Module Microcontroller SDA SCL Figure 46. Application Block Diagram 11.2.1 Design Requirements 11.2.1.1 Transmission Media The DS90UB91xQ-Q1 chipset is intended to be used in a point-to-point configuration through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize impedance discontinuities. The interconnect (cable and connectors) should have a differential impedance of 100 Ω. The maximum length of cable that can be used is dependent on the quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical environment (for example, power stability, ground noise, input clock jitter, PCLK frequency, and so forth). The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the differential eye opening of the serial data stream. A differential probe should be used to measure across the termination resistor at the CMLOUTP/N pins. Figure 20 illustrates the minimum eye width and eye height that is necessary for bit error free operation. 56 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Typical Application (continued) 11.2.1.2 Adaptive Equalizer – Loss Compensation The adaptive equalizer is designed to compensate for signal degradation due to the differential insertion loss of the interconnect components. There are limits to the amount of loss that can be compensated – these limits are defined by the gain curve of the equalizer. In addition, there is an inherent tolerance for loss defined by the delta between the minimum VDO of the serializer and the input threshold (Vswing) of the deserializer. In order to determine the maximum cable reach, other factors that affect signal integrity such as jitter, skew, ISI, crosstalk, and so forth, need to be taken into consideration. Figure 49 illustrates the maximum allowable interconnect loss with the adaptive equalizer at its maximum gain setting (914 equalizer gain). 11.2.2 Detailed Design Procedure Figure 47 shows the typical connection of a DS90UB913Q-Q1 serializer. DS90UB913Q (SER) VDDIO VDDIO C3 1.8V VDDT C4 C8 C9 C13 1.8V DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 DIN10 DIN11 HS VS PCLK LVCMOS Parallel Bus 1.8V VDDPLL C5 C14 C10 FB1 1.8V VDDCML C6 C11 C15 C7 C12 FB2 1.8V VDDD C1 Serial FPD-Link III Interface DOUT+ DOUTC2 10 k: MODE 1.8V RID 10 k: LVCMOS Control Interface ID[X] RID PDB GPO[0] GPO[1] GPO[2] GPO[3] GPO Control Interface VDDIO RPU I2C Bus Interface RPU SCL FB3 SDA FB4 C16 Optional Optional C17 RES DAP (GND) NOTE: C1 - C2 = 0.1 PF (50 WV) C3 ± C7 = 0.01 PF C8 - C12 = 0.1 PF C13 - C14 = 4.7 PF C15 = 22 PF C16 - C17 = >100 pF RPU = 1 k: to 4.7 k: RID (see ID[x] Resistor Value Table) FB1 - FB4: Impedance = 1 k: (@ 100 MHz) low DC resistance (<1:) The "Optional" components shown are provisions to provide higher system noise immunity and will therefore result in higher performance. Figure 47. DS90UB913Q-Q1 Typical Connection Diagram — Pin Control Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 57 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Typical Application (continued) Figure 48 shows a typical connection of the DS90UB914Q-Q1 deserializer. DS90UB914Q (Des) 1.8V VDDD C3 C11 C4 C12 C5 C13 VDDIO VDDIO1 C8 VDDR C16 C18 VDDIO2 C9 VDDSSCG VDDIO3 C10 1.8V VDDPLL FB1 C6 C14 C17 FB2 C7 C15 C19 1.8V VDDCML C1 RIN1+ Serial FPD-Link II Interface RIN1- C2 RIN0+ C1 RIN0- C2 1.8V GPIO[0] GPIO[1] GPIO[2] GPIO[3] MODE 10 k: RMODE ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 ROUT6 LVCMOS Parallel Outputs ROUT7 ROUT8 ROUT9 ROUT10 ROUT11 HS VS PCLK LOCK PASS 1.8V 10 k: IDx[0] RID0 PDB SEL OEN OSS_SEL BISTEN 1.8V VDDIO 10 k: IDx[1] RPU I2C Bus Interface RPU RID1 SCL FB3 SDA FB4 C20 C21 Optional Optional RES_PIN43 DAP (GND) NOTE: C1 - C2 = 0.1 PF (50 WV) C3 - C10 = 0.01 PF C11 - C16 = 0.1 PF C17 - C18 = 4.7 PF C19 = 22 PF C20 - C21 = >100 pF RPU = 1 k: to 4.7 k: RID (see ID[x] Resistor Value Table) FB1 - FB4: Impedance = 1 k: (@ 100 MHz) low DC resistance (<1:) The "Optional" components shown are provisions to provide higher system noise immunity and will therefore result in higher performance. Figure 48. DS90UB914Q-Q1 Typical Connection Diagram — Pin Control 58 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Typical Application (continued) 11.2.3 Application Curve 25 EFFECTIVE GAIN (dB) 20 15 914 Equalizer Gain (dB) VOD-Vswing Loss 10 Allowable Interconnect Loss 5 0 100 200 300 400 500 600 700 SERIAL LINE FREQUENCY (MHz) Figure 49. Adaptive Equalizer – Interconnect Loss Compensation Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 59 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com 12 Power Supply Recommendations This device is designed to operate from an input core voltage supply of 1.8 V. Some devices provide separate power and ground terminals for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal description tables typically provide guidance on which circuit blocks are connected to which power terminal pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs. 13 Layout 13.1 Layout Guidelines Printed-circuit-board layout and stack-up for the serializer and deserializer devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power/ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range. Voltage rating of the tantalum capacitors should be at least 5× the power supply voltage being used. Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50-µF to 100-µF range and will smooth low frequency switching noise. It is recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with a via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path. A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. Use at least a four-layer board with a power and ground plane. Locate LVCMOS signals away from the differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential lines of 100 Ω are typically recommended for differential interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less. Information on the WQFN style package is provided in Texas Instruments' Application Note: AN-1187 (SNOA401). See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details. • Use 100-Ω coupled differential pairs • Use the S, 2S, and 3S rule in spacings – S = space between the pair – 2S = space between pairs – 3S = space to LVCMOS signal • Minimize the number of Vias • Use differential connectors when operating above 500Mbps line speed • Maintain balance of the traces • Minimize skew within the pair 60 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 Layout Guidelines (continued) Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas Instrument web site at: www.ti.com/lvds 13.2 Layout Example Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Figure 50. Figure 50. No Pullback WQFN, Single Row Reference Diagram Figure 50 and Figure 51 PCB layout examples are derived from the layout design of the DS90UB913Q-Q1 Serializer and DS90UB914Q-Q1 Deserializer Evaluation Kit (SNLU110). These graphics and additional layout description are used to demonstrate both proper routing and proper solder techniques when designing in the serializer and deserializer. Table 11. No Pullback WQFN Stencil Aperture Summary for DS90UB913Q-Q1 and DS90UB914Q-Q1 MKT DWG PCB I/O PAD SIZE (mm) PCB PITCH (mm) PCB DAP SIZE (mm) STENCIL I/O APERTURE (mm) STENCIL DAP APERTURE (mm) NUMBER OF DAP APERTURE OPENINGS GAP BETWEEN DAP APERTURE (Dim A mm) 32 RTV 0.25 x 0.6 0.5 3.1 x 3.1 0.25 x 0.7 1.4 x 1.4 4 0.2 48 RHS 0.25 x 0.6 0.5 5.1 x 5.1 0.25 x 0.7 1.1 x 1.1 16 0.2 DEVICE PIN COUNT DS90UB913Q-Q1 DS90UB914Q-Q1 Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 61 DS90UB913Q-Q1, DS90UB914Q-Q1 SNLS420D – JULY 2012 – REVISED JULY 2015 www.ti.com Figure 51. 48-Pin WQFN Stencil Example of Via and Opening Placement 62 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 DS90UB913Q-Q1, DS90UB914Q-Q1 www.ti.com SNLS420D – JULY 2012 – REVISED JULY 2015 14 Device and Documentation Support 14.1 Documentation Support 14.1.1 Related Documentation For related documentation, see the following: • Absolute Maximum Ratings for Soldering, SNOA549 • AN-1187 Leadless Leadframe Package (LLP), SN0A401 • AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines, SNLA008 • Transmission Line RAPIDESIGNER Operation and Applications Guide, SNLA035 • DS90UB913Q-Q1 Serializer and DS90UB914Q-Q1 Deserializer Evaluation Kit, SNLU110 14.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 12. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY DS90UB913Q-Q1 Click here Click here Click here Click here Click here DS90UB914Q-Q1 Click here Click here Click here Click here Click here 14.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 14.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 14.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 14.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 15 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1 63 PACKAGE OPTION ADDENDUM www.ti.com 11-Jul-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DS90UB913QSQ/NOPB ACTIVE WQFN RTV 32 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB913SQ DS90UB913QSQE/NOPB ACTIVE WQFN RTV 32 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB913SQ DS90UB913QSQX/NOPB ACTIVE WQFN RTV 32 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB913SQ DS90UB914QSQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB914QSQ DS90UB914QSQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB914QSQ DS90UB914QSQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 UB914QSQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Jul-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS90UB913QSQ/NOPB WQFN RTV 32 DS90UB913QSQE/NOPB WQFN RTV DS90UB913QSQX/NOPB WQFN RTV DS90UB914QSQ/NOPB WQFN DS90UB914QSQE/NOPB DS90UB914QSQX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90UB913QSQ/NOPB WQFN RTV 32 1000 213.0 191.0 55.0 DS90UB913QSQE/NOPB WQFN RTV 32 250 213.0 191.0 55.0 DS90UB913QSQX/NOPB WQFN RTV 32 4500 367.0 367.0 35.0 DS90UB914QSQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS90UB914QSQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS90UB914QSQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.com MECHANICAL DATA RTV0032A SQA32A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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