TC1320 8-Bit Digital-to-Analog Converter with Two-Wire Interface Features General Description • • • • • • • The TC1320 is a serially accessible 8-bit voltage output digital-to-analog converter (DAC). The DAC produces an output voltage that ranges from ground to an externally supplied reference voltage. It operates from a single power supply that can range from 2.7V to 5.5V, making it ideal for a wide range of applications. Built into the part is a Power-on Reset function that ensures that the device starts at a known condition. 8-bit Digital-to-Analog Converter ±2 LSB INL ±0.8 LSB DNL 2.7-5.5V Single Supply Operation Simple SMBus/I2CTM Serial Interface Low Power: 350µA Operation, 0.5µA Shutdown 8-Pin SOIC and 8-Pin MSOP Packages Communication with the TC1320 is accomplished via a simple 2-wire SMBus/I2C™ compatible serial port with the TC1320 acting as a slave only device. The host can enable the SHDN bit in the CONFIG register to activate the Low Power Standby mode. Applications • Programmable Voltage Sources • Digital Controlled Amplifiers/Attenuators • Process Monitoring and Control Package Type Device Selection Table Part Number Package Temperature Range TC1320EOA 8-Pin SOIC (Narrow) -40°C to +85°C TC1320EUA 8-Pin MSOP -40°C to +85°C 8-Pin MSOP and 8-Pin SOIC (Narrow) VREF 1 8 VDD SDA 2 7 DAC-OUT 6 NC 5 VOUT SCL 3 TC1320 GND 4 Typical Application VIN (8) VDD TC1320 – VREF (1) DAC VOUT (5) + VADJUST Serial Port (2) (2) (3) SCLK SDAT Microcontroller 2002 Microchip Technology Inc. DS21386B-page 1 TC1320 Functional Block Diagram VDD TC1320 Configuration Register SDA SCL Serial Port Interface Data Register Control DAC-OUT VREF DS21386B-page 2 VOUT DAC GND 2002 Microchip Technology Inc. TC1320 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings* Supply Voltage (V DD) ............................................. +6V Voltage on any Pin .. (GND – 0.3V) to (VDD + 0.3V) Current on any Pin ............................................ ±50mA Package Thermal Resistance (θJA)............ 330°C C/W Operating Temperature (TA)........................ See Below Storage Temperature (TSTG) .............. -65°C to +150°C *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TC1320 ELECTRICAL SPECIFICATIONS Electrical Characteristics: VDD = 2.7V to 5.5V, -40°C ≤ TA ≤ +85°C, VREF = 1.2V unless otherwise noted. Symbol Parameter Min Typ Max Unit Test Conditions Power Supply VDD Supply Voltage 2.7 350 500 µA IDD Operating Current — 0.35 0.5 mA VDD = 5.5V, VREF = 1.2V Serial Port Inactive (Note 1) IDD-STANDBY Standby Supply Current — 0.1 1 µA VDD = 3.3V Serial Port Inactive (Note 1) — — 8 Bits Static Performance - Analog Section Resolution INL Integral Non-Linearity at FS, TA = +25°C — — ±2 LSB FSE Full Scale Error — — ±3 %FS (Note 2) DNL Differential Non-Linearity, TA = +25°C — — ±0.8 LSB All Codes (Note 2) VOS Offset Error at VOUT — ±0.3 ±8 mV (Note 2) TCV OS Offset Error Tempco at VOUT — 10 — µv/°C PSRR Power Supply Rejection Ratio — 80 — dB VREF Voltage Reference Range 0 — VDD – 1.2 V IREF Reference Input Leakage Current — — ±1.0 µA VDD at DC VSW Voltage Swing 0 — VREF V VREF ≤ (VDD – 1.2V) ROUT Output Resistance @ VOUT — 5 — Ω ROUT (Ω) IOUT Output Current (Source or Sink) — 2 — mA ISC Output Short-Circuit Current VDD = 5.5V — — 30 20 50 50 mA mA Source Sink Dynamic Performance SR Voltage Output Slew Rate — 0.8 — V/µs tSETTLE Output Voltage Full Scale Settling Time — 10 — µsec tWU Wake-up Time — 20 — µs Digital Feed Through and Crosstalk — 5 — nV-s SDA = VDD , SCL = 100kHz Serial Port Interface VIH Logic Input High 2.4 — VDD V VIL Logic Input Low — — 0.6 — VOL SDA Output Low — — — — 0.4 0.6 V V CIN Input Capacitance SDA, SCL — 5 0.4 pF ILEAK I/O Leakage — — ±1.0 µA IOL = 3mA (Sinking Current) IOL = 6mA Note 1: SDA and SCL must be connected to VDD or GND. 2: Measured at VOUT ≥ 50mV referred to GND to avoid output buffer clipping. 2002 Microchip Technology Inc. DS21386B-page 3 TC1320 TC1320 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: VDD = 2.7V to 5.5V, -40°C ≤ TA ≤ +85°C, VREF = 1.2V unless otherwise noted. Symbol Parameter Min Typ Max Unit Test Conditions Serial Port AC Timing fSMB SMBus Clock Frequency 10 — 100 kHz tIDLE Bus Free Time Prior to New Transition 4.7 — — µsec tH(START) START Condition Hold Time 4.0 — — µsec tSU(START) START Condition Setup Time 4.7 — — µsec tSU(STOP) STOP Condition Setup Time 4.0 — — µsec tH-DATA Data In Hold Time 100 — — nsec tSU-DATA Data In Setup Time 100 — — nsec tLOW Low Clock Period 4.7 — — µsec tHIGH High Clock Period 4 — — µsec 90% to 90% tF SMBus Fall Time — — 300 nsec 90% to 10% tR SMBus Rise Time — — 1000 nsec 10% to 90% tPOR Power-on Reset Delay — 500 — µsec VDD ≥ VPOR (Rising Edge) 90% SCL to 10% SDA (for Repeated START Condition) 10% to 10% Note 1: SDA and SCL must be connected to VDD or GND. 2: Measured at VOUT ≥ 50mV referred to GND to avoid output buffer clipping. DS21386B-page 4 2002 Microchip Technology Inc. TC1320 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number Symbol Type 1 VREF Input 2 SDA Bi-Directional Description Input. Voltage Reference Input can range from 0V to 1.2V below VDD. Bi-directional. Serial data is transferred on the SMBus in both directions using this pin. 3 SCL Input 4 GND Power Ground. Input. SMBus serial clock. Clocks data into and out of the TC1320. 5 VOUT Output Output. Buffered DAC output voltage. This voltage is a function of the reference voltage and the contents of the DATA register. 6 NC None 7 DAC-OUT Output Output. Unbuffered DAC output voltage. This voltage is a function of the reference voltage and the contents of the DATA register. This output is unbuffered and care must be taken that the pin is connected only to a high-impedance node. 8 VDD Power Positive power supply input. See electrical specifications. 2002 Microchip Technology Inc. No connection. DS21386B-page 5 TC1320 3.0 DETAILED DESCRIPTION 3.2 Output Amplifier The TC1320 is a monolithic 8-bit digital-to-analog converter, that is designed to operate from a single supply that can range from 2.7V to 5.5V. The DAC consists of a data register (DATA), a configuration register (CONF), and a current output amplifier. The TC1320 uses an external reference, which also determines the maximum output voltage. The TC1320 DAC output is buffered with an internal unity gain rail-to-rail input/output amplifier, with a typical slew rate of 0.8V/µsec. Maximum full scale transition settling time is 10µsec to within ±1/2LSB when loaded with 1kΩ in parallel with 100pF. The TC1320 uses a current steering DAC, based on an array of matched current sources. This current, along a precision resistor, converts the contents of the Data Register and V REF into an output voltage, VOUT given by: The TC1320 allows the host to put it into a Low Power (IDD = 0.5µA, typical) Standby mode. In this mode, the D/A conversion is halted. The SMBus port operates normally. Standby mode is enabled by setting the SHDN bit in the CONFIG register. The table below summarizes this operation. 3.3 VOUT = VREF (DATA/256) 3.1 Standby Mode TABLE 3-1: Reference Input The reference pin, V REF, is a buffered high-impedance input and because of this, the load regulation of the reference source needs only to be able to tolerate leakage levels of current (less than 1µA). VREF accepts a voltage range from 0 to (VDD – 1.2V). Input capacitance is typically 10pF. STANDBY MODE OPERATION SHDN Bit Operating Mode 0 Normal 1 Standby 3.4 SMBus Slave Address The TC1320 is internally programmed to have a default SMBus address value of 1001 000b. Seven other addresses are available by custom order (contact factory). See Figure 3-1 for locating address bits in SMBus protocol. FIGURE 3-1: SMBus PROTOCOLS Write 1-Byte Format S Address R/W 0 7-Bits Command ACK Data ACK 8-Bits Slave Address ACK P 8-Bits Data Byte: data goes into the register set by the command byte. Command Byte: selects which register you are writing to. Read 1-Byte Format Address S 7-Bits R/W ACK Command 0 S ACK Address 8-Bits Slave Address 7-Bits Command Byte: selects which register you are reading from. R/W ACK 1 Slave Address: repeated due to change in data flow direction. Data NACK P 8-Bits Data Byte: reads from the register set by the command byte. Receive 1-Byte Format S Address 7-Bits R/W ACK 1 S = START Condition P = STOP Condition Shaded = Slave Transmission DS21386B-page 6 Data NACK P 8-Bits Data Byte: reads data from the register commanded by the last Read Byte or Write Byte transmission. 2002 Microchip Technology Inc. TC1320 4.0 SERIAL PORT OPERATION 4.1 START Condition (START) The Serial Clock input (SCL) and bi-directional data port (SDA) form a 2-wire bi-directional serial port for programming and interrogating the TC1320. The following conventions are used in this bus architecture: The TC1320 continuously monitors the SDA and SCL lines for a START condition (a HIGH to LOW transition of SDA while SCL is HIGH), and will not respond until this condition is met. TABLE 4-1: 4.2 Term TC1320 SERIAL BUS CONVENTIONS Explanation Transmitter The device sending data to the bus. Receiver The device receiving data from the bus. Master The device which controls the bus: initiating transfers (START), generating the clock, and terminating transfers (STOP). Slave The device addressed by the master. START A unique condition signaling the beginning of a transfer indicated by SDA falling (High - Low) while SCL is high. STOP A unique condition signaling the end of a transfer indicated by SDA rising (Low - High) while SCL is high. ACK A Receiver Acknowledges the receipt of each byte with this unique condition. The Receiver drives SDA low during SCL high of the ACK clock pulse. The Master provides the clock pulse for the ACK cycle. Busy Communication is not possible because the bus is in use. Not Busy When the bus is IDLE, both SDA and SCL will remain high. Data Valid The state of SDA must remain stable during the High period of SCL in order for a data bit to be considered valid. SDA only changes state while SCL is low during normal data transfers. (See START and STOP conditions.) All transfers take place under control of a host, usually a CPU or microcontroller, acting as the Master, which provides the clock signal for all transfers. The TC1320 always operates as a Slave. The serial protocol is illustrated in Figure 3-1. All data transfers have two phases; all bytes are transferred MSB first. Accesses are initiated by a START condition (START), followed by a device address byte and one or more data bytes. The device address byte includes a Read/Write selection bit. Each access must be terminated by a STOP Condition (STOP). A convention called Acknowledge (ACK) confirms receipt of each byte. Note that SDA can change only during periods when SCL is LOW (SDA changes while SCL is HIGH is reserved for START and STOP Conditions). 2002 Microchip Technology Inc. Address Byte Immediately following the START Condition, the host must transmit the address byte to the TC1320. The 7-bit SMBus address for the TC1320 is 1001000. The 7-bit address transmitted in the serial bit stream must match for the TC1320 to respond with an Acknowledge (indicating the TC1320 is on the bus and ready to accept data). The eighth bit in the Address Byte is a Read/Write bit. This bit is a 1 for a read operation, or 0 for a write operation. During the first phase of any transfer, this bit will be set = 0 to indicate that the command byte is being written. 4.3 Acknowledge (ACK) Acknowledge (ACK) provides a positive handshake between the host and the TC1320. The host releases SDA after transmitting eight bits, then generates a ninth clock cycle to allow the TC1320 to pull the SDA line LOW to Acknowledge that it successfully received the previous eight bits of data or address. 4.4 Data Byte After a successful ACK of the address byte, the host must transmit the data byte to be written, or clock out the data to be read. (See the appropriate timing diagrams.) ACK will be generated after a successful write of a data byte into the TC1320. 4.5 STOP Condition (STOP) Communications must be terminated by a STOP condition (a LOW to HIGH transition of SDA while SCL is HIGH). The STOP Condition must be communicated by the transmitter to the TC1320. Refer to Figure 4-1, Timing Diagrams for serial bus timing. DS21386B-page 7 TC1320 FIGURE 4-1: TIMING DIAGRAMS SMBus Write Timing Diagram A B ILOW IHIGH C D E F G H I K J SCL SDA tSU(START) tH(START) tSU(STOP) tSU-DATA A = START Condition B = MSB of Address Clocked into Slave C = LSB of Address Clocked into Slave D = R/W Bit Clocked into Slave tIDLE I = Acknowledge Clock Pulse E = Slave Pulls SDA Line Low F = Acknowledge Bit Clocked into Master J = STOP Condition K = New START Condition G = MSB of Data Clocked into Master H = LSB of Data Clocked into Master SMBUS Read Timing Diagram A B ILOW IHIGH C D E F G H I J K M L SCL SDA tSU(START) tH(START) tSU-DATA A = START Condition B = MSB of Address Clocked into Slave C = LSB of Address Clocked into Slave D = R/W Bit Clocked into Slave E = Slave Pulls SDA Line Low 4.6 Register Set and Programmer’s Model TABLE 4-2: TC1320 COMMAND SET (SMBus READ_BYTE AND WRITE_BYTE) Command Byte Description Command Code Function RWD 00h Read/Write Data (DATA) RWCR 01h Read/Write Configuration (CONFIG) DS21386B-page 8 tH-DATA F = Acknowledge Bit Clocked into Master G = MSB of Data Clocked into Slave H = LSB of Data Clocked into Slave I = Slave Pulls SDA Line Low tSU(STOP) tIDLE J = Acknowledge Clocked into Master K = Acknowledge Clock Pulse L = STOP Condition, Data Executed by Slave M = New START Condition TABLE 4-3: CONFIGURATION REGISTER (CONFIG), 8-BIT, READ/WRITE Configuration Register (CONFIG) D[7] D[6] D[5] D[4] D[3] Bit POR D[0] 0 Standby Switch D[7]-D[1] 0 Reserved; Always returns Zero when Read D[2] Reserved Function D[1] D[0] SHDN Type Operation Read/ 1 = Standby Write 0 = Normal N/A N/A 2002 Microchip Technology Inc. TC1320 TABLE 4-4: DATA REGISTER (DATA), 8-BIT, READ/WRITE 4.7 The TC1320’s register set is summarized in Table 4-5 below. All registers are 8-bits wide. Data Register (DATA) D[7] D[6] D[5] D[4] D[3] D[2] D[1] MSB X X X X X X Register Set Summary D[0] TABLE 4-5: LSB The DAC output voltage is a function of reference voltage and the binary value of the contents of the Data register. The transfer function is given by the expression: Name Data Config TC1320 REGISTER SET SUMMARY Description POR State Read Write 0000 0000b X X CONFIG Register 0000 0000b X X Data Register EQUATION 4-1: V OUT = V REF DATA x ----------------256 2002 Microchip Technology Inc. DS21386B-page 9 TC1320 5.0 PACKAGING INFORMATION 5.1 Package Marking Information Package marking data not available at this time. 5.2 Taping Forms Component Taping Orientation for 8-Pin MSOP Devices User Direction of Feed PIN 1 W P Standard Reel Component Orientation for TR Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package 8-Pin MSOP Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 12 mm 8 mm 2500 13 in Component Taping Orientation for 8-Pin SOIC (Narrow) Devices User Direction of Feed PIN 1 W P Standard Reel Component Orientation for TR Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package 8-Pin SOIC (N) DS21386B-page 10 Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 12 mm 8 mm 2500 13 in 2002 Microchip Technology Inc. TC1320 5.3 Package Dimensions 8-Pin MSOP PIN 1 .122 (3.10) .114 (2.90) .197 (5.00) .189 (4.80) .026 (0.65) TYP. .122 (3.10) .114 (2.90) .043 (1.10) MAX. .016 (0.40) .010 (0.25) .008 (0.20) .005 (0.13) 6° MAX. .006 (0.15) .002 (0.05) .028 (0.70) .016 (0.40) Dimensions: inches (mm) 8-Pin SOIC PIN 1 .157 (3.99) .150 (3.81) .244 (6.20) .228 (5.79) .050 (1.27) TYP. .197 (5.00) .189 (4.80) .069 (1.75) .053 (1.35) .020 (0.51) .010 (0.25) .013 (0.33) .004 (0.10) .010 (0.25) .007 (0.18) 8° MAX.. .050 (1.27) .016 (0.40) Dimensions: inches (mm) 2002 Microchip Technology Inc. DS21386B-page 11 TC1320 SALES AND SUPPORT Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. DS21386B-page 12 2002 Microchip Technology Inc. TC1320 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro ® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 03/01/02 *DS21386B* DS21386B-page 14 2002 Microchip Technology Inc.