24LC04B/08B 4K/8K 2.5V I2C™ Serial EEPROMs FEATURES PDIP 8-lead SOIC 1 A1 2 A2 3 VSS 4 A0 1 A1 2 A2 3 VSS 8 VCC 7 WP 6 SCL 5 SDA VCC 7 WP 6 SCL 4 5 SDA NC 1 14 NC A0 2 13 VCC A1 3 12 WP 11 NC 10 SCL 24LC04B/08B 8 14-lead SOIC 24LC04B/08B DESCRIPTION The Microchip Technology Inc. 24LC04B/08B is a 4K or 8K bit Electrically Erasable PROM. The device is organized as two or four blocks of 256 x 8-bit memory with a 2-wire serial interface. Low voltage design permits operation down to 2.5 volts with typical standby and active currents of only 5 µA and 1 mA respectively. The 24LC04B/08B also has a page-write capability for up to 16 bytes of data. The 24LC04B/08B is available in the standard 8-pin DIP and both 8-lead and 14-lead surface mount SOIC packages. A0 24LC04B/08B • Single supply with operation down to 2.5V • Low power CMOS technology - 1 mA active current typical - 10 µA standby current typical at 5.5V - 5 µA standby current typical at 3.0V • Organized as two or four blocks of 256 bytes (2 x 256 x 8) and (4 x 256 x 8) • 2-wire serial interface bus, I2C compatible • Schmitt trigger, filtered inputs for noise suppression • Output slope control to eliminate ground bounce • 100 kHz (2.5V) and 400 kHz (5V) compatibility • Self-timed write cycle (including auto-erase) • Page-write buffer for up to 16 bytes • 2 ms typical write cycle time for page-write • Hardware write protect for entire memory • Can be operated as a serial ROM • Factory programming (QTP) available • ESD protection > 4,000V • 1,000,000 erase/write cycles guaranteed • Data retention > 200 years • 8-pin DIP, 8-lead or 14-lead SOIC packages • Available temperature ranges: - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C PACKAGE TYPES NC 4 A2 5 VSS 6 9 SDA NC 7 8 NC BLOCK DIAGRAM I/O CONTROL LOGIC WP HV GENERATOR MEMORY CONTROL LOGIC EEPROM ARRAY (2 x 256 x 8) or (4 X 256 X 8) XDEC PAGE LATCHES SDA SCL YDEC VCC V SS SENSE AMP R/W CONTROL I2C is a trademark of Philips Corporation. 1999 Microchip Technology Inc. DS21051G-page 1 24LC04B/08B 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* TABLE 1-1: Name Function VSS SDA SCL WP VCC A0, A1, A2 VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ...............-0.3V to VCC + 1.0V Storage temperature ..................................... -65˚C to +150˚C Ambient temp. with power applied................. -65˚C to +125˚C Soldering temperature of leads (10 seconds) ............. +300˚C ESD protection on all pins ..................................................≥ 4 kV *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: PIN FUNCTION TABLE Ground Serial Address/Data I/O Serial Clock Write Protect Input +2.5V to 5.5V Power Supply No Internal Connection DC CHARACTERISTICS VCC = +2.5V to +5.5V Commercial (C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C Parameter WP, SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmitt trigger Inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Symbol Min Max Units VIH VIL VHYS .7 VCC — .05 VCC — .3 VCC — V V V VOL ILI ILO CIN, COUT — -10 -10 — .40 10 10 10 V µA µA pF ICC WRITE ICC READ ICCS — — — — 3 1 30 100 mA mA µA µA (Note) IOL = 3.0mA, VCC = 2.5V VIN = .1V to VCC VOUT = .1V to VCC VCC = 5.0V (Note) Tamb = 25˚C, Fclk = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC WP = VSS Note: This parameter is periodically sampled and not 100% tested. FIGURE 1-1: BUS TIMING START/STOP VHYS SCL THD:STA TSU:STA TSU:STO SDA START DS21051G-page 2 STOP 1999 Microchip Technology Inc. 24LC04B/08B TABLE 1-3: AC CHARACTERISTICS Parameter STANDARD MODE Symbol VCC = 4.5 - 5.5V FAST MODE Min Max Min Max Units Remarks Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time FCLK THIGH TLOW TR TF THD:STA — 4000 4700 — — 4000 100 — — 1000 300 — — 600 1300 — — 600 400 — — 300 300 — kHz ns ns ns ns ns START condition setup time TSU:STA 4700 — 600 — ns Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time THD:DAT TSU:DAT TSU:STO TAA TBUF 0 250 4000 — 4700 — — — 3500 — 0 100 600 — 1300 — — — 900 — ns ns ns ns ns TOF — 250 250 ns (Note 1), CB ≤ 100 pF TSP — 50 20 +0.1 CB — 50 ns (Note 3) TWR — 10 — 10 ms — 1M — 1M — Output fall time from VIH min to VIL max Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2) Time the bus must be free before a new transmission can start Byte or Page mode cycles 25°C, Vcc = 5.0V, Block Mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model whcih can be obtained on our website. FIGURE 1-2: BUS TIMING DATA TR TF THIGH TLOW SCL TSU:STA THD:DAT TSU:DAT TSU:STO THD:STA SDA IN TSP TAA THD:STA TAA TBUF SDA OUT 1999 Microchip Technology Inc. DS21051G-page 3 24LC04B/08B 2.0 FUNCTIONAL DESCRIPTION The 24LC04B/08B supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24LC04B/08B works as slave. Both, master and slave can operate as transmitter or receiver but the master device determines which mode is activated. 3.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1). 3.1 3.4 The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last 16 will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion. 3.5 Both data and clock lines remain HIGH. 3.2 Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 3.3 Stop Data Transfer (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. FIGURE 3-1: Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: Bus not Busy (A) Data Valid (D) The 24LC04B/08B does not generate any acknowledge bits if an internal programming cycle is in progress. The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) START CONDITION ADDRESS OR ACKNOWLEDGE VALID (D) (C) (A) SCL SDA DS21051G-page 4 DATA ALLOWED TO CHANGE STOP CONDITION 1999 Microchip Technology Inc. 24LC04B/08B 3.6 Device Addressing FIGURE 3-2: A control byte is the first byte received following the start condition from the master device. The control byte consists of a 4-bit control code, for the 24LC04B/08B this is set as 1010 binary for read and write operations. The next three bits of the control byte are the block select bits (B2, B1, B0). B2 is a don't care for both the 24LC04B and 24LC08B; B1 is a don't care for the 24LC04B. They are used by the master device to select which of the two or four 256 word blocks of memory are to be accessed. These bits are in effect the most significant bits of the word address. CONTROL BYTE ALLOCATION START READ/WRITE SLAVE ADDRESS 1 0 1 0 X R/W A B1 B0 X = Don’t care. B1 is don’t care for 24LC04B. The last bit of the control byte defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected. Following the start condition, the 24LC04B/08B monitors the SDA bus checking the device type identifier being transmitted, upon a 1010 code the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24LC04B/ 08B will select a read or write operation. Operation Control Code Block Select R/W Read Write 1010 1010 Block Address Block Address 1 0 1999 Microchip Technology Inc. DS21051G-page 5 24LC04B/08B 4.0 WRITE OPERATION 4.1 Byte Write after the master has transmitted a stop condition. After the receipt of each word, the four lower order address pointer bits are internally incremented by one. The higher order seven bits of the word address remains constant. If the master should transmit more than 16 words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 4-2). Following the start condition from the master, the device code (4 bits), the block address (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24LC04B/08B. After receiving another acknowledge signal from the 24LC04B/08B the master device will transmit the data word to be written into the addressed memory location. The 24LC04B/08B acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24LC04B/08B will not generate acknowledge signals (Figure 4-1). 4.2 Note: Page Write The write control byte, word address and the first data byte are transmitted to the 24LC04B/08B in the same way as in a byte write. But instead of generating a stop condition the master transmits up to 16 data bytes to the 24LC04B/08B which are temporarily stored in the on-chip page buffer and will be written into the memory FIGURE 4-1: BYTE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE S CONTROL BYTE WORD ADDRESS PAGE WRITE S T A R T SDA LINE S DS21051G-page 6 A C K A C K A C K BUS ACTIVITY MASTER BUS ACTIVITY S T O P DATA P BUS ACTIVITY FIGURE 4-2: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or Ôpage sizeÕ) and end at addresses that are integer multiples of [page size - 1]. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. CONTROL BYTE WORD ADDRESS (n) DATA n S T O P DATA n + 15 DATA n + 1 P A C K A C K A C K A C K A C K 1999 Microchip Technology Inc. 24LC04B/08B 5.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for flow diagram. FIGURE 5-1: ACKNOWLEDGE POLLING FLOW Send Write Command 7.0 Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 7.1 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LC04B/08B as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24LC04B/ 08B will then issue an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC04B/08B discontinues transmission (Figure 7-2). Send Start Send Control Byte with R/W = 0 7.3 NO YES Next Operation 6.0 Current Address Read The 24LC04B/08B contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24LC04B/08B issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC04B/08B discontinues transmission (Figure 7-1). 7.2 Send Stop Condition to Initiate Write Cycle Did Device Acknowledge (ACK = 0)? READ OPERATION WRITE PROTECTION The 24LC04B/08B can be used as a serial ROM when the WP pin is connected to VCC. Programming will be inhibited and the entire memory will be write-protected. Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24LC04B/08B transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24LC04B/08B to transmit the next sequentially addressed 8-bit word (Figure 7-3). To provide sequential reads the 24LC04B/08B contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. 7.4 Noise Protection The 24LC04B/08B employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. 1999 Microchip Technology Inc. DS21051G-page 7 24LC04B/08B FIGURE 7-1: CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T SDA LINE S CONTROL BYTE S T O P DATA n P A C K BUS ACTIVITY N O A C K FIGURE 7-2: RANDOM READ BUS ACTIVITY MASTER S T A R T CONTROL BYTE S T A R T WORD ADDRESS (n) S DATA (n) P A C K A C K BUS ACTIVITY BUS ACTIVITY MASTER S T O P S SDA LINE FIGURE 7-3: CONTROL BYTE A C K N O A C K SEQUENTIAL READ CONTROL BYTE DATA n DATA n + 1 DATA n + 2 S T O P DATA n + X P SDA LINE BUS ACTIVITY A C K A C K A C K A C K N O A C K 8.0 PIN DESCRIPTIONS 8.3 8.1 SDA Serial Address/Data Input/Output This pin must be connected to either VSS or VCC. This is a Bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pullup resistor to VCC (typical 10KΩ for 100 kHz, 2 KΩ for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. 8.2 SCL Serial Clock WP If tied to VSS, normal memory operation is enabled (read/write the entire memory). If tied to VCC, WRITE operations are inhibited. The entire memory will be write-protected. Read operations are not affected. This feature allows the user to use the 24LC04B/08B as a serial ROM when WP is enabled (tied to VCC). 8.4 A0, A1, A2 These pins are not used by the 24LC04B/08B. They may be left floating or tied to either VSS or VCC. This input is used to synchronize the data transfer from and to the device. DS21051G-page 8 1999 Microchip Technology Inc. 24LC04B/08B NOTES: 1999 Microchip Technology Inc. DS21051G-page 9 24LC04B/08B NOTES: DS21051G-page 10 1999 Microchip Technology Inc. 24LC04B/08B 24LC04B/08B Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 24LC04B/08B – /P Package: Temperature Range: Device: P SL SN SM = = = = Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (207 mil Body), 8-lead Blank = 0°C to +70°C I = -40°C to +85°C 24LC04B 24LC04BT 24LC08B 24LC04BT 4K I2C Serial EEPROM 4K1 2C Serial EEPROM (Tape and Reel) 8K1 2C Serial EEPROM 8K 12C Serial EEPROM (Tape and Reel) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 1999 Microchip Technology Inc. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan’an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060 Italy 11/15/99 Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. 1999 Microchip Technology Inc.